Abstract: A method and apparatus for generating multiple locked self-timed pulsed clock signals is disclosed. Race margins are reduced over separate clock generating circuits by sharing the necessary delay circuit elements between the multiple clock generating circuits. An edge is gated with a delayed edge to form the first clock pulse. A subsequent second clock pulse is generated by gating a partially-delayed edge with the first clock pulse, which minimizes race margins and pulse evaporation.

Abstract: A method and apparatus for generating multiple locked self-timed pulsed clock signals is disclosed. Race margins are reduced over separate clock generating circuits by sharing the necessary delay circuit elements between the multiple clock generating circuits. An edge is gated with a delayed edge to form the first clock pulse. A subsequent second clock pulse is generated by gating a partially-delayed edge with the first clock pulse, which minimizes race margins and pulse evaporation.

Abstract: A GTL I/O transceiver circuit having a pulsed latch receiver. A pulse generator generate a first pulse and a second pulse within the first pulse in response to a rising edge of the bus clock. The first pulse turns on the differential amplifier of the receiver circuit just long enough to provide a valid amplifier output signal. The second pulse controls a tristate latch such that the value of the amplifier output signal is latched before the differential amplifier is turned off. The pulsed latch receiver turns the differential amplifier on for only a fraction of the period of the bus clock such that power dissipation of the pulsed latch receiver circuit is significantly reduced. By using the pulsed latch receiver in VLSI components having hundreds of I/Os, significant reduction in overall component power dissipation can be achieved and static DC power is eliminated. The GTL I/O transceiver is useful for interfacing VLSI CMOS components to a terminated bus.

Abstract: A latch circuit comprises a delaying inverter circuit 1 for inverting a clock signal CLK with a predetermined delay, a precharge circuit for precharging a first node A and a second node B of the latch circuit to a predetermined potential during a time period in which the clock signal is in a first logic level, a first amplifier circuit for providing a potential difference between the first node A and the second node B in response to an input signal DIN during a first time period in which the clock signal CLK and an output signal iCLK of the delaying inverter circuit are in a second logic level, a second amplifier circuit for amplifying the potential difference between the first node and the second node during a time period in which the clock signal is in the second logic level and a flip-flop circuit adapted to be set and reset according to the potentials at the first and second nodes.

Abstract: A method for resolving race conflicts in a loop circuit having a forward path and a feedback path includes enabling and disabling the feedback path in accordance with a phase waveform. The phase waveform may be a system clock, in which case one of two approaches may be used to ensure that data from the feedback loop arrives later in time than data from an input signal line. During the first approach, only the rising edge of a clock signal used to control data flow in the feedback loop is delayed relative to the rising edge of a clock signal that controls data flow in the forward path. During the second approach, both the rising and falling edges of the clock signal are delayed. Through these approaches, the method of the present invention achieves improved performance in terms of power consumption, frequency response, area, and switching capacitance.

Abstract: A substantially noise-free data input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates either a logical true or complement output signal representation of a data input signal and includes timing circuitry to delay an edge transition on the output signal for a predetermined period of time in response to a signal edge transition appearing on the data input signal. The input buffer further includes edge transition detection (ETD) circuitry for generating an initialization signal in response to the generation of the data output signal.

Abstract: Circuit for reducing a standby current, is disclosed, including a PMOS transistor connected to a power supply voltage terminal, an NMOS transistor connected to a ground voltage terminal, and a switching device between the PMOS transistor and the NMOS transistor for cutting off a leakage current flowing to the NMOS transistor through the PMOS transistor, whereby minimizing a leakage current and shortening a time period for going from a standby state to an active state.

Abstract: D flip-flop structures are provided which respond to a DATA signal and a clock (CLK) signal by generating an output signal whose state during each clock pulse is that of the DATA signal at that pulse's leading edge and whose state between clock pulses is reset to a selected logic value. Accordingly, these flip-flops can function (e.g., monitor events in the DATA signal or generate sequences of trigger pulses) at the clock rate.

Abstract: A dynamic flip-flop circuit that operates in a pre-charge phase and an evaluation phase allows for implementation of multiple-input logic functions without sacrificing performance by using a single evaluation path to generate its output signals. In one embodiment, the dynamic flip-flop circuit includes input logic that receives a clock signal and one or more data input signals. The clock signal defines the pre-charge phase and the evaluation phase of the flip-flop circuit. The input logic has an output terminal connected to a first output buffer circuit, which in turn drives the flip-flop circuit's Q output signal. The output terminal of the input logic is combined with the clock signal in a logic gate having an output terminal connected to a second output buffer circuit, which in turn drives the flip-flop circuit's complementary output signal {overscore (Q)}.

Abstract: The present invention provides a double edge trigger D-type flip-flop which can be both triggered at the rising edge and falling edge of a clock. That is to say, the double edge trigger D-type flip-flop of the present invention can access data twice in a clock cycle. Therefore, the double edge trigger D-type flip-flop of the present invention is capable of providing a double accessed data amount than that of a conventional rising (or falling) edge trigger D-type flip-flop, thereby significantly increasing the efficiency of the system.

Abstract: A timed bistable circuit is described which includes two inverters each having its input connected to the output of the other, an output of the circuit via a “buffer” and an input of the circuit via a controlled electronic switch. The supply terminals of the inverters are connected to the supply terminals of the circuit via another two controlled switches. A clock generator provides timing signals to control both the input switches to open or close and to control the supply switches to close or open when the input switches are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches between the supply terminals of the inverters and the supply terminals which are controlled by a timing signal in such a way as to close with a predetermined delay with respect to the closure of the input switches and to open when input switches open.

Abstract: An improved latch circuit having a dynamically adjustable internal feedback level. The improved latch circuit includes a latch inverter and a feedback inverter cross-coupled with the latch inverter. A controllable supplemental feedback inverter is connected in parallel with the feedback inverter to provide a controllable level of feedback to the latch inverter. An independently selectable control signal enables or disables the controllable feedback inverter in conformity with a need for more or less feedback, such that the internal feedback level may provide optimal functionality and performance of the latch circuit.

Abstract: A flip-flop circuit 10 is provided with a discord detecting circuit DDC and a clock control circuit CCC. The discord detecting circuit DDC detects the discord of a data input signal DIS of the flip-flop circuit 10 with a data output signal DOS thereof. When the data input signal DIS discords with the data output signal DOS, the clock control circuit CCC supplies a short pulse to the flip-flop circuit 10 as an internal clock signal ICLK in synchronism with the rising of an external clock signal ECLK. On the other hand, when the data input signal DIS coincides with the data output signal DOS, the clock control circuit CCC supplies a low level signal to the flip-flop circuit 10 as the internal clock signal ICLK. Thus, it is possible to suppress electric power consumption required to supply a clock signal, and to prevent errors from being caused in a flip-flop operation.

Abstract: A top clock stacked circuit is provided that substantially prevents charge sharing and that prevents any deleterious bipolar effect. The top clock stacked circuit comprises a primary pre-charge circuit coupled to a primary node, a first device coupled between the primary node and a first secondary node, and a second device coupled between the first secondary node and a second secondary node. A second pre-charge circuit is coupled to the first secondary node and a pre-discharge circuit is coupled to the second secondary node. In response to a first clock polarity, the primary and the second pre-charge circuits pre-charge the primary and the first secondary nodes, respectively, and the pre-discharge circuit pre-discharges the second secondary node. Thereafter, in response to a second clock polarity, the first device creates a path between the primary node and the first secondary node. Because both nodes are pre-charged to the same voltage, charge sharing is substantially prevented.

Abstract: A low power, high performance flip-flop includes a first branch having a number of transistors connected in series, and a second branch having a number of transistors connected in series. A clock signal and a data input signal are coupleable to the first and second branches of the circuit, the circuit generating a stable logic one or logic zero. The circuit has low power consumption and high performance speed.

Abstract: An input buffer and an input-output buffer in full compliance with IDDQ testability are provided, which use a signal fed back to a P-type or N-type controllable switch to turn on or turn off the switch so as to obtain a desired resistance by using an equivalent circuit for the buffer. The problem of reduced operating speed due to the use of a high-impedance resistor is then avoided. Hence, the IDDQ testing results will not be affected by using the input buffer or the input-output buffer, no matter the circuit is operated in an output mode or input mode. Furthermore, the input signal, either in the low state or in the high state, has no effect on the IDDQ testing results either.

Abstract: In a known bitable flip-flop, a first inverter stage (1) is driven by an input signal (D), a second inverter stage (2) by a clock signal (CLK), and a third inverter stage (3) by an output signal (INV2) of the second inverter stage (2). In order to buffer the output signal levels of the inverter stages, the first and third inverter stages (1, 3) can be switched into a disabling state by the clock signal (CLK) and the second inverter stage (2) by an output signal (INV1) of the first inverter stage (1). The new bistable flip-flop is to be set independently of the input signal. For setting the flip-flop, preferably of CMOS design, field-effect transistors (M10, M11) are provided in the third and second inverter stages (3, 2) which inhibit disabling of the third inverter stage (3) by a set signal (SET) and a signal (SETN) that is complementary to it and which allow disabling of the second inverter stage (2) independently of the output signal (INV1) of the first inverter stage (1).

Abstract: A dynamic latch receiver device comprises a sequence of data latch devices arranged in parallel for enabling sequential latching of data signals communicated serially on a single data line. The device includes a first pointer signal generator for generating a sequence of one or more first pointer signals, each generated first pointer signal of a sequence corresponding to a specific latch device and overlapping in time with a prior generated first pointer signal of the sequence; and, a pulse converter device associated with a latch device for receiving a corresponding first pointer signal and generating a respective second pointer signal for input to a respective latch device, each second pointer signal generated in a non-overlapping sequence for triggering a respective latching of each data signal in synchronism with serially communicated data signals.

Abstract: A single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes an input stage, precharge stage and buffer. The input stage is coupled to receive a data-input signal and a clock signal. During the precharge phase, the input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, the input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low. The precharge stage receives the output signal from the input stage and the clock signal. During the precharge phase, the precharge stage generates a logic high level output signal independently of the signal received from the input stage.

Abstract: An edge triggered latch has an improved transparency window, which is essentially the delay of the N-stack pull-down tree. This minimizes the delay yet guarantees that the circuit will have enough time to evaluate the input data, since the evaluation is limited by the pulse width. This circuit eliminates early mode failure for latches placed in series, without the requirement of delay padding.

Abstract: A method and device are disclosed for the reduction of the penalty associated with inserting a latch in a circuit which is utilized to implement an integrated circuit in a data-processing system. A semiconductor device is disclosed which includes a main latch circuit, a feedback latch circuit and an output terminal. The main latch circuit is capable of receiving an input data signal and an input clock signal. The main latch circuit generates a latch output signal in response to the input data and clock signals. The feedback latch circuit is capable of receiving the latch output signal from the main latch circuit and storing the latch output signal. The feedback latch circuit is capable of generating a feedback latch circuit output signal which is received by the main latch circuit to maintain the latch output signal. The output terminal of the device is coupled to the feedback latch circuit for outputting a device output signal which is equal to the feedback latch circuit output signal.

Abstract: A flip-flop including a first stage and a second stage. The first stage receives a pair of differential signals to generate a set and reset signal. The complement of the set and reset signal generates output signals Q and Q. These signals have equal rising and falling transitions with the same delays for the Q signal and the Q signal. The second stage has symmetrical pull-up and pull-down circuits.

Abstract: A prescaler system (100) has a prescaler circuit (102) coupled to a divider (104), wherein the divider includes an improved dynamic flip flop divider (118). The divider (118) includes a TSPC nine-transistor D-flip-flop (10). The divider further includes a tenth transistor such as N channel device (41) having a source coupled to ground (43), a drain coupled to a junction between a drain of a P channel device (34) and a drain of another N channel device (37). The divider also includes an eleventh transistor such as N channel device (42) having a source coupled to ground and a drain coupled to a junction between the drain of a P channel device (35) and the drain of a N channel device (39), the junction providing a feedback signal to a N channel device (36), wherein the eleventh transistor further has a gate coupled to the output signal (/Q.sub.A).

Abstract: A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

Abstract: A flip-flop circuit consists of a conventional pulse-drive flip-flop plus a clock driver and a local pulse generator that generates a pulse signal according to the output of the clock driver. The flip-flop circuits of this kind are used to form, for example, a shift register in which the clock drivers are connected in series from the last stage toward the first stage. The clock driver in the last stage receives a clock signal, which is successively supplied to the flip-flop circuits from the one in the last stage toward the one in the first stage. This arrangement prevents a data-pass-through problem, assures a sharp waveform of pulse signals, and reduces the size of each clock driver. This type of flip-flop circuits may be used to form logic circuits such as N-bit registers and N-bit shift registers.

Abstract: A high-speed flip-flop is provided that implements a low power consumption and a high-speed response caused by an interior capacitance reduction. A D flip-flop includes a first latch that receives a clock signal and a data signal to produce a first output signal. A second latch receives the first output signal and the clock signal to produce a second output signal. A third latch receives the second output signal and the clock signal to produce a third output signal. An inverter receives the third output signal to produce the data signal on a rising or falling edge of the clock signal. The first and second latches are preferably ratioed latches having series coupled pull-up and pull-down elements. The third latch is preferably a clock operated latch.

Abstract: A logic circuit includes an inverter for generating a complement of an output signal from another logic circuit for input to a dynamic logic circuit. The dynamic logic circuit is capable of receiving both the complement signal and dynamic input signals during both the precharge and evaluate phases of the dynamic logic circuit. The complement signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages with the dynamic logic circuit still capable of correctly evaluating the implemented logical operation of the dynamic logic circuit on the complement signal and the dynamic input signals. A p-channel FET is coupled between the internal precharge node and a voltage reference source where the gate electrode of the p-channel FET device receives the complement signal.

Abstract: A method of implementing a single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes receiving a data-input signal and a clock signal. During the precharge phase, an input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, an output signal that either remains at a logic high level or else transitions from high-to-low is generated by the input stage. The output signal and the clock signal are received by the precharge stage from the input stage. During the precharge phase, a logic high level output signal is generated the precharge stage independently of the signal received from the input stage.

Abstract: A CMOS latch circuit comprises a data input node, an output node, and first and second inverters, each of which have an input coupled to the data input node, and an output coupled to the output node. Pairs of feedback NFETs and PFETs are each coupled in series between V.sub.CC and ground. Intermediate nodes between each of the NFET and PFET feedback pairs are coupled to the data input node. The gate of the first feedback NFET is coupled to the data input node, and the gate of the second NFET is coupled to the output node. Similarly, the gate of the first PFET is coupled to the output node, and the gate of the second PFET is coupled to the data input node. The CMOS latch circuit maintains a logic state at the output node regardless of a high-energy particle strike.

Abstract: A method of implementing a scan flipp for use with logic gates includes configuring the flip-flop into a scan mode or data mode. Then the flip-flop enters the precharge phase in which a dynamic input stage is precharged and a static output stage maintains the output signal from the previous evaluation phase. During the evaluation phase in the normal mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. During the evaluation phase in the scan mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the scan input signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the evaluation phase, the static output stage outputs the complement of the output signal received from the dynamic input stage.

Abstract: A driver circuit which drives a signal line includes a first output section for outputting a reference voltage potential to the signal line during a first period and a second output section for outputting one of a first information voltage potential and a second information voltage potential in accordance with an input signal during a second period.

Abstract: A clock control circuit is provided in a flip-flop circuit, since a first clock signal supplied to a master latch circuit is generated by an OR logic between a reference clock signal and a skew adjustment clock signal, a second clock signal supplied to a slave latch circuit is generated in accordance with the reference clock signal, the first clock signal has a phase advanced from the second clock signal by exactly an amount of a skew margin. An input signal is fetched into the flip-flop circuit at the rising edge of the first clock signal, then is output at the rising edge of the second clock signal. By this, malfunction due to the clock skew is prevented. The flip-flop circuit can operate as in the normal mode by holding the skew adjustment clock at a logic "0".

Abstract: A flip-flop with enhanced support for dynamic circuits. The flip-flop comprises at least one data input node along with at least one inverting and at least one non-inverting output node. A clock input node receives an external clock signal and transmits it to a clocking unit which, in turn, generates a clock signal therefrom for gating an input signal received at the data input node. A storage unit holds the input signal value upon assertion of the clock signal and simultaneously transmits that value in appropriate logic level to inverting and non-inverting outputs. It is understood that the inverting and non-inverting outputs represent complementary signal values as is normally known in the art. The flip-flop further comprises a clear input node which is coupled to an edge-sensitive quiescent state control unit. A predetermined logic state transition, i.e.

Abstract: A dynamic CMOS register implemented on a silicon die that requires the use of only two input signals, a data-in signal and an inverse clock signal. Each embodiment includes a self-timed clock circuit having a CMOS PNN tier of FETs with a P channel and two N channels connected serially (sources of P channel at one end connected to bus and N channel at the other end connected to ground, and gate of end N channel connected to bus), a first inverter to receive inverse clock with output connected to gate of P channel, a second inverter connected to drain of P channel, and a NOR gate with one input receiving inverse clock, second input connected to output of second inverter and output connected to gate of center N channel. In one embodiment, a single self-timed clock circuit interfaces with and controls a plurality of CMOS registers.

Abstract: A flip-flop circuit for use with logic gates includes a dynamic input stage and a static output stage. The flip-flop receives a single phase which defines a precharge phase and an evaluation phase. The dynamic input stage has a NMOS logic block coupled to receive one or more data signals. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the evaluation phase, the NMOS logic block of the dynamic input stage causes the dynamic input stage to generate an output signal that either remains at a logic high level or else transitions from high-to-low by performing a logic operation of the data signals. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage.

Abstract: A single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes an input stage, precharge stage and buffer. The input stage is coupled to receive a data-input signal and a clock signal. During the precharge phase, the input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, the input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low. The precharge stage receives the output signal from the input stage and the clock signal. During the precharge phase, the precharge stage generates a logic high level output signal independently of the signal received from the input stage.

Abstract: A single phase edge-triggered staticized dynamic flip-flop circuit for use with dynamic logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is coupled to receive a data signal and a clock signal. During the precharge phase, the dynamic input stage provides an output signal that is the complement of the data signal. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the evaluation phase, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage.

Abstract: An unbuffered flip-flop includes feedback control circuitry providing adaptive control of the internal node during the transfer and latching phases of the flip-flop to prevent back-writing. A complementary pair of transmission gates controlled by the output node are included in the feedback path between an output buffer and a feedback buffer. As noise voltage variations and spikes alter the voltage on the output node, the charge transmittance of the transmission gates is weakened or shut off, thereby preventing the incorrect logic state from being driven by the feedback buffer through to the input of the flip-flop's output buffer and causing back writing. Because the transmission gate transistors are complementary, one transistor or the other will be operating in a transmissive state for each of the bi-stable states of the output buffer during static operation of the flip-flop.

Abstract: A power reduction system for a UART system having a controllable oscillator for producing free-running clock signals. A controlled clock synchronizer having an output terminal is coupled to the oscillator and responsive to both a first control signal thereto and application of the free-running clock signals thereto to provide synchronized pulses and is responsive to both a second control signal different from the first control signal thereto and application of the free-running clock signals thereto to cease production of the synchronized pulses at the output terminal. A UART core controls the oscillator and the clock synchronizer and is operated under control of clock signals from the clock synchronizer. The controllable oscillator includes an inverter having a feedback circuit thereacross including a switch responsive to the third control signal to cause the oscillator to cease oscillation.

Abstract: A dynamic latch circuit or a dynamic flip-flop circuit of the present invention includes a transfer gate to be controlled by a clock and provided with a complementary configuration using a P-channel and an N-channel MOS (Metal Oxide Semiconductor) transistor. The transfer gate allows the individual node included in the circuit to fully swing between a high potential power source and a low potential power source. This causes a minimum of decrease to occur in an ON current for driving the respective node and thereby realizes high-speed operation. Further, the balance of the rising time and falling time of an output signal is improved, reducing the deviation of the duty of the output signal from 50%. The circuit is therefore operable with sufficient operation margins at positive- and negative-going edges. Consequently, the entire macrocircuit using the circuit of the present invention can have its operation frequency and therefore power consumption lowered.

Abstract: A staticized flop circuit converts a dynamic signal appearing across the output of a logic circuit into a static signal, and includes a dynamic-to-static convertor which minimizes glitching in the static output. The dynamic-to-static convertor includes a pull-down device, operatively coupled between an output node and a ground, which is closed while an input node is at a precharge potential and which is open while the input node is at a ground potential, and a pull-up device, operatively coupled between a source voltage and the output node, which is closed while the input node is at the ground potential and which is open while the input node is at the precharge potential.

Abstract: A flip-flop circuit with scan circuitry for use with static logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is coupled to receive a data signal, a scan input signal, a scan enable signal, a data enable signal and a single-phase clock signal. During the precharge phase, the dynamic input stage provides an output signal that is the complement of the data or the scan signal. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage. During the evaluation phase in the normal mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal.

Abstract: In a level conversion circuit where the input signal is input via a flip-flop which sets its output in a high impedance state during the holding state, by adding a circuit which sets the output voltage to a predetermined potential level when the output of the flip-flop is in a high impedance state, the leakage current is reduced and a clock skew is prevented, to result in a stable operation of the level conversion circuit.

Abstract: A master portion may introduce input data thereinto in a low level period of a clock and then hold and output the input data therefrom in a high level period of the clock. A slave portion may introduce input data thereinto in the high level period of the clock and then hold and output the input data therefrom in the low level period of the clock. Two exclusive NOR circuits may compare present logic values of the input data with logic values in a preceding half period of the clock to determine coincidences therebetween respectively, and then control output states of the input data held in the master portion and the slave portion based on results of their comparisons.

Abstract: The present invention is a novel and improved method and apparatus for implementing a latch within an integrated circuit. Data is stored on a storage node via the application of either a first or second state logic source applied through a feedback inverter that maintains the storage node at a particular logic state. During logic transitions from a first state to a second state the storage node is decoupled from the first state logic source via the use of a gating circuit, and the new logic level is applied to the storage node. During logic transitions from the second state to the first state the storage node remains coupled to the second state logic source. The coupling and decoupling of the storage node from the first state logic source is performed via the use of a clock signal that has a non-overlapping cycle with respect to a second clock signal that is used to control the transitions of the state of the latch.

Abstract: A latch circuit has an enable circuit responds to clock pulse levels of a first polarity by outputting an enabling voltage of a second polarity opposite to the first polarity. The latch circuit also has first and second inverters which each have an output, a first biasing input connected to a first polarity voltage, a first input, a second a biasing input receiving the enabling voltage from the enable circuit and a second input. When enabled by the enabling voltage, each inverter drives its respective output to a voltage of the first polarity in response to receiving a signal of the second polarity at its first input. Alternatively, when enabled, each inverter drives its respective output to a voltage of the second polarity in response to receiving a signal of the first polarity at its second input. The first input of the first inverter receives, between the leading and trailing edges of the first polarity clock pulse levels, a signal to be stored.

Abstract: A timed bistable circuit is described which includes two inverters each having its input connected to the output of the other, an output of the circuit via a "buffer" and an input of the circuit via a controlled electronic switch. The supply terminals of the inverters are connected to the supply terminals of the circuit via another two controlled switches. A clock generator provides timing signals to control both the input switches to open or close and to control the supply switches to close or open when the input switches are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches between the supply terminals of the inverters and the supply terminals which are controlled by a timing signal in such a way as to close with a predetermined delay with respect to the closure of the input switches and to open when input switches open.

Abstract: The present invention provides a latching mechanism for use in high-speed domino logic pipestages. The latching mechanism allows time borrowing across latch boundaries, provides sufficient hold time for the output to be sensed by the next stage, and provides a circuit configuration in which race conditions related to the latching mechanism have inherent positive margin. The latching mechanism of the present invention is applicable to fully self-resetting domino logic, globally resetting domino logic, or any combination thereof. The latching mechanism is a set dominant latch having its set input driven by the output of the last domino logic gate in a pipestage, and having its reset input driven by the output of the last domino logic gate in a pipestage ANDed with a delayed version of the pulsed clock that triggers the domino chain of the pipestage.

Abstract: A status latch with one-phase control signal is constructed only from purely static gates, thus has great security against interference in the stationary state, and is thus suited in particular for low-voltage operation. In the one-phase latch, the power loss is particularly low due to the lower wiring capacity of the control lines, for which reason it can be advantageously used in particular in digital circuits with high data rates. Advantageously, a low number of transistors is required.

Abstract: A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially setup and clock-to-output times. The flip-flop consumes no static power.