Abstract: A high speed capture latch includes differential data inputs, a latch clock input, a boost clock input, a current steering circuit, a switched current source, a latch element and first and second boost current sources. The current steering circuit has first and second differential control terminals which are coupled to the differential data inputs and control current through first and second current paths, respectively. The switched current source is coupled between the current steering circuit and a first voltage supply terminal and has a control terminal coupled to the latch clock input. The latch element is coupled between a second voltage supply terminal and the current steering circuit and provides a latch output. The first boost current source is coupled to the first current path between the latch element and the current steering circuit and has a control terminal coupled to the boost clock input.

Abstract: A method of identifying potential clock qualifiers in netlist description of an integrated circuit, the netlist comprising logic elements. The method comprises the steps of initializing every net of the netlist to a speed of zero, identifying all potential clock nets so that all signals with a path to a clock source has a speed of one, computing the maximum speed of each output net of each of the logic elements in the netlist, and marking as a potential clock qualifier any net of the netlist that is input to the logic elements in the netlist that is slower than the maximum speed of any net that is input to the logic elements.

Abstract: A method and circuitry are provided for latching information. The information is selectively transferred from a selected one of: a first node (DIN) to a second node (416); and a third node (SIN) to a fourth node (419a-b). The transferred information is selectively latched by coupling the second node (416) to the fourth node (419a-b) in response to a signal (308, 410).

Abstract: A logic circuit is described. The logic circuit generates a first signal state in response to a first set of input signals, generates a second signal state in response to a second set of input signals, activates a bypass switch in response to the first signal state, and bypasses a domino logic unit in response to the first signal state.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: A flip-flop circuit has a master circuit including a static flip-flop with a feedback loop, and a slave circuit including a dynamic flip-flop. In the flip-flop circuit, a clock signal is applied to the master circuit and the slave circuit. A clock width of the clock signal is determined by a time period from a clock edge for taking data into the master circuit to another clock edge for closing the master circuit, and is set to less than a given time period.

Abstract: A circuit (51) for converting a pair of precharged dynamic logic signals into a static logic signal includes a first input (61) to receive one of said dynamic logic signals, a second input (67) to receive the other of said dynamic logic signals, and an output (Qout). A first signal path from said first input to said output includes only two logic gates (63,69), and a second signal path from said second input to said output includes only one logic gate (69).

Abstract: A scan cell is described which can function as either a positive edge triggered latch or a double edge triggered latch during normal functional operation of circuitry to be scan tested. It functions only as a positive edge triggered latch when scan testing of a logic structure is to be performed.

Abstract: A scan flip-flop includes a data input, a scan input, a mode selection input, a mode control input and a clock input. When the mode selection input is set to a first selection value, and the mode control input is set to a first control value, the scan flip-flop operates as a D flip-flop. When the mode selection input is set to a second selection value, the scan flip-flop shifts in a scan input value on the scan input when one of the mode control input and the clock input is toggled. Also, as long as the mode selection input is set to the first selection value, and the mode control input is set to a second control value, the scan flip-flop holds a current value within the scan flip-flop.

Abstract: A self-enabling latch includes a pair of pass transistors, a pair of cross-coupled inverters, an EXCLUSIVE-NOR logic gate and a differential amplifier. The pass transistors receive a differential input data signal which is selectively latched by the cross-coupled inverters. The EXCLUSIVE-NOR logic gate also receives the input data signal and compares it with the latched data signal to provide a control signal for the amplifier. The control signal is active when the present input data is different from the previously latched data. The amplifier, enabled by the active control signal, amplifies a differential clock signal to provide an enabling signal for the pass transistors which thereby present the new input data to the cross-coupled inverters for latching.

Abstract: A scan flip-fop is designed to hold the state of the slave latch during scan shifting. This allows an ATPG tool to develop robust delay path tests using combinational scan flip-flop models. Combinational scan flip-flop models suffice because the launch can be done in the cycle before test enable goes active and capture can be performed during the cycle in which test enable is active. Thus, multiple clocks during the capture cycle are not necessary and, therefore, sequential delay path ATPG is not necessary. It is only necessary for the ATPG tool to store the last parallel vector in a buffer. The dynamic latch used for the scan slave latch is made small and slow, thereby increasing the delay along the data path during shifting, making the cell immune to hold time violation for any reasonable amount of clock skew.

Abstract: A sample and hold flip-flop that includes a clock buffer circuit responsive to a first clock signal for producing a second clock signal and a third clock signal, wherein the second clock is delayed inverted replica of the first clock and wherein the third clock is a delayed inverted replica of the second clock signal; a CMOS inverter having an input and an output, wherein the output of said CMOS inverter forms the output of the sample and hold flip-flop; a first MOS transistor of a first type having a gate terminal connected to the first clock signal and a drain terminal connected to the input of the CMOS inverter; a second MOS transistor of the first type having a gate terminal connected to the second clock signal and a drain terminal being connected to the source terminal of the first MOS transistor of the first type; a first MOS transistor of a second type having a gate terminal connected to the second clock signal and a drain terminal connected to the input of the CMOS inverter; a second MOS transistor of

Abstract: A storage element responsive to static and dynamic input signals which generates complementary static and dynamic output signals and incorporates scan test logic. The invention includes a first circuit for receiving dynamic and static input signals and providing static output signals in response thereto and a second circuit connected to the first circuit for providing dynamic output signals. In the illustrative embodiment, the first circuit includes a static flip-flop constructed with a multiplexer, a static input (master) latch and a static output (slave) latch. The static input latch provides first and second intermediate complementary outputs on first and second intermediate output terminals respectively.

Abstract: A latch, connected between an input self-reset dynamic MOS logic circuit and an output self-reset dynamic MOS logic circuit, is provided with clocked interface circuitry to assure proper latching of the state of the input logic in the latch and provides a pulsed output to the output logic circuit. Circuitry is provided to control the self-reset operation of the input logic circuit such that the reset does not occur until a predetermined period of time after the leading edge of the clock pulse latching the state of the input self-reset circuit in the latch. The output of the latch is gated from the latch to the output self-reset circuit under the control of a chopper circuit. The chopper circuit provides a control pulse to gate the state of the latch to the output self-reset circuit a predetermined period of time after the data has been latched. The control pulse has a duration sufficient to assure that the state of the latch is registered in the output self-reset logic.

Abstract: A device which includes a plurality of master/slave stages, each master/slave stage includes a master segment and at least one slave segment. Each master segment (excluding the one including a first master/slave stage) may be actuated by either external logic during normal operation, or by the output of a preceding slave segment during a scan operation. A continuous single phase clock provides clocked signals to a scan port, as well as the master segment and the slave segment in each of said master/slave stages. A control portion deactivates logic applied to the master segments, and actuates logic applied from the scan port to said master segments during all scan enable periods. The control portion also deactivates the scan port from the master segment, and activates the logic output to the master segments during all normal operation periods.

Abstract: A flip-flop circuit includes a first switch for controlling passing of input data in response to a single clock signal, a first inverter for inverting the data passed through the first switch, a second inverter for inverting the data output from the first inverter into inverted data and for inputting the inverted data to the first inverter, a second switch for controlling passing of the data output from the first inverter in response to the single clock signal, a third inverter for inverting the data passed through the second switch, and a fourth inverter for inverting the data output from the third inverter into inverted data and for inputting the inverted data to the third inverter, where the first inverter has a driving capability larger than that of the second inverter, and the third inverter has a driving capability larger than that of the fourth inverter.

Abstract: A flip-flop circuit for driving an input circuit of a synchronous dynamic random access memory (SDRAM) including a complementary pair of data inputs for receiving data pulses, a clock input for receiving clock pulses, a capture latch circuit for capturing a bit, having a pair of complementary inputs and a pair of complementary outputs, apparatus for applying data pulses from the complementary data inputs to the inputs of the capture latch, apparatus for triggering the capture latch from the clock pulses, and apparatus for connecting the complementary outputs to each other through a bidirectional holding latch, whereby during coincidence of a rising edge of a clock pulse and the presence of a data pulse of one polarity, the capture latch is enabled to store a bit corresponding to the data pulse, and to drive the pair of complementary outputs, and following the leading edge of a clock pulse and the one polarity of the data pulse the complementary outputs remain driven by the holding latch.

Abstract: In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.

Abstract: A general object of the present invention is to provide a latch of which demand is small. In a half-latch 101, control signals T2 and T2C which vary at late timings are applied to a main unit for data input (update) operation while control signals T1 and T1C which vary at early timings are applied to a feedback unit for data retaining operation. The data input (update) operation is never started until the data retaining operation is completed. The data retaining operation is practiced by retaining two signals having a negative logic relation with each other in a loop made up with two inverters. A signal related to retension of data and a signal newly input never reside in the same signal line. Thus, collision of those signals is avoided, and consequently, through-current due to the collision of the signals can be reduced.

Abstract: A flip-flop circuit is described which comprises of a dynamic master which stores a signal by maintaining a charge representing the signal. It also comprises of a static slave which stores a signal by switching to a voltage potential representing the signal. A clock line is coupled to the master and the slave carrying a clock signal to control the master and the slave.

Abstract: A clocking scheme provides for an improved latching of an output from a domino circuit by delaying a precharging of a domino node. The precharging delay is achieved by introducing the delay in the clocking circuitry which activates the precharging of the domino node. No delay is introduced in the data path in order not to delay the evaluation and transmission of the data signal. During one phase of a clocking cycle, the domino node is precharged to a predetermined logic state. Also during this precharge phase, an input latch couples an input data signal to the domino circuit. During the other phase of the clocking cycle, the domino circuit performs a logic operation based on the input signal. Also during this evaluation phase, an output latch latches the logic state of the domino output for transmission from the output latch.

Abstract: A storage element is provided in a circuit arrangement for latching one bit. A first MOS transistor (T1) is provided which, when a first control signal (S1) is present, switches an input signal corresponding to the bit to the input of the storage element. The storage element is provided with circuit elements by which an output signal at the output of the storage element is brought to a predetermined potential in dependence on the level of the input signal. The circuit arrangement is particularly suitable for constructing an address latch for DRAMs, particularly of the 16-M generation.

Abstract: A high speed processing flip-flop contains a header circuit and a pulse flip-flop circuit. The header circuit is a clock pre-processing circuit that generates clock pulses for operation of the pulse flip-flop circuit, and the pulse flip-flop circuit is a single stage latch. The header circuit contains functional logic including the flip-flop functionality for the high speed processing flip-flop, and any additional processing functions, such as multiplexing. The header circuit also contains a pulse modulator that generates selected clock pulses, based on the functional logic, for the pulse flip-flop circuit. The pulse flip-flop circuit contains storage, a driver circuit, and, for each data input, an input buffer, and a pass gate. The pulse flip-flop circuit couples the data to the driver circuit and storage during an active clock pulse for the corresponding data. Consequently, data input to the pulse flip-flop is not delayed by logic processing.

Abstract: A select line scanner for a liquid crystal display includes a plurality of cascaded stages each having an input terminal and an output terminal. Each stage includes a push-pull output circuit including pull up and pull down transistors driven with separate control signals. A further transistor has its conduction path coupled between the control electrode and a point of potential of sufficient value to turn the pull up transistor off. The control electrode of the further transistor is coupled to an output of a succeeding one of the cascaded stages to insure that the output of the respective stage cannot drift to an on state.

Abstract: In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.