Abstract: A novel 2/3 full-speed divider operating at high speed with low power consumption comprising a ECL D flip-flop in master-slave configuration and a phases-selection block is provided in the present invention. The master latch and slave latch comprise a pair of input terminals, a pair of control terminals, and a pair of output terminals. The master latch further comprises two pairs of complementary cross-couple transistors for amplifying the output of the master latch for entering the phase-selection block. The phase-selection block has a pair of input terminals, a clock signal input terminal, and an output terminal generating an output signal adjusted by a division ratio according to the clock signal. The division ratio is either 1/2 or 1/3 and the divider functions as a 2/3 divider.

Abstract: A binary digital logic level sensitive latch comprising a first inverter that provides an output (O1). At least one input signal (I1) and an activation signal (Clk) are provided to the first inventer both being capacitively coupled to an input of the first inverter and a switching threshold of the first inverter. The capacitance of the couplings being predetermined such that the output of the first inverter (O1) is a NOR function of the inputs signals and the activation signal O1={overscore (I1+Clk)}. A second inverter has as inputs capacitively coupled the output of the first inverter (O1), the activation signal (Clk) and an inverted pervious output signal (P) to provide output (O2). A switching threshold of the second inverter and the capacitance of the couplings being predetermined such that the output of the second inverter (O2) takes the function of: O2={overscore ((Clk×P)+O1)}.

Abstract: A high-speed, current-driven latch is provided. The latch conducts a current and includes an output, a SET circuit and a RESET circuit. The output is variable between a first state and a second state. The SET circuit conducts the current present in the latch at the first state such that the SET circuit is maintained close to a level required to change the output of the transistor from the first to the second level, and the RESET circuit conducts the current at the second level such that the RESET circuit is close to a level required to change the output of the transistor from the second level to the first level.

Abstract: A flip-flop circuit comprising a first stage having a transmission gate to receive a data signal from an input node, and a second stage connected to the first stage, the second stage having another transmission gate to transfer the data signal to a memory unit, wherein the memory unit provides complementary output signals.

Abstract: A new D-type latch structure is disclosed which has an input data sampling circuit and a symmetrical cross coupled latching circuit. The clock is delayed a predetermined time through an inverter circuit. The clock and the delayed inverted clock are used to generate a clock window time during which time the data input state and the inverted data input state are asserted on the latch output and complementary. The latch outputs are cross-coupled to pull-up and pull-down circuitry in each output circuit stage. A common pull-down transistor may be used to further reduce devices and to improve path delays from clocks to the latch outputs. The clock window assertion of states of the data inputs to the changing latch output is enhanced by the cross-coupled feedback of the latch outputs to improve the differential transition timings of the latch outputs. The D-type latch has fewer transistors and better delay, and more precise transition skew over prior art designs.

Abstract: An electronic circuit with digital output including an auto-stable assembly of latches (1), a control assembly (2), a blowable assembly (3), a logic gate (4) including a first input connected to a common point (14) between the auto-stable assembly (1) and the blowable assembly (3), and a second input connected to the control input (20) of the electronic circuit. A breaker (5) is controlled by the output of the logic gate (4) and arranged between the auto-stable assembly (1) and ground, and an associated process.

Abstract: A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data input signal. The first input latch has a first shutoff mechanism and the second input latch has a second shutoff mechanism. During a precharge phase, the first and second input latches each provide an output signal. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal if a compare enable signal is activated. The shutoff mechanisms as well will then only activate if the compare enable signal is activated. This allows the circuit to save power because flip-flop will not execute a compare during each clock cycle.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A dual level voltage shifter includes several series connections of transistors, and cross coupled pairs of transistors, to provide dual-level voltage shifting with low power consumption and low static current. In another embodiment, a dual level voltage shifter includes an inverter with current limiting diodes, and cross coupled inverters with a pass gate in their feedback loop, also providing low power consumption and low static current.

Abstract: A multiple input set/reset circuit is described that includes cross-coupled inverters connected between set and reset nodes. The set/reset circuit also includes at least one set input circuit coupled to the set node configured to receive a set signal and to drive the set node to a first logic state in response to the set signal asserted, and at least one reset input circuit coupled to the reset node configured to receive a reset signal and drive the reset node to the first logic state in response to the reset signal asserted. Incorporated into the set/reset circuit are a first switching circuit to change the logic state of one of the nodes to a second logic state when the other node changes the logic state to the first logic state, and a second switching circuit to disable the first switching circuit after the first and second nodes have completed a logical state change in response to a set or reset signal asserted.

Abstract: A method for resolving race conflicts in a loop circuit having a forward path and a feedback path includes enabling and disabling the feedback path in accordance with a phase waveform. The phase waveform may be a system clock, in which case one of two approaches may be used to ensure that data from the feedback loop arrives later in time than data from an input signal line. During the first approach, only the rising edge of a clock signal used to control data flow in the feedback loop is delayed relative to the rising edge of a clock signal that controls data flow in the forward path. During the second approach, both the rising and falling edges of the clock signal are delayed. Through these approaches, the method of the present invention achieves improved performance in terms of power consumption, frequency response, area, and switching capacitance.

Abstract: A body voltage controlled semiconductor integrated circuit which can solve a problem of a conventional CMOS inverter in that it cannot operate at a supply voltage beyond the built-in voltage of the CMOS transistors if their body electrodes are each connected to their own gate electrodes rather than to their source electrodes to quicken the operation of the CMOS inverter. A voltage divider circuit is provided which conducts during the operation of the CMOS transistors of the inverter so that the body voltages of the PMOS transistor or the NMOS transistor of the inverter is varied in the direction of reducing their threshold voltages. By controlling the size of electrodes and the voltages applied to the body electrodes of transistors constituting the voltage divider circuit, it becomes possible to operate the CMOS inverter at the supply voltage beyond the built-in voltage.

Abstract: A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

Abstract: An improved voltage level shifting circuit which is capable of increasing a level shifting speed and reducing a current consumption and layout area by decreasing a pull-up capacity of the pull-up PMOS transistors in a side in which a voltage level is shifted to a low level and increasing a pull-up capacity through the NMOS transistors in a side in which a voltage level is shifted to a high level.

Abstract: According to the preferred embodiment of the present invention pull-up/pull-down circuits are provided that use transistors with different threshold voltages to assure power-up to the correct predetermined state. These circuits have the ability to hold a node up or down while drawing very little DC current. In one embodiment a pull-up/pull-down circuit is provided that powers up to a first state with the pull-up node high and the pull-down node low, and that can be toggled from one state to another. A second embodiment provides a pull-up or pull-down circuit that powers up to the desired state and can be disabled by pulling the pull-up node low or pulling the pull-down node high. The circuits remain disabled until the power to the circuit is cycled.

Abstract: A scalable level shifter which performs at high-speeds and optimizes power consumption. The scalable level shifter receives an input signal and converts the input signal having a scalable voltage level to an output signal having a predetermined voltage level. The scalable level shifter includes a self-resetting circuit connected to an internal power supply for interrupting an internal current path responsive to output signal voltage variations corresponding to voltage transitions of the input signal.

Abstract: A meta-hardened circuit that reduces the effects of metastability preferably includes a pulse generator coupled to receive a first clock signal and generate in response thereto a second clock signal and an enable signal. A buffer, preferably tri-state, is coupled to receive a first data signal and the enable signal and generate in response thereto a second data signal. A bi-stable device, such as a flip-flop, is coupled to receive the second clock signal and the second data signal. The pulse generator preferably includes a combining device and a delay device. The buffer preferably includes at least one tri-state inverter and a keeper circuit. A method to reduce the metastability effects preferably includes the step of generating a delay between a second data input signal and a second clock signal that is greater than a delay between a first data input signal and a first clock signal. The step of generating preferably occurs in one clock cycle.

Abstract: The present invention provides a power amplifier operating with a single power supply. The amplifier includes at least one depletion-mode FET for amplifying an ac signal and a negative voltage generator for providing a bias to the FET. Preferably the amplifier further includes a negative voltage regulator to provide a regulated bias to bias the FET for a class A, AB or B operation. The negative generator includes a multivibrator for producing two clock signals and a charge pump which receives the clock signals and produces a negative voltage. Advantageously the negative voltage is provided as a low reference potential to the multivibrator so that the clock signals it produced include a negative voltage period, which enables the charge pump to operate in a power efficient manner.

Abstract: A D-type latch circuit includes a first differential amplifier circuit which receives first and second input signals having a complementary relationship and has an active state in a transfer operation and an inactive state in a latch operation. A second differential amplifier circuit receives first and second output signals having the complementary relationship and has an inactive state in the transfer operation and an active state in the latch operation. An output circuit receives output signals of the first differential amplifier circuit and outputs them as the first and second output signals in the transfer operation and receives output signals of the second differential amplifier circuit and outputs them as the first and second output signals in the latch operation. A negative feedback circuit feeds the first and second output signals back to predetermined nodes of the D-type latch circuit.

Abstract: A circuit combines the functions of a logic gate and a latch to lower steady state power dissipation during gate operation. The circuit operates in two modes: a flow-through mode and a latched mode. In the flow-through mode, a gate portion which receives one or more digital input signals implements the complement of a desired Boolean logic function on the input signals and provides an internal signal. The gate portion may have a steady-state power dissipation while providing the internal signal. An inverter in a latch portion of the circuit inverts the internal signal to generate an output signal which represents the desired logical combination of the input signals. The inverter provides the output signal with a full-range CMOS voltage. In latched mode, the gate portion is disabled to stop the steady-state power dissipation while the latch portion of the circuit preserves the desired output signal.

Abstract: A first output buffer circuit with independent transparent latch and tristate output capabilities includes input translators that directly drive a pair of main pull-up and pull-down output transistors. The input translators are tristatable in response to latch control signals and latching elements on side branches of the signal paths leading from the translator outputs to the output transistor gates hold the last voltage value on those signal paths at the time the translators are disabled. The main current paths through the output transistors include isolation transistors in series with the output transistors and responsive to feedback control from the buffer output. These feedback paths include logic gates responsive to output enable control signals that can shut off isolation transistors and hence put the buffer output in a high impedance state.

Abstract: A fast data transmission circuit for a semiconductor memory minimizes voltage variations of a data transmission line without the use of a separate data transmission voltage. The data transmission circuit includes a pair of input nodes, a data transmission line pair, a pair of sensing nodes, a pair of output nodes, and a control electrode. Prior to data transmission, the output nodes are pulled up to a high voltage state, the data transmission line pair is pulled down to a low voltage state, and the sensing nodes are held between the high and low voltage states. When the control pulse is applied to the control electrode, the sensing node voltage levels are transferred to the data transmission line pair by the sensing voltage transfer circuit. When one input node is pulled to a low voltage state, a corresponding one voltage level on one transmission line is changed, causing a corresponding change of voltage at one of the sensing nodes.

Abstract: A double edge triggered flip-flop is made up of six switches and four inverters. The input data is supplied to one end each of first and second ones of the six switches, the other ends of the first and second switches being separately connected to the inputs of a first and second of the four inverters. The outputs of the first and second inverters are separately connected to the input of the third and fourth inverters via the third and fourth switches. The third inverter serves as a common feedback inverter with the output of the third inverter is connected through the fifth and sixth switches to respective ends of the first and second switches, and the output of the fourth inverter forms the output of the present invention. The first, third, and fifth switches thus form the up-loop for the double edge triggered flip-flop and the second, fourth, and sixth switches forming the down loop, with the two loops sharing the third and fourth inverters.

Abstract: The present invention discloses an improved latch circuit. In the latch circuit, a composite gate takes in a basic clock signal and a delayed clock signal which is delayed by a delay circuit for a specific amount with respect to the basic clock signal, and puts out to a second drive circuit a first signal identical in waveform with the basic block signal, and further puts out to a first drive circuit a second signal that is delayed in the rising timing with respect to the first signal. As a result of such arrangement, when a transition is made from a feedback period during which an input switch has an off state while a feedback switch has an on state to a sampling period during which the input switch has an on state while the feedback switch has an off state, neither the input switch nor the feedback switch has an on state.

Abstract: The power consumption of a flip-flop circuit is reduced and an output magnitude is increased to prevent a malfunction from occurring often. In order to reduce the power consumption, an emitter-coupled logic with series gating is used for the master latch of the flip-flop circuit. A series gating is not used but an ECL having transistors connected in parallel is used for the gates of a slave latch so as to increase the output magnitude.

Abstract: A variable delay circuit capable of changing delay time includes a latch circuit constituted of a pair of inverters cross-coupled to each other and a transistor serving for reducing voltage difference between two inputs of the latch circuit based on a control signal given thereto. The control signal is also supplied to a pair of transfer gates to control the delay time of the variable delay circuit. The latch circuit has two inputs, between which the transistor is coupled, coupled to the respective transfer gates' ends, at which buffers are respectively coupled to feed output signals. When the control signal reaches a high level, the state of the transistor becomes one of low impedance, so that the voltage difference between the two inputs of the latch circuit is reduced, and so that the state of the latch circuit can be quickly and easily changed with little energy.

Abstract: A self-enabling latch includes a pair of pass transistors, a pair of cross-coupled inverters, an EXCLUSIVE-NOR logic gate and a differential amplifier. The pass transistors receive a differential input data signal which is selectively latched by the cross-coupled inverters. The EXCLUSIVE-NOR logic gate also receives the input data signal and compares it with the latched data signal to provide a control signal for the amplifier. The control signal is active when the present input data is different from the previously latched data. The amplifier, enabled by the active control signal, amplifies a differential clock signal to provide an enabling signal for the pass transistors which thereby present the new input data to the cross-coupled inverters for latching.

Abstract: A flip-flop circuit is described. The flip-flop circuit receives the data signal from a data input, receives a trigger signal from a trigger input, generates a pulse signal in response to an edge in the trigger signal, and stores the data signal in response to the pulse. Alternatively, the flip-flop circuit receives a data signal through a data input, receives a trigger signal through a trigger input, stores the data signal in a latch, and suppresses the trigger signal to the latch when the data signal stored in the latch corresponds to the data signal received through the data input.

Abstract: Output signals from a plurality of self reset CMOS a logic circuits are multiplexed by means of the plurality of input multiplex circuits and an output circuit. The multiplex circuits are individually enabled by means of a select lead and true and complement input signals to the multiplex circuits are supplied to input terminals of an output circuit in which the state of the true or complement input is latched to provide a static output. The inputs to the output circuits simultaneously provide an output and initiate the setting of the latch by means of a separate latch setting gate. An inverter tree within the output circuit maintains the state of the output on the output terminal of the output circuit after the latch has been reset. A test access to the output circuit allows a test signal to be gated into a test latch and subsequently gated into the primary latch of the output circuit to provide a test output.

Abstract: A semiconductor integrated bipolar flip-flop circuit prevents or suppresses erroneous operation arising from a current induced by external noise and flowing through a parasitic capacitance associated with a p-type diffused resistor. The semiconductor integrated circuit includes bipolar transistors that are directly involved with set and reset operations of the flip-flop circuit having bases connected to a two-stage inverter including bipolar transistors so that the bases of the bipolar transistors involved in setting and resetting are not connected directly to a p-type diffused resistor.

Abstract: A differential latch circuit which places very little capacitance on the clock line is described. The invented differential latch circuit utilizes differential data signals, and thus, has two data lines. The transfer portion of the latch receives the differential data signals and passes them to the storage portion responsive to a control signal. The storage portion stores and outputs the differential data signals. In a first embodiment, each data line in the transfer portion comprises a single transistor pass gate for selectively passing one of the differential data signals responsive to the control signal, which is coupled to the gate terminals of both pass gates.

Abstract: A flip-flop having a master section including two switching transistors is provided with output loading transistors to drive the two transistors into saturation in the event of a metastable condition causing input is present. By driving the switching transistors into saturation they become inactive and background noise cannot cause proprogation of the metastable condition to subsequent flip-flip stages.

Abstract: A control circuit for a multiplexer includes two inverters, and exclusive-NOR gate, and a d-type flip-flop. The multiplexer has two input terminals and two selection terminals, and the control circuit has two input terminals. One of the two inverters is connected in circuit between one of the two control circuit input terminals and one of the two multiplexer input terminals; the d-type flip-flop is coupled to the two multiplexer selection terminals; the exclusive-NOR gate is connected in circuit between the two control circuit input terminals and two of three input terminals of the d-type flip-flop; and the second inverter is connected in circuit between the exclusive-NOR gate and one of the three input terminals of the d-type flip-flop.

Abstract: An electric multiple-valued register for electrically maintaining a multiple-valued digital signal of a ternary value of (0, 1/2, 1), quaternary value of (0, 1/3, 2/3, 1) or quinternary value of (0, 1/4, 2/4, 3/4, 1) instead of a binary digital signal such that 1 digit is of 0 or 1 is realized by inserting an element having a stair shaped voltage-current characteristic into a coupling circuit of a conventional flip-flop circuit. It may be used for a quantization circuit with the aid of a step characteristic, a multivalued memory, a multivalued register, a multivalued loop memory, a multivalued pattern matching circuit, a voice recognition divide, pattern recognition device, or a associative memory device.

Abstract: A storage element is provided in a circuit arrangement for latching one bit. A first MOS transistor (T1) is provided which, when a first control signal (S1) is present, switches an input signal corresponding to the bit to the input of the storage element. The storage element is provided with circuit elements by which an output signal at the output of the storage element is brought to a predetermined potential in dependence on the level of the input signal. The circuit arrangement is particularly suitable for constructing an address latch for DRAMs, particularly of the 16-M generation.

Abstract: An apparatus for a transparent master/slave flip-flop logic circuit including a single line connected to the transparency input of the logic macro so that when the line is active input data will pass through the flip-flop, unless the scan signal is also active, in which case the flip-flop will return to a clocked (latching) status.