Abstract: A method for minimizing instantaneous currents ina signal bus is disclosed. The method involves providing a programmable delay element in each of the signal buffers driving the signal on the bus. The programmable delay element in each signal buffer is selectable enabled to include a predetermined time delay. The method involves programming the delay elements in a selected group of the signal buffers t includde the predetermined time delay, so that the selected group of signal buffers each generate an output signal switching after the predetermined delay relative to the switching of output signals generated by other signal buffers.

Abstract: A delay generation circuit comprising (i) a circuit configured to generate a reference clock signal having a period, (ii) a divide circuit and (iii) an output circuit. The divide circuit may be configured to generate a first divided clock signal and a second divided clock signal in response to said reference clock signal. The output circuit may be configured to generate (i) a first output clock signal and (ii) a second output clock signal in response to (i) the first and second divided clock signals and (ii) the reference clock signal. The second output clock signal may have a delay with respect to the first output clock signal. The delay may be (i) a multiple of or (ii) a fraction of the period of the reference clock signal.

Abstract: A method and apparatus is disclosed for generating, based upon user input, clock signals which are delayed by sub-delays which are of a size that is smaller than the smallest achievable delay of a conventional delay element. A user can selectively add one or more sub-delays by providing control inputs which define the desired number of sub-delays to be added.

Abstract: A method and structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.

Abstract: A delay locked loop has a voltage-controlled delay section and a mis-lock detecting circuit. The voltage-controlled delay sections comprises a plurality of controlled delay circuits, including a specific one. In the mis-lock detecting circuit, there are generated pulse signals, each having a pulse width equivalent to the delay time between the delayed signals output from the adjacent two of the controlled delay circuits preceding the specific controlled delayed circuit. Another pulse signal is generated, which has a pulse width equivalent to the delay time between the delayed signals output from adjacent two of the specific controlled delay circuit and the other controlled delay circuits following the specific one. These pulse signals are added, generating a pulse signal. The number of pulses this pulse signal has per a unit time is compared with the number of pulses a reference signal has per the unit time, thereby detecting whether the delay locked loop is normally locked or not.

Abstract: The present invention provides a time delay system that generates a selectable asynchronous time delayed signal from an incoming signal using a pulse having a minimum pulse width and stop-startable oscillator. The time delay system of the present invention produces a minimum data dependency error which is independent of the repetition rate of the incoming signal, the substrate settling time, and the length of the time delay of the delayed signal.

Abstract: A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. In the lattice-like delay circuit, input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of a plurality of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.

Abstract: Rapid set-up is achieved in a programmable delay element having identical pairs of positionally corresponding delay stages in parallel arrays. The pairs of delay elements include identical arrangements of circuit elements and are replicable in a step-and-repeat fashion to simplify delay element manufacture for any arbitrary maximum delay time to be provided. Delay stages of the delay element are comprised of multiplexers. Outputs of respective delay stages are simultaneously stored as a signal transition is propagated through the delay stages in a first order to program the delay element. Thereafter, signals are propagated through selected delay stages in a second order controlled by the simultaneously stored outputs of respective delay stages during the propagation of the signal transition.

Abstract: A oscillation circuit has a delay loop with a clock delay circuit for generating a delayed clock signal. The clock delay circuit has a selector and has multiple delay elements with delay times differing from each other. The clock delay circuit may produce a time lag which is less than the delay time of any single delay element, the time lag being based on the difference between the time delays of different delay elements. A phase comparator compares the phase of a signal associated the delay loop to that of a reference clock signal, generating a phase difference clock signal. A delay setting circuit can cause the selector to change the selection of one delayed clock signal according to the phase difference signal from the phase comparator in such a manner as to reduce the phase difference.

Abstract: A voltage controlled oscillator includes plural cascade-connected unit circuits supplied with selection signals corresponding to an oscillation frequency. Each unit circuit includes a voltage controlled delay circuit, selection circuit and adder circuit. The selection circuit has a first input terminal supplied with an output signal of the voltage controlled delay circuit and a second input terminal supplied with the selection signal. The adder circuit has a first input terminal supplied with an output signal of the selection circuit, a second input terminal supplied with a feedback signal from a next-stage one of the unit circuits and a third input terminal supplied with the selection signal. The adder circuit adds signals supplied to its first and second input terminals to form a feedback signal. The output signal of the voltage controlled delay circuit in each unit circuit is supplied to the voltage controlled delay circuit in the next-stage one of the unit circuits.

Abstract: A delay circuit includes a primary circuit receiving an input signal and outputting two intermediate signals having a delay therebetween. A combination circuit with two modules that output a combination signal on the basis of the addition with weighting and effect of integration of the intermediate signals and of their conjugate. Each module includes a discharging circuit and a charging circuit, which each have switching elements controlling the connection between a common line and first and second supply potentials. These connections use a variable resistor and a non-variable resistor so as to ensure the permanent participation of the two modules in the charging or discharging of a capacitor. This delay circuit is particularly useful in CMOS circuits.

Abstract: A high resolution delay line includes a coarse delay having a minimum period of delay and a fine delay having a total delay, wherein the total delay is equal to or greater than half the minimum period. Each delay can be implemented in analog or digital form and the delay line can be implemented with one portion in analog form and the remainder in digital form. The digital delay can provide a delay upward of 1,500 milliseconds. The fine delay provides a resolution of ten microseconds or less. An unknown delay is measured by coupling a signal into two channels, wherein the first channel includes the unknown delay and the second channel includes the coarse delay and the fine delay. The output signals from the channels are correlated while adjusting the coarse delay for maximum correlation and then adjusting the fine delay for maximum correlation.

Abstract: A structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.

Abstract: Multiple controllable delays reduce EMI radiated during the transmission of multiple synchronized signals. Each controllable delay introduces a controlled delay into a corresponding signal being transmitted. The controlled delay is such that the combined strength of the multiple signals at peak frequencies is substantially reduced. This results in reduced EMI radiation at those peak frequencies.

Abstract: Arbiter circuits placed between two signal path segments on a semiconductor chip to measure the difference in propagation delay between those paths at their beginning and end. Each arbiter circuit has two inputs, and outputs signals indicating which of its inputs is the first to receive a leading edge of an input transition. External circuitry monitors the arbiter outputs, and accordingly controls the application of the input transitions. By varying the delay of the input signal paths, the relative propagation delay can be determined.

Abstract: A controlled delay circuit having a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: A delay signal generating apparatus incorporated in an integral circuit, includes a plurality of serially-connected delay elements for delaying an input signal successively and for outputting plural delay signals, a heat generating circuit for heating the plurality of delay elements, and a heat controller for controlling a heat amount generated by the heat generating circuit so as to change the delay time of each of the plural delay signals.

Abstract: A delay cell for use in binary delay line which includes a delay circuit having N outputs where N.gtoreq.2, each delay circuit coupled to an input through N-1 serially connected unit cells. For each output there are P unit cells having a unit delay of t.sub.P0 and N-1-P unit cells having a unit delay of t.sub.p1. The N outputs are ordered such that each output other than the first is delayed with respect to an immediately preceding output by t.sub.p1 -t.sub.p0, and P goes in succession from N-1 to 0 in unit steps. Each value of P corresponds to only one of the N outputs.

Abstract: A delay circuit is to produce a delay timing which is larger than one cycle time of a reference clock while the resolution of which is smaller than the one cycle time of the reference clock.

Abstract: An external clock signal CK is input to a buffer, which generates an internal clock signal CLK having a skew of D1 with respect to the external clock signal CK. The internal clock signal is input first to a delay circuit which has a delay time A, then to a delay array which provides a delay time D2, and finally to a delay circuit which has a delay time of D2. The delay circuit generates a corrected internal clock signal CK' which is synchronous with the external clock signal CK. The delay array is composed of delay units, each having a state-holding section. The state-holding section of any delay unit that has passed a forward pulse is set in a predetermined state. Once its state-holding section is set in the predetermined state, the delay unit provides a correct delay time of 2.times..DELTA..

Abstract: A scale of circuit is reduced when a plurality of variable delay circuits are provided with respect to the same signal. A variable delay circuit is constructed such that variable delay circuit elements each comprising a delay circuit element composed of buffer gates each having an identical amount of delay connected in series and a selector e for selecting the input and output of the delay circuit element are connected in series in n-1 stages, wherein the number of the delay elements of the delay circuit element in each variable delay circuit element is 2.sup.i-1 (i: number of stages) in the order from the final stage.

Abstract: A pulse generator comprising a delay circuit uses a series of "n" delay stages to generate pulses that do not have distorted duty cycles. The output of the delay stage "n" feeds back to reset the delay stage "n-2". The output of each of the delay stages initially changes from a first logic state to a second logic stage at the leading edge of a pulse. The output of each delay stage switches back to the first logic state, or the trailing edge of the pulse, upon receipt of the feedback signal from a subsequent delay stage. The wave characteristics depend only on the rising edge of the pulse because the rising edge of the pulse of a future stage generates the falling edge of the current stage.

Abstract: A fully digital clock multiplier capable of generating any N/M multiple of an input clock frequency with a precise duty cycle is provided. The input clock signal is divided by M to create a divided clock signal. The propagation of the input clock signal along a delay cell string during a half cycle of the divided clock signal is then measured. The measured propagation is then scaled by a factor N to select an appropriate delay cell string length within a ring oscillator for generating an output signal.

Abstract: An improved clock signal modeling circuit capable of more quickly generating an internal clock signal in an external clock signal without using a phase locked loop and a delay locked loop, which includes a delay unit for receiving an external clock signal and for outputting a delay clock sinal; a sampling unit for receiving the delay clock signal and for sampling in accordance with an external clock signal; a comparing unit for receiving the output of the sampling unit and for sequentially comparing the output; and an output unit for receiving the delay clock signal outputted from the delay unit and for outputting an internal clock signal in accordance with an output signal of the comparing unit and an externally applied switching signal.

Abstract: A self-setup non-overlap clock generator is disclosed. This clock generator includes a primary clock signal input terminal for providing a primary clock signal, and a selection signal input terminal for providing at least one selection signal. The present invention also includes a first logic gate having a first input terminal coupled to receive an inverted signal of the primary clock signal. Further, a second logic gate is provided, having a first input terminal coupled to receive the primary clock signal. A first programmable delay portion is used to delay an output signal from the first logic gate an amount of time according to the selection signal, and a second programmable delay portion is used to delay an output signal from the second logic gate a predetermined amount of time according to the selection signal. Therefore, a first clock signal is generated from the output of the first logic gate, and a second clock signal is generated from the output of the second logic gate.

Abstract: A delay line having variable delay comprising apparatus for receiving an input clock signal and for providing an inverted and non-inverted version thereof, a plurality of serially connected inverter stages each for receiving and translating the inverted and non-inverted versions of the input clock signal, inverted and non-inverted outputs of each of the inverter stages except a last inverter stage in series being cross-connected to inputs of an immediately following inverter stage, and apparatus for shunting outputs of one of the inverter stages to a pair of output nodes.

Abstract: Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying application of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage.

Abstract: An apparatus for use in the simultaneous deactivation of a set of series-connected switching devices includes gate command control logic to generate a gate command signal for application to a selected switching device of the set of series-connected switching devices. A command compensation circuit processes the gate command signal. The command compensation circuit includes a time differential measurement module that forms a time differential signal indicative of the time from the previous turn-off of the selected switching device and the previous turn-off of the last switching device in the set of series-connected switching devices. A time difference processing module of the command compensation circuit process the time differential signal and creates a delay signal. A delay module of the command compensation circuit delays the gate command signal in response to the delay signal. Each switching device of the set of series-connected switching devices includes a command compensation circuit.

Abstract: An improved clock signal modeling circuit capable of more quickly generating an internal clock signal in an external clock signal without using a phase locked loop and a delay locked loop, which includes a delay unit for receiving an external clock signal and for outputting a delay clock signal; a sampling unit for receiving the delay clock signal and for sampling in accordance with an external clock signal; a comparing unit for receiving the output of the sampling unit and for sequentially comparing the output; and an output unit for receiving the delay clock signal outputted from the delay unit and for outputting an internal clock signal in accordance with an output signal of the comparing unit and an externally applied switching signal.

Abstract: A ring oscillator shortens the delay time between consecutive delayed clock signals, and increases of the number of delayed clock signals, without changing the oscillation frequency f of the ring oscillator and the number of stages n of inverter in one loop, and holding the same control current/osclllation frequency. The ring oscillator has odd numbers of unit inverters, wherein the unit inverter comprises two serial circuits connected in parallel each comprising of P channel transistor and N channel transistor, constant current sources connected to P channel and N channel sides in these parallel circuits, respectively, which are controlled by a current control circuit.

Abstract: In a circuit provided in a single integrated circuit unit for use in a signal delay device, there is provided with a device in which an input signal is delayed and a plurality of delay signals, each having a different delay period from the input signal, are outputted, and a detector in which a delay signal having a specific relation with the input signal among the plurality of delay signals is detected.

Abstract: A video clock input signal is applied to a delay line comprising a cascade connection of a plurality of delay elements formed in an integrated circuit for providing a plurality of delayed clock signals at respective taps of the delay line. A selection circuit, responsive to a horizontal synchronizing signal supplied thereto, couples a selected one of the taps to an output for providing a delayed output clock signal that is edge-aligned with the synchronizing signal. For reducing the number of taps required to provide a given minimum delay step resolution and a given minimum total delay for delay elements which may vary in delay, from one integrated circuit to another, the taps are spaced one element apart for a first group of the delay elements and are spaced more than one element apart for at least one second group of the elements.

Abstract: A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference input clock signal or which produces a selected phase relationship to the reference clock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference input clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference input clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference input clock/output clock relationship.

Abstract: Systems and methods for accurately skewing periodic signals using a matching pair of voltage controlled delay lines, a frequency comparator, and a common control signal to the delay lines as generated by the frequency comparator. A feedback oscillation is established in a loop including one of the voltage controlled delay lines. The frequency comparator controls the frequency of the loop oscillation in direct proportion to a comparison between the oscillation frequency and a subharmonic of a base clock signal. The base clock signal is sent through the second voltage controlled delay line, which by matching of delay line characteristics and a common control signal introduces a clock period of skew or delay over the length of the second voltage controlled delay line. Taps to nodes in the succession of device stages making up the second voltage controlled delay line provides the clock signals with directly proportioned skews, the skews being defined by precise physical divisions of the delay line.

Abstract: An improved high precision synchronous delay line featuring propagation control circuitry in the voltage controlled delay line removing skew between a pair of propagated waveforms. A pair of waveforms are received by the voltage controlled delay line of the synchronous delay line. The voltage controlled delay line features propagation control circuitry which couples together the propagation of the pair of waveforms through the present invention. If a transition from one level to another level occurs on any one of the received pair of waveforms, the propagation control circuitry prevents the transition from propagating until a corresponding transition occurs on the other one of the pair of waveforms. As a result, any skew that is created between the pair of waveforms, for any reason, is removed by the propagation control circuitry. With the skew removed, the presently improved synchronous delay line features increased precision and provides for greater resolution.

Abstract: A programmable, timing signal generator propagates a digital wave along a delay chain comprised of series connected inverters that has sufficient stages that the edge of the wave will not propagate to the end during one system clock cycle time. The delay chain is sampled once each clock cycle, and the point to which the wave has progressed is encoded. Programmable, fine leading and fine trailing edge registers store, as a fraction of the clock cycle time, the desired locations of the timing signal leading and trailing edge relative to the clock edges.

Abstract: A programmable, timing signal generator propagates a digital wave along a delay chain comprised of series connected inverters that has sufficient stages that the edge of the wave will not propagate to the end during one system clock cycle time. The delay chain is sampled once each clock cycle, and the point to which the wave has progressed is encoded. Programmable, fine leading and fine trailing edge registers store, as a fraction of the clock cycle time, the desired locations of the timing signal leading and trailing edge relative to the clock edges.

Abstract: A timing signal generator produces a timing signal having one or more pulses of adjustable phase relative to pulses of a stable reference clock. The timing signal generator employs a low jitter retriggerable oscillator to produce a set of tap signals. The tap signals are frequency locked to the reference clock signal but are evenly distributed in phase. The timing signal generator times the pulses of its output timing signal using pulses of the various tap signals as timing references. Each cycle of the oscillator is triggered by a pulse of the reference clock signal to minimize timing signal jitter. Phase lock loops frequency lock the tap signals to the reference clock and ensure predictability of the timing signal pulse timing relative to the reference clock signal.

Abstract: A pulse phase difference encoding circuit includes a ring delay pulse generating circuit which is formed by a NAND circuit and inverters. Signal lines connecting the NAND circuit and the inverters have uniform load capacity to obtain even time resolutions. The NAND circuit is formed by component transistors one of which is larger in size to have the same delay time as the other inverters. A dedicated latch buffer for applying steeply changing drive pulse to a pulse selector is provided to prevent difference in the measurements. A specific value is outputted in the event of the overflow or underflow of the measurement time to obtain a constant digital output.

Abstract: In a circuit provided in a single integrated circuit unit for use in a signal delay device, there is provided with a device in which an input signal is delayed and a plurality of delay signals, each having a different delay period from the input signal, are outputted, and a detector in which a delay signal having a specific relation with the input signal among the plurality of delay signals is detected.

Abstract: A multiple-phase clock signal generator includes a phase-locked loop (PLL) for generating an oscillating signal having a predetermined frequency, a counter driven by the oscillating signal and having a plurality of outputs, and a plurality of combinational logic gates each having a plurality of inputs and an output. Selected ones of the inputs of each combinational logic gate are coupled to selected outputs of the counter to produce, at the output of each combinational logic gate, a clock signal having a particular phase. Different combinations of the outputs of the counter can be used to generate different phases.

Abstract: In a display data driving IC for driving a matrix display unit, switching current in a plurality of channel driving buffer circuits is suppressed, and when a multi-tone display unit is driven, the tone display quality is improved.

Abstract: The invention relates to an integrated circuit, having an output stage with at least two respective output transistors, respective main current channels of which are connected in parallel between a first supply terminal and the output. A control circuit ensures that, in response to a variation in an input signal on the input, the charging of respective control electrodes of the at least two respective output transistors commences with a delay relative to one another. The peak value of the time derivative of a current output together by the at least two output transistors is thus limited. After the start of charging, a speed of charging of the control electrode of at least one of the two respective output transistors is reduced. The peak value of the time derivative of the current applied to the output by the at least one of the at least two output transistors is thus reduced.

Abstract: A programmable multiphase clock divider for selectively frequency dividing a multiphase input clock to provide a lower-frequency, self-aligned, multiphase output clock includes a counter, combinational logic circuitry, a multiphase signal generator and a multiplexor. With the counter serving as the sole frequency divider element, multiple phase-aligned clock phases are generated which are then programmably multiplexed to provide the desired frequency-divided, self-aligned clock phases. The counter, in response to a preset signal and an input clock phase, generates a multibit count signal, one bit of which forms the first output clock phase. The combinational logic circuitry receives a programming signal for decoding the multibit count signal to generate the counter preset signal and an output control signal.

Abstract: A delay circuit includes a first and a second switching transistor, each of which has a control electrode and a first and a second main electrode, a first and a second input of the delay circuit being coupled to the control electrode of the first switching transistor and the second switching transistor, respectively. A first and a second output of the delay circuit are coupled to the second electrode of the first and the second switching transistors, respectively. The first electrodes of the first and the second switching transistors are coupled to one another and, via a current source, to a first power supply terminal. The outputs are coupled to a second power supply terminal via respective load circuits. Respective clamp circuits are coupled to the outputs in order to limit maximum attainable differences between a voltage on the second power supply terminal on the one side and a voltage on the respective outputs on the other side.

Abstract: An apparatus and method for enhancing the signal-to-noise ratio of an input signal which divides the input signal into a plurality of divided signals of equal power, introduces a delay into a corresponding one of the plurality of divided signals, mixes together pairs of the plurality of delayed divided signals, and sums the mixed signals. The apparatus and method of the present invention may be employed in a signal detector to improve the sensitivity of the signal detector.

Abstract: A delay-locked-loop based clock synthesizer for generating, from a reference signal, a clock signal having a frequency different from a frequency of the reference signal includes a delay-locked-loop circuit having a plurality of controllable delay elements serially connected to one another. Each of the delay elements delays the reference signal by an adjustable quantum of time such that the delay elements generate a plurality of delayed signals. A first multiplexer routes one of the delayed signals to a phase detector, which generates a control signal indicative of a difference between a phase of the routed delayed signal and a phase of the reference signal. A feedback loop transfers the control signal from the phase detector to the delay elements, wherein each of the delay elements adjusts, in accordance with the control signal, the quantum of time by which they each delay the reference signal, such that the phase of the reference signal is synchronized with the phase of the routed delayed signal.

Abstract: Controlled delay digital clock signal generator, characterised in that it comprises means (I5, I6, I7, I8, I9, I10, IT7, IT8, IT9, IT10, C4) to generate from a clock signal (CK) and its complementary signal (CKB) a ramp signal comprising at least two segments of positive slope and at least two segments of negative slope, means (I1, I2, IT1, IT2, IT3, C2, CET1T2, AMPLI, I3, I4, IT4, IT5, IT6, C3, CET3T4, AMPL2) for separate control of the slopes of the said segments, means with trigger circuits (AMPLO) for converting the ramp signal (RAMP) into a square signal (CKQ) means (NO0, A0, A1, NO1) for achieving the logic combinations of the delayed square clock signal (CKQ) resulting from the conversion with the clock signal (CK) and the clock complementary clock signal (CKB) of the said clock signal to obtain as many delayed digital clock signals as the ramp signal has segments of different slopes.

Abstract: Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying applications of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage.