Abstract: One embodiment of the present invention provides a system that biases a floating node within an integrated circuit. During operation, the system first identifies the floating node within the integrated circuit to be biased. The system then determines a desired bias voltage. Next, the system couples a low-power bias source to the floating node to supply the desired bias voltage, wherein the floating node is biased without stopping data transmission through the floating node during biasing.

Abstract: A delay setting data generator generates delay setting data based on rate data. A variable delay circuit delays the test pattern data by a delay time determined by the delay setting data with reference to a predefined unit amount of delay. First rate data designates the period of the test pattern data with a precision determined by the unit amount of delay. Second rate data designates the period of the test pattern data with a precision higher than that determined by the unit amount of delay. The delay setting data generator outputs a first value and a second value in a time division manner at a ratio determined by the second rate data, the first and second values being determined by the first rate data.

Abstract: A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output.

Abstract: Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation.

Abstract: In one embodiment, a method of performing an A/D conversion includes comparing a reference signal to a ramp signal, comparing an input signal to the ramp signal and causing a signal to propagate through a delay line when the ramp signal crosses a first of the reference signal or the input signal. The state of the delay line is stored when the ramp signal crosses a second of the reference signal or the input signal after the ramp signal crosses the first of the reference signal or the input signal.

Abstract: A delay circuit that includes a logic gate through which an input signal passes, a capacitor configured to be charged and discharged at an output terminal of the logic gate and delaying the input signal, and a mirroring unit configured to constantly maintain current output by the logic gate by mirroring current output by a constant current source.

Abstract: There is provided a digitally controlled oscillator, which is capable of widening its operation range with maintaining its resolution and the maximum frequency at which it operates. The digitally controlled oscillator includes a phase compensation block, a coarse block, and a fine block. The phase compensation block 510 generating a PLL signal PLLCLK and a first clock signal CLK1 which has the same phase and frequency as the PLL signal, in response to a phase control signal DISABLE and a fourth clock signal CLK4. The coarse block 520 generating a second clock signal CLK2 and a third clock signal CLK3 which results from delaying the PLL signal PLLCLK and the first clock signal CLK1 for a given time, in response to a m(integer)-bit coarse A control signal COAR_A and an (m?1)-bit coarse B control signal COAR_B.

Abstract: A leakage efficient anti-glitch filter. In accordance with a first embodiment of the present invention, a leakage efficient anti-glitch filter with variable delay stages comprises a plurality of variable delay stages and a coincidence detector element for detecting coincidence of an input signal to the delay element and an output of the delay element. The plurality of variable delay stages may comprise stacked inverter circuits or stacked NAND circuits.

Abstract: A variable delay circuit includes: a first delay section that changes a first drive capability or a first capacity load, receives the reference signals, and generates a first delayed signal by giving a first delay to the reference signal; a second delay section that changes a second drive capability or a second capacity load of the second delay section, receives the reference signal, and generates a second delayed signal by giving a second delay to the reference signal; a first capacity load setting section that sets at least one of the first capacity load and the second capacity load; a first phase comparing section that compares a first phase of the first delayed signal with a second phase of the second delayed signal; and a drive capability setting section that controls the first drive capability and the second drive capability.

Abstract: Delay lock loop circuits are described, which may include two or more delay stages that each includes a plurality of selectable delay elements. A reference signal drives an input of the first delay stage, which provides a first output. The first output drives an input of the second delay stage, which provides a second output. The circuits further include a first selector register that is associated with the first delay stage. A value maintained in the first selector register determines a number of the selectable delay elements utilized in the first delay stage. The circuits further include a second selector register associated with the second delay stage. A value maintained in the second selector register determines a number of the selectable delay elements utilized in the second delay stage. Modification of the values maintained in the first and second selector registers are synchronized to the first and second outputs, respectively.

Abstract: A plurality of delay paths are connected in parallel between two synchronous operation circuits operating in synchronism with a clock signal CLK, and enable transmission of a signal. A delay detection unit detects the respective delay times of the plurality of delay paths, and a control unit selects one delay path from among the plurality of delay paths based on the detection results from the delay detection unit, and controls the blocking of signal transmission in the delay paths other than the selected one delay path.

Abstract: A delay circuit includes an interface for giving a command of setting a delay time and a delay device that can be set to any desired delay time, and the delay time of the delay device is set according to a command from the interface.

Abstract: A circuit synchronizes parallel data of different timing for transfer. The synchronous data transfer circuit includes a plurality of first flip-flop circuits in which the parallel data are set by a data strobe signal, a plurality of delay circuits, and a plurality of second flip-flop circuits. By configuring the second flip-flop circuits to share generation of a delay amount, the second flip-flop circuits are utilized for data synchronization by the synchronous data transfer circuit. Thus, it becomes possible to configure the delay circuits with a remarkably reduced amount of delay elements.

Abstract: A delay circuit of a semiconductor memory apparatus can include a clock period sensing unit for generating a sensing signal in response to a clock frequency, and a selective delay unit for delaying an input signal for a delay time and then output the input signal as an output signal, wherein the delay time can be one selected from a plurality of delay times according to the sensing signal. The delay time can be selectively determined according to a clock frequency used in a semiconductor memory apparatus.

Abstract: A signal generating circuit includes an input stage delay circuit which can switch a state of outputting a reference clock and a state of outputting a signal delaying the reference clock by a first time which is shorter than one cycle of the reference clock, a control section including a gate circuit holding the output of the input stage delay circuit for a second time which is shorter than one cycle of the reference clock from a point at which the output of the input stage delay circuit is changed to output a signal corresponding to the output of the gate circuit, and an output stage delay circuit outputting a signal delaying the output signal of the control section by the second time, in which the input stage delay circuit switches an output state in response to change of the output signal of the control section.

Abstract: A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay of a predetermined period should be required when the semiconductor chip is designed. The data delay circuit includes a clock oscillation unit that can reflect changes in a delay period of a delay cell and automatically adjust the delay period of the delay cell. Since the data delay circuit includes a monitoring circuit and a plurality of delay paths, the data delay circuit can provide a delay path having a desired delay value. Therefore, even when the operating environment of a semiconductor device changes, the data delay circuit can control the delay period of a data signal.

Abstract: The invention relates to multi-phase clock system for receiving a plurality of clock signals (CLKo-n) comprising actual time events (aTE) defining different clock phases, the clock signals all having a same clock frequency but different clock phases, the system further arranged for receiving a reference clock signal (REFCLK) for providing reference time events (rTE) for the plurality of clock signals (CLKo-n), the reference clock signal (REFCLK) having a reference frequency different from the clock frequency, the reference frequency being selected such that each one of the subsequent reference time events (rTE) coincides with a desired time event (dTE) for a single one of the plurality of clock signals (CLKo-n).

Abstract: A delay circuit has a fixed delay path at a lower voltage level, a level converter, and an adjustable delay path at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to the circuit output. In an application for a local clock buffer of a static, random-access memory (SRAM), the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. These voltages may vary in response to dynamic voltage scaling, requiring re-calibration of the adjustable delay path. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns the correct output, or by using a replica SRAM path to simulate variations in delay with changes in voltage supply.

Abstract: A delay adjustor for adjusting the delay time of a signal, the adjustor comprising: a first capacitance unit and a variable capacitance unit serially coupled to the first capacitor wherein the capacitance of the variable capacitance unit is adjusted according to a first control signal and the variable capacitance unit comprises a plurality of second capacitors and at least a first switch coupled to the at least one capacitor of the second capacitors.

Abstract: A method for operating a data storage medium when changing from an operating mode to a directly subsequent power-saving quiescent mode, where the operating mode effects a transmission delay for the last item of information which is to be transmitted, so that immediately after the last item of information which is to be transmitted has been transmitted the quiescent mode is activated and the maximum permissible power consumption is observed.

Abstract: The frequency of an oscillating signal generated by a ring oscillator is used to determine the select-to-output delay of standard cell multiplexers. The ring oscillator has no active logic elements other than an odd or even number of standard cell multiplexers. The signal path of the oscillating signal passes through the select input leads of the multiplexers of the ring oscillator. The ring oscillator can be used to characterize how signal propagation delay varies depending on the voltage supplied to the multiplexers. The lowest supply voltage at which a signal can continue to travel through the most critical circuit path of a test circuit can be modeled. In addition, the ring oscillator can be built into operational circuits to monitor timing and signal propagation delay in real time. Real time monitoring of delay enhances the benefits of adaptive voltage scaling, which is used in signal processing circuits in cell phones.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A delay circuit includes: a current control circuit which has n (n is 1 or larger natural number) control pins and a first output line, and is capable of controlling current outputted from the first output line in response to n control signals inputted to the corresponding n control pins; a current mirror circuit connected with the first output line to produce current mirror current from the current and output the current mirror current from a second output line; a first active element having a gate pin and an input pin, the gate pin is connected with the second output line, and the input pin is connected with the first voltage line; a second active element having a gate pin and an input pin, the gate pin is connected with the first output line, and the input pin is connected with the second voltage line; and an inverter circuit having third and fourth active elements connected in series between an output pin of the first active element and an output pin of the second active element.

Abstract: A configurable delay chain with switching control. The configurable delay chain includes a plurality of delay elements. A switch circuit is included and is coupled to the delay elements and configured to select at least one of the plurality of delay elements to create a delay signal path. The delay signal path has an amount of delay in accordance with a number of delay elements comprising the delay signal path. An input is coupled to a first delay element of the delay signal path to receive an input signal and an output is coupled to the switch circuit and is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path. A plurality of turnoff devices are coupled to inputs of the delay elements and coupled to the switch circuit, wherein the switch circuit activates at least one turnoff device of at least one unused delay element that is not on the delay signal path.

Abstract: A device having power management capabilities and a method for power management, the method includes: providing a clock signal and a supply voltage to at least one component of a device; detecting a timing error; delaying by a fraction of a clock cycle and in response to the detected timing error, a clock signal provided to at least one of the components; and determining a clock signal frequency and a level of the supply voltage in response to at least one detected timing error.

Abstract: A digital delay line includes a plurality of hysteresis-based delay cells electrically connected in series. These hystersis delay units in the hysteresis-based delay cells may be similar or different. All of the hysteresis delay units respectively have an inverter mode and a hesteresis mode. The delay and resolution of the hysteresis delay unit may be derived from the time difference in the inverter mode and hysteresis mode. Such a digital delay line applied to a digital phase locked loop may reduce consumption of area and power.

Abstract: A variable delay apparatus comprises a calibrating unit receiving a signal from a variable delay unit and from a plurality of fixed delay sources, the calibrating unit comparing the signal from the variable delay unit with a plurality of signals from the fixed delay sources to control operation of the variable delay unit over a delay range independently of environmentally-induced drift.

Abstract: A delay circuit comprising a delay measurement unit, a delay mapping unit and a map delay module. The delay measurement unit generates a mapping table according to a reference signal and a reference clock signal. The delay mapping unit generates a mapped delay selection signal according to an input selection signal and at least a mapping value from the mapping table. The map delay module delays an input data signal to generate an output data signal according to the mapped delay selection signal.

Abstract: It is an object of the invention to provide a variable delay apparatus in which, even immediately after the delay amount of the variable delay apparatus is changed, a signal of a timing that is different from a set delay amount is not output. The variable delay apparatus of the invention includes: a variable delay block 108 having N (N is a natural number) delay elements 101a to 101n, and N selectors 102a to 102n; a variable delay block 109 having N delay elements 103a to 103n, and N selectors 104a to 104n; and a selector 107. After selection signals 105a to 105n and 106a to 106n are changed, and after an output timing of a delay amount set by the variable delay blocks 108, 109 is attained, the signal to be output is switched by the selector 107, thereby avoiding a situation where, immediately after the delay amount is changed, a signal of a timing that is different from the set delay amount is output as an output signal.

Abstract: A tapered chain of delay elements. The chain of delay elements includes a plurality of delay elements comprising a plurality of smaller sized stacked inverter delay elements each configured to implement a first delay, and a plurality of larger sized stacked inverter delay elements each configured to implement a second delay larger than the first delay. A switch circuit is coupled to the plurality of delay elements and is configured to select at least one of the plurality of delay elements to create a delay signal path having an amount of delay in accordance with a number of delay elements comprising the delay signal path. An input is coupled to a first delay element of the delay signal path to receive an input signal. An output is coupled to the switch circuit, wherein the output is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.

Abstract: According to an embodiment of the present invention, an insulating communication circuit includes a first insulating circuit 62#11 having first and second circuits, a second insulating circuit 62#12 having third and fourth circuits, and a communication interface that is connected to a first ground and transmits a signal to the first circuit based on a communication signal and a clock signal from an external control device.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: Circuits, methods, and apparatus for delaying signals in a power and area efficient manner are provided. A gating element within a stage of a programmable delay element suppresses an operation of other stages of the delay element. A programmable delay has components with differing delays that may be combined to give flexibility in choices for delay increments while minimizing the area of the delay element. A delay element is shared between different signal paths, for example, to reduce the number of delay elements or to allow utilizing unused delay elements of other signal paths.

Abstract: A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.

Abstract: A delay line architecture is presented. In one embodiment, the delay line is used to introduce delay compensation into a circuit design at the top level of the circuit design.

Abstract: A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer.

Abstract: A delay circuit is described having a variable capacitor and a triggering circuit. The variable capacitor and the triggering circuit may both comprise transistors. With both the variable capacitor and the triggering circuit dependent on the threshold voltage, the delay circuit may be less sensitive to process variations. The delay circuit may also include a capacitor, a first triggering circuit, a second triggering circuit, and a pull down circuit. The capacitor may discharge at a first rate, triggering the first triggering circuit which, in turn, activates the pull down circuit to pull down the capacitor at a second rate that is faster than the first rate. The second triggering circuit is triggered as the capacitor is pulled down, thereby reducing the effect of input signal noise on the output of the delay circuit. The discharging of the capacitor may be adjusted by a control input thereby making the delay of the delay circuit programmable.

Abstract: A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control signals and (B) generating the plurality of first control signals in response to the output signal and a plurality of second control signals. The output signal may include a delayed version of the input signal. An amount of delay between the input signal and the output signal may be determined based upon the plurality of first control signals.

Abstract: A delay circuit that includes a logic gate through which an input signal passes, a capacitor configured to be charged and discharged at an output terminal of the logic gate and delaying the input signal, and a mirroring unit configured to constantly maintain current output by the logic gate by mirroring current output by a constant current source.

Abstract: The present invention provides a way of hysteretic switching for efficiently reducing the heavy switching between two adjacent coarse intervals. The present invention disposes a number of fine intervals to cover a range which is larger than the length of one coarse interval. Each coarse interval comprises some extra fine intervals which are exceeded the boundary of the coarse intervals in one side. The heavy switching will be postponed until the extra fine intervals are used up. In the meantime, the fine calibration unit records the number of extra fine interval which be used. An extra-boundary value will be recorded in the fine calibration unit for determining an initial fine interval in another coarse interval if the heavy switching occurs. It should be noted that the extra-boundary value could be a positive or minus value corresponding to which a forward coarse interval or a backward coarse interval the reference signal drifts into.

Abstract: A clock signal generator for generating clock signals to an integrated circuit. The clock signal generator comprises a delay-locked loop adapted to generate a plurality of mutually delayed clock phases based on a reference clock signal. The delay-locked loop is further adapted to select one of the plurality of clock phases as an output signal of the delay-locked loop in response to a first control signal, wherein said output signal is a first clock signal. The clock signal generator further comprises an inverter arranged to generate an inverse of the output signal and a multiplexer unit arranged to, in response to a clock-invert signal, forward either the output signal or the inverse of the output signal as a second clock signal.

Abstract: A stacked inverter delay chain. The stacked inverter delay chain includes a plurality of stacked inverter delay elements. A switch circuit is included and is coupled to the stacked inverter delay elements and configured to select at least one of the plurality of stacked inverter delay elements to create a delay signal path. The delay signal path has an amount of delay in accordance with a number of stacked inverter delay elements comprising the delay signal path. An input is coupled to a first stacked inverter delay element of the delay signal path to receive an input signal and an output is coupled to the switch circuit and is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.

Abstract: A clock distribution circuit includes a monitoring circuit that delays a signal based on a clock signal from a clock tree by using multiple inverter circuits and predicts a timing violation on the basis of the amount of delay produced by the multiple inverter circuits. The clock distribution circuit further includes an OR circuit that controls, on the basis of the result of prediction by the monitoring circuit, a clock gating signal generated by a combinational circuit and a clock gating circuit that supplies a clock signal or stops supply of the clock signal depending on a signal output from the OR circuit.

Abstract: A conditioning buffer is provided for a clock interpolator that controls the duration of the clock edges to achieve high-linearity interpolation. The conditioning buffer includes a first buffer and a second buffer, with a fixed or variable strength, that receive their respective inputs from a set of mutually delayed clock signals, such as a set of N equidistant clock phases with mutual delay of 360/N degrees, to form a two-tap transversal filter that is insensitive to changes in Process, Temperature, and Voltage (PVT). Use of an equidistant set of clock phases makes the time constant of such transversal filter proportional to the clock period thus making it insensitive to changes in clock frequency as well. Such transversal filtering action operated in conjunction with natural bandwidth limitations of the buffers yields an efficient clock conditioning circuit that is highly insensitive to PVT and clock frequency variations.

Abstract: A master-slave device communication circuit includes a master device, a bus, and a slave device having a bus switch connected to the master device via the bus, and a status detecting circuit. The status detecting circuit includes a power input terminal and a detecting signal output terminal. A power terminal of the master device is connected to the power input terminal of the status detecting circuit. The detecting signal output terminal is connected to the bus switch and a trigger pin of the master device. When the master device supplies power to the slave device via the power terminal thereof, the detecting signal output terminal transmits a control signal to control the bus switch to turn on the bus and trigger the master device to communicate with the slave device after a delay time.

Abstract: An apparatus, includes a counter which counts a frequency of input of a first signal, a delay controller which generates a second signal by adding a delay to the first signal, the delay corresponding to the frequency, and a control circuit which halts the counter counting the frequency, when a phase difference between the first signal and the second signal is a predetermined value.

Abstract: A delaying stage selecting circuit for selecting a specific delaying stage from a plurality of delaying stages, where the delaying stages are for outputting delayed clock signals, includes: a first register for sampling the delayed clock signals according to a clock signal to generate sampled values; first memory units, wherein the first memory units are utilized to memorize the sampled values, and each of first memory unit outputs at least one of the sampled values according to a corresponding first selecting signal; a first selecting unit, for outputting the sampled values according to a second selecting signal; a determining module, for determining if the sampled values meet a specific relation, where if the determination result is positive then determining the particular delaying stage; and a counter for generating a counting value to control the delayed clock signal sampled by the first register.

Abstract: A circuit includes a first wiring to transmit a first signal, an alteration element to adjust a delay amount being added to the first wiring, and a shield element to shield the alteration element from a second wiring, the second wiring transmitting a second signal.

Abstract: A self correcting device includes a first flip-flop to receive data and coupled to a clock input; one or more delayed flip-flops used to detect delay variations; a multiplexer coupled to the output of the first flip-flop and the delayed flip-flops, a metastability detector and error check controller to control the multiplexer to select one flip-flop output; and an adaptive voltage swing link coupled to the multiplexer output to generate a voltage swing on the link based on a selected clock skew.

Abstract: A delay circuit, including: a plurality of first delay units coupled in series and each configured to generate a delay time that is approximately double a unit delay time; a second delay unit configured to generate the unit delay time and coupled to a last stage of the plurality of first delay units; and a selector configured to select either an output signal of the last stage of the plurality of first delay units or an output signal of the second delay unit, wherein an external input signal is input to the first delay unit and to each second delay unit, and the first delay unit and the second delay unit each include a switch circuit configured to output with a delay either an output signal of a previous stage delay unit or the external input signal.