With Plural Paths In Network Patents (Class 327/293)
  • Patent number: 7812659
    Abstract: A programmable logic device (“PLD”) or the like has a plurality of data transmitter channels. Certain circuitry is shared by the channels. The shared circuitry includes at least one phase-locked loop (“PLL”) circuit for producing a primary clock signal, and global frequency divider circuitry for producing at least one global secondary clock signal based on the primary signal. The primary and global secondary signal(s) are distributed to the channels. Each of the channels includes local frequency divider circuitry for producing at least one local secondary clock signal based on the primary signal. Each channel also includes selection circuitry for selecting either the global or local secondary signal(s) for use by clock utilization circuitry of the channel. The clock utilization circuitry may include serializer circuitry for converting data from parallel to serial form.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: October 12, 2010
    Assignee: Altera Corporation
    Inventors: Sergey Shumarayev, Rakesh H Patel, William W Bereza, Tim Tri Hoang, Thungoc Tran
  • Patent number: 7795943
    Abstract: An integrated circuit device has multiple first circuit elements arranged in a first area. A signal distribution circuit that has multiple drive circuits is connected in the form of a tree structure and that distributes a common signal that is input to the starting point of said tree structure to each of the multiple first circuit elements through the same number of levels of drive circuits. At least some of the drive circuits of the tree structure are arranged one each in each of multiple second areas into which the first area is divided to include approximately the same number of the first circuit elements, and the common signal is supplied to the first circuit elements included in the second area where they are arranged.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: September 14, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Yutaka Toyonoh, Tomohide Miyagi
  • Patent number: 7791382
    Abstract: Provided is a semiconductor integrated circuit which includes a logical operation circuit, a clock generator, a relay circuit, and a signal generating unit that are integrated. The clock generator generates multiphase clocks. The relay circuit distributes the generated multiphase clocks to the logical operation circuit. The signal generating unit detects phase states of the distributed multiphase clocks and, based on the detected phase states, generates an analog voltage signal having a voltage value indicative of a phase error in the multiphase clocks.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: September 7, 2010
    Assignee: NEC Corporation
    Inventor: Takaaki Nedachi
  • Patent number: 7786750
    Abstract: Methods and apparatus are provided for compensating for skew in a differential signal using non-complementary inverters. A skew attenuator is provided for a differential signal having a P rail and an N rail. The skew attenuator comprises one or more non-complementary inverters for compensating for skew between the P rail and the N rail. The non-complementary inverters attenuate a time difference of arrival of transitions for the P rail and the N rail. An exemplary skew attenuator includes a first non-complementary inverter associated with each of the P rail and the N rail. The P rail and the N rail signals are each applied to a gate of one of the first non-complementary inverters, and drains of the first non-complementary inverters provide differential output signals OUTP and OUTN. The exemplary skew attenuator also includes an additional non-complementary inverter associated with each of the first non-complementary inverters.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: August 31, 2010
    Assignee: Agere Systems Inc.
    Inventor: Shawn M Logan
  • Patent number: 7760000
    Abstract: A multiphase clock with high resolution is generated. A first clock generator circuit (120) includes n level converters BUFs that conduct level conversion on two input signals, and generate a pair of pulse signals that switch the levels with reference to a crossing point at which the two signal are identical in level with each other. An i-th BUF in the first clock generator circuit (120) inputs a one-side output pair that is respective one-side outputs of the differential outputs of two i-th (1?i?n) and (i+1)-th (1 when i=n) differential circuits in a ring oscillator 110 in which n differential circuits DCELs having differential inputs and outputs are connected in a ring configuration. The one-side output pair is two one-side outputs that are input to the noninverting terminal of the next differential circuit, or the two one-side outputs that are input to the inverting terminal of the next differential circuit.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: July 20, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Masaki Sano
  • Patent number: 7755408
    Abstract: A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/our preceding sub tree.
    Type: Grant
    Filed: October 8, 2007
    Date of Patent: July 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Sebastian Ehrenreich, Juergen Koehl, Juergen Pille
  • Patent number: 7746143
    Abstract: An object is to provide a clock generating circuit that can suppress variation of an oscillation frequency from the clock generating circuit, which is due to a change in the output voltage according to a discharging characteristic of the battery, and effectively utilize the remaining power of the battery. A structure includes an output voltage detecting circuit for detecting an output voltage from a battery; a frequency-division number determining circuit for determining the number of frequency-division by a value of the output voltage detected by the output voltage detecting circuit; an oscillation circuit for outputting a reference clock signal depending on the output voltage; a counter circuit for counting a number of waves of the reference clock signal that depends on the number of frequency-division; and a frequency-dividing circuit that frequency-divides the reference clock signal depending on the number of waves counted by the counter circuit.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: June 29, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventor: Masami Endo
  • Patent number: 7741890
    Abstract: A method and apparatus for generating multi-phase clock signals. The multi-phase generating method includes: generating L reference clock signal groups having predetermined phase delay intervals from an external clock signal, wherein each reference clock signal group includes M sub reference clock signals; averaging phases of sub reference clock signals for each reference clock signal group, and generating L main reference clock signals from the L×M sub reference clock signals; and sequentially delaying the L main reference clock signals, and generating the N multi-phase clock signals having the different phases. Because a plurality of clock signals having equal phase delay intervals between each other are generated regardless of the frequency of a received clock signal, the yield of Delay Locked Loop (DLL) circuits is improved using the multi-phase generating apparatus.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: June 22, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-hyuk Jeung, Kwang-ho Kim
  • Patent number: 7679416
    Abstract: The invention is directed to a method for clock distribution and VLSI circuits include a clock distribution network. In a method of the invention, a transmission lines are patterned as to connect a clock tree and a periodic waveform clock, preferably a sine waveform, is used to control clock skew, even at frequencies extending into the gigahertz range. In an exemplary embodiment of the invention, an overlay includes differential pairs of transmission lines that connect the drivers of a clock distribution tree. In preferred embodiments of the invention, an H-tree clock distribution scheme is overlayed with a spiral of transmission lines, each realized by a differential conductors and driven using a sinusoidal standing wave to distribute global clock signals into local regions of the chip. Each transmission line connects drivers in the H-tree that are at the same level of the H-tree.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: March 16, 2010
    Assignee: The Regents of the University of California
    Inventors: Chung-Kuan Cheng, Hongyu Chen
  • Patent number: 7667517
    Abstract: A system and method that use a first clock to digitally generate a second clock, wherein the ratio of the frequency of the first clock to the frequency of the second clock is a non-integer. Circuitry may be used to ensure that the first clock, or input clock, has a frequency at least equal to the highest of the desired output frequencies. The input clock may be used to generate several output clocks with different frequencies. If one of the output clocks has the same frequency as the input clock, the circuitry can be bypassed. The different clocks may be used to drive parts of a system, each of which may require a different frequency.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: February 23, 2010
    Assignee: Broadcom Corporation
    Inventor: John Iler
  • Patent number: 7667633
    Abstract: A time-to-digital converter includes low and high resolution time-to-digital converters for providing both high resolution and wide measurement range. The low resolution time-to-digital converter measures a time difference between first and second signals with a first quantization step. The high resolution time-to-digital converter measures the time difference between the first and second signals with a second quantization step that is smaller than the first quantization step. The low resolution time-to-digital converter has a wider measurement range than the high resolution time-to-digital converter.
    Type: Grant
    Filed: November 23, 2007
    Date of Patent: February 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyoung-Chul Choi, Seong-Hwan Cho, So-Myung Ha
  • Patent number: 7639058
    Abstract: The semiconductor device is provided with a clock signal generation circuit that includes a reference clock signal generation circuit which generates a first reference clock signal, a first counter circuit which counts the number of rising edges of the first reference clock signal by using the first reference clock signal and a synchronizing signal, a second counter circuit which counts the number of rising edges of the first reference clock signal by using an enumerated value of the first counter circuit, a first divider circuit which divides a frequency of the first reference clock signal by using the enumerated value of the first counter circuit and generates a second reference clock signal, and a second divider circuit which divides a frequency of the second reference clock signal and generates a clock signal.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: December 29, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Masami Endo, Hiroki Dembo, Daisuke Kawae, Takayuki Inoue, Munehiro Kozuma
  • Patent number: 7619454
    Abstract: The clock generator for semiconductor memory apparatus which includes: a first divider configured to divide a frequency of a first internal clock generated by using an external clock; a first delay unit configured to delay an output of the first divider by first delay time; a second divider configured to divide a frequency of an output of the first delay unit; a second delay unit configured to delay the output of the second divider by second delay time; a phase comparator configured to compare a phase of the output of the first divider with a phase of the output of the second delay unit and output a result of the comparison; and a delay time setting unit configured to set the first delay time on the basis of the output of the phase comparator.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: November 17, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyun-Woo Lee
  • Patent number: 7616042
    Abstract: For the purpose of achieving multiplexing of data signals for the channels of more than four in number in the generating of a frequency-divided clock signal using toggle flip-flop circuits (TFF), while avoiding any possible phase shift relationship between generated frequency-divided clock signals attributed to the indefinite initial state posing the inherent problem of the TFF, there is provided a clock generator circuit comprising a plurality of toggle flip-flop circuits connected in series, capable of outputting a pair of frequency-divided clock signals with different phases; and a delay circuit connected to the toggle flip-flop circuit, capable of outputting a clock signal with a phase shifted with respect to the phases of the pair of frequency-divided clock signal phases by delaying either one or both of the pair of frequency-divided clock signals being outputted from the toggle flip-flop circuits.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: November 10, 2009
    Assignee: Fujitsu Limited
    Inventor: Toshihide Suzuki
  • Patent number: 7616043
    Abstract: Methods and apparatus for distributing clock signals to an integrated circuit provide for: producing, in a slow mode of operation, a first clock signal having at least first and second on-pulses of differing first and second on-times each period, respectively, where a sum of the first and second on-times is approximately equal to a sum of off-times each period; distributing the first clock signal through a distribution tree and terminating at a plurality of final buffer circuits that produce respective distributed clock signals from which respective second clock signals are produced to supply at least a portion of the integrated circuit; deleting the second on-pulse from each of the distributed clock signals each period to produce the respective second clock signals, the second clock signals each including at least a portion of the first on-pulse, but none of the second on-pulse each period.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: November 10, 2009
    Assignee: Sony Computer Entertainment Inc.
    Inventor: Chiaki Takano
  • Patent number: 7612597
    Abstract: An electronic circuit for performing clock gating on a clock signal supplied to a clock system using both edges, has a non-inverted/inverted signal selector which has an input connected to an input terminal, is fed with the clock signal through the input terminal, and outputs a first signal obtained by non-inverting or inverting the clock signal in response to a control signal; a signal latch which has an input connected to an output of the non-inverted/inverted signal selector, outputs the inputted first signal as a second signal through an output terminal, and latches a state of the second signal in response to an enable signal inputted through an enable terminal; and an input/output comparator which compares the clock signal and the second signal and outputs the control signal to the non-inverted/inverted signal selector such that the first signal agrees with the second signal.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: November 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shuuji Matsumoto
  • Patent number: 7605631
    Abstract: A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains when the time delay of the adjustable delay circuit from which one of the clock signals is output is changed.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: October 20, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. LaBerge
  • Publication number: 20090243687
    Abstract: Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.
    Type: Application
    Filed: April 1, 2008
    Publication date: October 1, 2009
    Inventors: David Lewis, David Cashman, Jeffrey Christopher Chromczak
  • Patent number: 7567110
    Abstract: A clock distribution circuit for distributing an input clock according to an embodiment of the present invention includes: a first clock buffer receiving the clock; a first clock mask series-connected to the first clock buffer and controlling clock input to the first clock buffer; a second clock buffer series-connected to the first clock buffer and receiving a clock output from the first clock mask; and a second clock mask series-connected to the first clock buffer and the second clock buffer to control clock input to the second clock buffer.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: July 28, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Shinichi Shionoya
  • Patent number: 7567108
    Abstract: The invention is related to an apparatus and a method for generating an output clock. The method comprises: receiving a transmitted signal comprising at least one data signal and at least one synchronized signal; producing a reference signal according to the synchronization signal; counting the first reference signal according to a free-run clock outputted by a free-run clock generator to produce a counter signal; and generating the output clock according to the counter signal and the free-run clock.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: July 28, 2009
    Assignee: Realtek Semiconductor Corp.
    Inventors: Sen-Huang Tang, Wen-Chung Lai
  • Patent number: 7548106
    Abstract: The internal read signal generator according to the present invention includes: a first delay unit for delaying a clock signal in order to obtain a margin of a setup/hold time of an input signal; a signal transfer unit for transferring the input signal in synchronization with the delayed clock signal of the first delay unit; a second delay unit for delaying an output signal of the signal transfer unit; and an output unit for combining the input signal and an output signal of the second delay unit, wherein an amount of the delay of the second delay unit is determined in order that a rising edge of an output signal of the output unit has a period of the clock signal.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: June 16, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Sic Yoon
  • Patent number: 7548101
    Abstract: A delay locked loop circuit for a semiconductor memory apparatus includes a duty cycle correcting part that corrects and outputs duty cycles of internal clocks. A clock pulse width detecting part detects a pulse width of an external clock and outputs a pulse width detecting signal. A driving part divides a phase of the output of the duty cycle correcting part, adjusts a pulse width of at least one of two signals, which are obtained by dividing the phase, in accordance with the pulse width detecting signal, and outputs the two signals as delay locked loop clocks.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: June 16, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seok-Bo Shim
  • Patent number: 7535278
    Abstract: A clock manager circuit includes a number of clock output blocks, each providing an independent output. Counter controlled delay devices (CCDs) are used in these clock output blocks. To achieve full cycle delays, the CCDs are placed in parallel with outputs of the CCD outputs driving set and reset terminals of a common latch. The parallel connection of the CCDs, as opposed to a series connection, offers an increase in maximum frequency and possibly fewer needed CCDs than if the CCDs are placed in series. In one embodiment, at least one of the CCDs includes a counter/compare circuit with a frequency divider enabling the frequency of the CCD to be varied relative to the common input clock.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: May 19, 2009
    Assignee: Xilinx, Inc.
    Inventors: Robert M. Ondris, Raymond C. Pang, Kwansuhk Oh
  • Patent number: 7532043
    Abstract: The present disclosure relates to a system, apparatus and method for a line driver circuit to generate a signal detect (SD) signal when an invalid data signal is detected at its input. An invalid signal may be present either when no signal is available or when the line driver circuit or another component in the system (e.g., a crosspoint switch, a multiplexer, etc.) fails. The SD signal is coupled to an external controller that can either power down the line driver circuit to save power when no signal is available, or change over to a different line driver circuit or other component of the system when a failure is identified. When the input signal is determined to be a valid data signal via the SD signal, the line driver circuit can be enabled for operation. The described systems, apparatus and methods can save the user from having to directly control the line driver power state, especially in systems with large router configurations that may include hundreds of line drivers.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: May 12, 2009
    Assignee: National Semiconductor Corporation
    Inventor: Robert Karl Butler
  • Patent number: 7528642
    Abstract: A semiconductor integrated circuit device includes a semiconductor substrate having a first area. A first counter is provided in the first area, cyclically counts and outputs a first counter signal as a result of counting. A global reset circuit is provided on the semiconductor substrate and outputs a global reset signal. A first local reset circuit is provided in the first area and outputs a first local reset signal upon receiving the first counter signal of a set value after supplied with the global reset signal. A first circuit is provided in the first area and supplied with the first local reset signal.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: May 5, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Ishigaki
  • Patent number: 7521978
    Abstract: A clock driver is provided. A first driving unit is configured with a plurality of drivers and receives a first clock signal to drive a first pumping clock. A second driving unit is configured with a plurality of drivers and receives a second clock signal to drive a second pumping clock. A charge recycling switch is connected between an output terminal of the first driving unit and an output terminal of the second driving unit. A switch controller selectively transfers an input clock signal of the first or second driving unit to the charge recycling switch in response to the first and second pumping clock signals.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: April 21, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dong-Hwan Kim, Si-Nae Kim, Kae-Dal Kwack, Jae-Jin Lee
  • Patent number: 7495496
    Abstract: The present invention is to provide a method and circuit for producing spread spectrum and over clock, which includes a primary circuit and a secondary circuit, wherein the primary circuit uses a frequency division technique based on phase swallow to achieve a high frequency resolution clock signal, and the secondary circuit multiplies the frequency of the output clock signal of the primary circuit, so as to expand its frequency range.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: February 24, 2009
    Assignee: Realtek Semiconductor Corp.
    Inventors: Peng-Zhan Zhang, Li-Jun Gu, Ran Ding
  • Patent number: 7489176
    Abstract: A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: February 10, 2009
    Assignee: Rambus Inc.
    Inventors: Kambiz Kaviani, Tsu-Ju Chin
  • Publication number: 20090033398
    Abstract: A wiring structure for clock signals has two or more parallel clock signal wires disposed in adjacent power wire bays that span the distance between the sinks to which the clock signal wires are to be coupled. The parallel clock signal wires are shorted one to another by stubs placed at locations in order to time the clock wiring structure. The delay tuning of the structure is obtained by the discrete movement of wiring stubs between the wiring bays of the pre-defined power grid.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 5, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rick L. Dennis, Charlie C. Hwang, Jose L. Neves
  • Patent number: 7486126
    Abstract: This invention provides a technique for enhancing an operating frequency and improving reliability in a system using at least level sense type sequence circuits as a plurality of sequence circuits. A microcomputer includes a clock generator configured as a clock supply source, functional modules operated in sync with a clock signal, level sense type sequence circuits which are contained in the functional modules and configured as clock supply destinations, a clock supply system which propagates the clock signal to the level sense type sequence circuits, etc. The clock supply system includes a clock wiring which propagates the clock signal outputted from the clock generator to ends thereof via a plurality of branches. At least pulse generators are disposed in the midstream of the clock wiring. Each of the pulse generators varies timing provided to change the falling edge of the clock signal, which defines an endpoint of an input operating period of each level sense type sequence circuit.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: February 3, 2009
    Assignee: Renesas Technology Corp.
    Inventor: Yasuhisa Shimazaki
  • Patent number: 7474137
    Abstract: A circuit is provided with a plurality of interconnected logic blocks, a main clock generator for distributing a reference clock signal to the logic blocks. Each logic block in the circuit comprises a local clock generator that generates a set of synchronized local clock signals from the reference clock signal for further provision to respective elements of the logic block. In such a circuit, a phase shift is introduced between a set of local clock signals of a first block and a set of local clock signals of a second block.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: January 6, 2009
    Assignee: NXP B.V.
    Inventors: Sylvain Duvillard, Isabelle Delbaere
  • Publication number: 20080303552
    Abstract: Disclosed herein is a digital system that includes a distribution network to carry a reference clock and a plurality of circuit domains coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. Each circuit domain of the plurality of circuit domains includes a respective clock generator driven by the reference clock to generate a resonant clock signal, respective circuitry coupled to the clock generator to operate in accordance with the resonant clock signal, with the circuitry including a capacitive load for the resonant clock signal and a respective inductance coupled to the circuitry and the clock generator to resonate the capacitive load of the circuitry.
    Type: Application
    Filed: December 3, 2007
    Publication date: December 11, 2008
    Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou
  • Patent number: 7463076
    Abstract: A power consumption reduction circuit for reducing power consumed by a clock tree network including a transmission control circuit. The power consumption reduction circuit includes a transmission control circuit for controlling transmission of the clock signal to the buffer circuit group so as to selectively provide and interrupt the clock signal. A switch circuit disconnects the buffer circuit group from a power supply when the transmission control circuit interrupts the clock signal.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: December 9, 2008
    Assignee: Fujitsu Limited
    Inventors: Kazufumi Komura, Takayoshi Nakamura, Keiichi Fujimura, Masahito Hirose, Keigo Nakashima, Masaki Nagato
  • Publication number: 20080284483
    Abstract: A clock distribution circuit having plural stages of buffers disposed along branch paths for dividing up a clock signal and configured in a manner that outputs of a plurality of buffers in a final stage and/or a middle stage are short-circuited, includes in relation to at least one buffer of a plurality of buffers in the same stage on a branch path, a selector for receiving an output of an adjacent buffer located upstream in terms of chain-connection along which the plurality of buffers are connected in testing, and a signal at a branch node corresponding to the at least one buffer by a first input and a second input respectively, selecting one of the first input and the second input based on a select control signal, and supplying the selected input to the one buffer.
    Type: Application
    Filed: September 25, 2007
    Publication date: November 20, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hidemi Nakashima
  • Patent number: 7446587
    Abstract: The invention provides a semiconductor device which can suppress a variation of clock signals. According to the invention, a single clock signal is divided into a plurality of clock signals and supplied to each of a plurality of circuits in a semiconductor device. Propagation delay time of each of the clock signals is not completely fixed in a design phase, but a circuit (variable delay circuit) which can appropriately change propagation delay time of a clock signal even after forming the semiconductor device is provided. By using the variable delay circuit, a variation in the propagation delay time is compensated so that a circuit provided in a subsequent stage of the variable delay circuit can operate normally on a desired condition. In specific, a phase of each clock signal is controlled.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: November 4, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Patent number: 7443221
    Abstract: A system and method that use a first clock to digitally generate a second clock, wherein the ratio of the frequency of the first clock to the frequency of the second clock is a non-integer. Circuitry may be used to ensure that the first clock, or input clock, has a frequency at least equal to the highest of the desired output frequencies. The input clock may be used to generate several output clocks with different frequencies. If one of the output clocks has the same frequency as the input clock, the circuitry can be bypassed. The different clocks may be used to drive parts of a system, each of which may require a different frequency.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: October 28, 2008
    Assignee: Broadcom Corporation
    Inventor: John Iler
  • Patent number: 7427879
    Abstract: The present invention discloses a frequency detecting apparatus for detecting a frequency of an input clock. The frequency detecting apparatus includes: a pulse generator, a digital signal generator, and a decoder. The pulse generator is coupled to the input clock for extracting a period of the input clock to generate a pulse, and the digital signal generator is coupled to the pulse generator for converting the pulse into a plurality of logic values. The digital signal generator includes: a delay module coupled to the pulse, for delaying the pulse to generate a plurality of delayed pulses according to a plurality of delay amounts, respectively; and a sampling module coupled to the delay module for sampling the pulse to generate the logic values according to the delayed pulses, respectively. The decoder is coupled to the digital signal generator for determining the frequency of the input clock according to the logic values.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: September 23, 2008
    Assignee: Nanya Technology Corp.
    Inventor: Wen-Chang Cheng
  • Patent number: 7423470
    Abstract: A split signal pulse generator (“SSPG”) that generates a difference signal from two split signals from a splitter module, where one of the split signals may be time delayed by a delay module, where the delay module may be a transmission line having a time delay or an adjustable delay line. The SSPG may include an input amplifier configured to shape an input signal received by the splitter module. A method of generating a difference signal is also provided.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: September 9, 2008
    Assignee: Agilent Technologies, Inc.
    Inventors: Daniel B. Gunyan, Jonathan B. Scott
  • Publication number: 20080204104
    Abstract: A method and apparatus for distributing clock signals throughout an integrated circuit is provided. An embodiment comprises a distribution die which contains either the clock signal distribution network by itself, or the clock signal distribution network in tandem with a clock signal generator. The distribution die is electrically connected through an interface technology, such as microbumps, to route the clock signals to the functional circuits on a separate functional die. Alternatively, the distribution die could be electrically connected to more than one die at a time, using vias through the distribution die to route the clock signals to the different die. This separate distribution die reduces the coupling between lines and also helps to prevent signal skew as the signal moves through the distribution network.
    Type: Application
    Filed: February 27, 2007
    Publication date: August 28, 2008
    Inventor: Mark Shane Peng
  • Patent number: 7403058
    Abstract: A test clock generating apparatus is provided in the invention. The test clock generating apparatus includes an at-speed clock generator and a multiplexer. The at-speed clock generator is for receiving a reference clock signal and a scan chain enable signal and outputting an at-speed clock signal. The frequency of the at-speed clock signal is substantially the same with that of the reference clock signal. The multiplexer is for receiving the at-speed clock signal and a scan chain clock signal and outputting a test clock signal according to the scan chain enable signal. The frequency of the reference clock signal is higher than that of the scan chain clock.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: July 22, 2008
    Assignee: Realtek Semiconductor Corporation
    Inventors: Ta-Chia Yeh, Chien-Kuang Lin, Chi-Feng Wu
  • Patent number: 7382171
    Abstract: There is provided a semiconductor circuit including three or more nodes at least including one input node and one output node, plural paths which are connected between the three or more nodes and whose signal propagation directions between the nodes are regulated, a signal propagation time regulator for regulating a signal propagation time of each of the paths, an input unit for inputting a predetermined input signal to the input node, and a detector for detecting a time required for the input signal to propagate through the paths and arrive at the output node.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: June 3, 2008
    Assignee: Rohm Co., Ltd.
    Inventors: Makoto Ogawa, Tadashi Shibata
  • Patent number: 7348863
    Abstract: A pulse generating circuit and related method, for producing extremely narrow pulses for use in monolithic microwave integrated circuits (MMICs) for radar, high-speed sampling, pulse radio and other applications. A sinusoidal input signal is supplied to two nonlinear shock wave generators, which are oppositely biased to produce periodic outputs that are mirror images of each other, one with a very steep rising edge and one with a very steep falling edge. The combined outputs would cancel each other completely but for the introduction of a slight time delay in one of them, which results in a narrow peak in the combined signals.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: March 25, 2008
    Assignee: Northrop Grumman Corporation
    Inventors: Mark Kintis, Flavia S. Fong
  • Patent number: 7348837
    Abstract: For distributing a signal to loads in an area, the area is divided into a plurality of regions. A respective signal point is disposed in each region for providing the signal to a load in the region. A respective diffusion point is disposed between any two neighboring signal points. The signal is initially applied to a center point of the signal and diffusion points. The signal when received at a given signal or diffusion point is transmitted to any of the signal or diffusion points within a maximum distance from the given signal or diffusion point.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: March 25, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gun-Ok Jung, Young-Min Shin
  • Patent number: 7339412
    Abstract: The invention relates to a clock generator comprised of a system clock input (2) for applying a high-frequency system clock signal, of a digital input (3) for applying a settable digital increment value, of an adder (6) for adding the increment value with the feedback digital cumulative value of the adder, of an output register (13) for outputting the highest-order data bit of the digital cumulative value as an output clock signal of the clock generator (1) over an output clock line, and of a digital phase deviation calculating unit (30) for calculating the phase deviation of the output clock signal according to the remaining low-order data bits of the digital cumulative value and of the digital increment value, whereby the phase deviation is output as a digital phase deviation value to a digital data output (29).
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: March 4, 2008
    Assignee: Micronas GmbH
    Inventor: Hartmut Beintken
  • Patent number: 7336116
    Abstract: The clock supply circuit of the present invention comprises a plurality of clock supply paths and a clock gate circuit. The clock supply paths branch a clock signal and supply each of the branched clock signals to a plurality of sequential circuits via a buffer. The clock gate circuit is inserted at least to one of the clock supply paths, which lets through the clock signals when a control signal is in a first logic state and, when the control signal is in a second logic state, outputs an inversion signal of a logic level that is outputted in a previous occasion where the control signal in the second logic state is applied.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: February 26, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akio Hirata, Takahiro Ichinomiya, Takashi Ando
  • Patent number: 7336115
    Abstract: A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/or preceding sub tree.
    Type: Grant
    Filed: February 8, 2006
    Date of Patent: February 26, 2008
    Assignee: International Business Machines Corporation
    Inventors: Sebastian Ehrenreich, Juergen Koehl, Juergen Pille
  • Patent number: 7327180
    Abstract: An information processing apparatus is constructed by a system PLL, a first unit, a second unit, and a system board on which they are mounted. A delay setting circuit in which a variation and delay elements (a gate delay and a line delay) which are equivalent to those of a clock tree circuit for a gate have been set at the designing stage is provided on a signal line of a system clock in the first unit to the second unit. A delay setting circuit in which a variation and delay elements which are equivalent to those of the clock tree circuit for the gate have been set at the designing stage is provided on a signal line of a clock gate signal to the second unit.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: February 5, 2008
    Assignee: Fujitsu Limited
    Inventor: Kazue Yamaguchi
  • Patent number: 7317343
    Abstract: In one embodiment of the invention, a pulse-generation circuit for generating control signals has clock-delay circuitry for generating a plurality of differently delayed clock signals. Each control signal is generated by a set-reset latch that receives its set and reset signals from different pulse generators operating based on different delayed clock signals from the clock-delay circuitry. In one implementation, the clock-delay circuitry has a partitioned delay block in which different sub-blocks provide different delay functionality to provide the clock-delay circuitry with programmable flexibility.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: January 8, 2008
    Assignee: Lattice Semiconductor Corporation
    Inventors: Louis De La Cruz, Hemanshu T. Vernenker
  • Patent number: 7310011
    Abstract: The present invention relates to a clock signal distribution circuit for distributing the clock signal to circuits such as LSI integrated circuits, and, more specifically, provides a clock adjuster circuit, which performs phase difference adjustment of clock signals automatically. It is a circuit, which on driving a circuit element implemented on an LSI chip, supplies the clock signal, which is a reference for driving, is distributed subsequently from first distribution to lower-level distributions of a hierarchical structure, or from a fifth level distribution circuit “5” to every area on the LSI chip, for example. At that time, delay of the clock signal is detected by a phase difference detector circuit, the delay data is automatically written to a delay adjuster circuit built into each of the fifth level distribution circuits “5”. Using the delay data, the phase difference of the clock signals, is adjusted when the LSI chip is manufactured.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: December 18, 2007
    Assignee: Fujitsu Limited
    Inventor: Katsunao Kanari
  • Patent number: 7304522
    Abstract: A spread spectrum clock generator includes a plurality of delay cells, wherein each delay cell includes at least one delayer receiving an external clock signal and causing a predetermined propagation delay to the received clock signal, and a controller transmitting a control signal to the delayer to control the propagation delay of the delayer according to a state value of the control signal. With this configuration, the spread spectrum clock generator using a delayer can have a simple circuit configuration and effectively attenuate an EMI.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: December 4, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-hoon Kim, Pil-jung Jun, Jung-gun Byun, Dong-gun Kam, Joung-ho Kim