Abstract: An information processing apparatus is constructed by a system PLL, a first unit, a second unit, and a system board on which they are mounted. A delay setting circuit in which a variation and delay elements (a gate delay and a line delay) which are equivalent to those of a clock tree circuit for a gate have been set at the designing stage is provided on a signal line of a system clock in the first unit to the second unit. A delay setting circuit in which a variation and delay elements which are equivalent to those of the clock tree circuit for the gate have been set at the designing stage is provided on a signal line of a clock gate signal to the second unit.

Abstract: In one embodiment of the invention, a pulse-generation circuit for generating control signals has clock-delay circuitry for generating a plurality of differently delayed clock signals. Each control signal is generated by a set-reset latch that receives its set and reset signals from different pulse generators operating based on different delayed clock signals from the clock-delay circuitry. In one implementation, the clock-delay circuitry has a partitioned delay block in which different sub-blocks provide different delay functionality to provide the clock-delay circuitry with programmable flexibility.

Abstract: The present invention relates to a clock signal distribution circuit for distributing the clock signal to circuits such as LSI integrated circuits, and, more specifically, provides a clock adjuster circuit, which performs phase difference adjustment of clock signals automatically. It is a circuit, which on driving a circuit element implemented on an LSI chip, supplies the clock signal, which is a reference for driving, is distributed subsequently from first distribution to lower-level distributions of a hierarchical structure, or from a fifth level distribution circuit “5” to every area on the LSI chip, for example. At that time, delay of the clock signal is detected by a phase difference detector circuit, the delay data is automatically written to a delay adjuster circuit built into each of the fifth level distribution circuits “5”. Using the delay data, the phase difference of the clock signals, is adjusted when the LSI chip is manufactured.

Abstract: A spread spectrum clock generator includes a plurality of delay cells, wherein each delay cell includes at least one delayer receiving an external clock signal and causing a predetermined propagation delay to the received clock signal, and a controller transmitting a control signal to the delayer to control the propagation delay of the delayer according to a state value of the control signal. With this configuration, the spread spectrum clock generator using a delayer can have a simple circuit configuration and effectively attenuate an EMI.

Abstract: An apparatus is disclosed which includes a signal generator providing a first signal having a first frequency; a clock tree operative to propagate the first signal to at least one clock mesh of the apparatus; and a final buffer operative to receive the first signal, provide a second signal having a second frequency, synchronize the second signal with the first signal, and propagate the synchronized second signal to at least one other clock mesh of the apparatus.

Abstract: A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.

Abstract: An apparatus for measuring the time delay between adjacent clock edges includes target and delay signal paths, a variable delay module in said delay signal path, the delay cell having a delay bias input, and a phase detector having respective inputs coupled to the target and delay signal paths. The variable delay module is operable to delay a first clock signal on the delay path so that a bias input signal presented to the delay bias input, when a bias input signal is present, corresponds to the time delay between the first clock signal and a second clock signal on the target signal path.

Abstract: Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock signal. A second series of feedback delay circuits mirror respective first delay circuits. After the input signal has been coupled through the first delay circuits, the mirrored signals from the first delay circuits are coupled through the feedback delay circuits. The delay of the feedback delay circuits is one-half the delay of the first delay circuits to provide a signal that is the quadrature of the clock signal.

Abstract: Distributed traveling wave oscillator circuitry is disclosed. The oscillator circuitry includes a signal path, a plurality of active switching means, and a direction promoting means. The signal path is formed from a pair of adjacent conductors and exhibits endless electric or magnetic continuity. The signal path also includes a portion that creates a signal phase inversion which sets half-cycles of oscillation to be the time of a single traverse of the signal path by the signal. The plurality of active switching means is connected between the adjacent conductors of the signal path for setting rise and fall times of each said half-cycle of oscillation. The direction promoting means establishes the direction of the traveling wave on the signal path.

Abstract: A pulse generator electrical circuit capable of operating as both a clock-based pulse generator and a delay-based pulse generator while minimizing the limitations of these two types of pulse generators is disclosed. When the pulse generator operates in “delay mode,” the smallest output pulse width possible corresponds to the minimum set point delay between the two delay circuits. The largest possible output pulse width corresponds to the difference between the maximum and minimum of the delay circuits. When the pulse generator operates in “clock mode,” the output of one of the delay circuits is blocked so that the output of the gate depends solely on the output of other delay circuit. This limits the lower pulse width interval to that of the retimer clock, but allows for an arbitrarily long (wide) pulse.

Abstract: Signal transmission circuitry on an integrated circuit ameliorates the effects of possible inequality in rise and fall times of buffer circuits along the transmission circuitry by providing at least one of the buffer circuits as an inverting buffer circuit and at least one other of the buffer circuits as a non-inverting buffer circuit. The invention may be of particular interest for use in clock signal distribution networks on integrated circuits such as programmable logic devices.

Abstract: The present invention relates to the field of electronics. More particularly, forms of the present invention relate to systems, methods and circuits for generating a signal. A system, method and circuit for generating a signal are described. Forms of this system, method and circuit provide clock duty cycle improvement with no frequency reduction. Some such forms provide a clock signal approaching or achieving 50 percent with no significant frequency departure, reduction, etc. from a generated clock. One form of the present invention uses two similar clock signals that oscillate at the same frequency, but effectively inverted one from another. In one such form, the inverted signals are generated with a voltage controlled oscillator having differential stages.

Abstract: Provided are a method and apparatus for reducing the number of power ports equipped with an integrated circuit (IC) apparatus by reducing the number of bus outputs that are simultaneously switched, with the use of a master clock signal and a slave clock signal, which is a variation of the master clock signal. The IC apparatus includes a slave clock signal generator, which receives the master clock signal and generates a slave clock signal for controlling simultaneously switching outputs; and a flipflop circuit, which transmits a signal to an external device in synchronization with the slave clock signal.

Abstract: A technique implements high impedance nodes using high threshold voltage devices that may generate less leakage current and may have a higher gate oxide breakdown voltage than standard devices in a particular manufacturing technology. Under at least one operating condition, for a particular power supply voltage, a circuit may unable to produce a control signal that is sufficient to turn on such a high threshold voltage device. The technique adjusts the control signal voltage to provide a gate-to-source voltage sufficient to turn on the high threshold voltage device. At another power supply voltage, when the circuit is able to produce a control signal sufficient to turn on the high threshold voltage device, the technique does not adjust the control signal.

Abstract: A clocking system for a memory that accomplishes these and other objectives has an external clock. A clock shaper has an input coupled to the external clock and an access clock at an output. A first delay block has an input coupled to the external clock and an output coupled to a master of an output register. A slave of the output register is coupled to the external clock. By having the master clock trailing the slave clock a temporary transparency window condition is created at the output register, allowing an improved cycle time (speed) prime bin distribution.

Abstract: A system for distributing a small signal differential signal to a circuit element. The system includes: a first converter configured to convert a first small signal differential signal to a first two phase full CMOS differential signal for input into the differential multiplexer; and a programmable driver circuit configured to boost an output current of the programmable driver circuit at selected frequencies and to convert two phase full CMOS differential signal outputs of the differential multiplexer to a second small signal differential signal.

Abstract: A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

Abstract: Methods and Apparatuses for generating and distributing a clock signal between components within a semiconductor chip. According to one embodiment of the invention, a clock generator, distributed over an integrated circuit, includes a plurality of cells each coupled to multiple adjacent ones of the plurality of cells by different clock wires; wherein, for each of the plurality of clock wires, the cell on one end generates the rising edge and the cell on the other end generates the falling edge. According to another embodiment of the invention, an integrated circuit includes a distributed clock generator and a plurality of sets of synchronous logic. The distributed clock generator includes a plurality of cells and a plurality of clock wires. The plurality of clock wires each couple together two of said plurality of cells such that said plurality of cells are coupled together in grid.

Abstract: A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

Abstract: An information processing apparatus is constructed by a system PLL, a first unit, a second unit, and a system board on which they are mounted. A delay setting circuit in which a variation and delay elements (a gate delay and a line delay) which are equivalent to those of a clock tree circuit for a gate have been set at the designing stage is provided on a signal line of a system clock in the first unit to the second unit. A delay setting circuit in which a variation and delay elements which are equivalent to those of the clock tree circuit for the gate have been set at the designing stage is provided on a signal line of a clock gate signal to the second unit.

Abstract: Described are methods and systems for distributing low-skew, predictably timed clock signals. A clock distribution network includes a plurality of dynamically adjustable clock buffers. A control circuit connected to each clock buffer controls the delays through the clock buffers in response to process, voltage, and temperature variations, and consequently maintains a relatively constant signal-propagation delay through the network. In one embodiment, each clock buffer includes skew-offset circuitry that adds to or subtracts from the PVT compensated delay values provided by the PVT control circuit to simplify clock skew minimization.

Abstract: The invention provides a clock delay arrangement accounting for the worst-case delay situation of data signals, which is independent of the layout and technology. It comprises a main clock line; two dummy clock lines, each arranged parallel to the main clock line, and the main clock line disposed between the two dummy clock lines; and a clock source coupled to the main clock line and the two dummy clock lines, adapted to drive said dummy clock lines in phase opposition with respect to the main clock line.

Abstract: Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock signal. A second series of feedback delay circuits mirror respective first delay circuits. After the input signal has been coupled through the first delay circuits, the mirrored signals from the first delay circuits are coupled through the feedback delay circuits. The delay of the feedback delay circuits is one-half the delay of the first delay circuits to provide a signal that is the quadrature of the clock signal.

Abstract: In integrated circuit (IC) devices, skew concerns between the clock pulses supplied to different latches hinder high speed operation. An IC device therefor includes a first clock processor means to generate a third clock pulse in response to first and second clock pulses with identical phase and frequency, a second clock processor means to generate a fifth clock pulse in response the third clock pulse and a fourth clock pulse with identical phase and frequency, and first and second latch groups each including a plurality of latches, in which the second clock pulse is generated via a buffer or divider from the third clock pulse, a fourth clock pulse is generated via a buffer or divider from the fifth clock pulse, and the third and fifth clock pulses are supplied to the first and second latch groups via a buffer, respectively.

Abstract: An integrated circuit having a clock calibration device receiving a local clock signal from an oscillator and applying a correction value to the signal to produce a corrected clock signal. The clock calibration device includes a frequency dividing module having a programmable divider and a calibration register for storing the correction value, the programmable divider receiving the local clock signal and delivering the corrected clock signal, and a circuit for determining a new correction value using an external reference signal. A time base unit produces a time base signal using a timing signal derived from the local clock signal, and it includes a counting module coupled to a load register wherein a load value is stored that determines the ratio between the frequency of the time base signal and that of the timing signal. An external computing unit loads a new load value into the load register by using the new correction value stored in the calibration register to deduce the new load value therefrom.

Abstract: The invention provides an apparatus adapted for supplying a plurality of clock signals. The apparatus comprises a set of clock signal circuits for generating m clock signals of at least two different signal periods, with m being a natural number, and a superperiod signal-generating unit adapted for deriving, from a dedicated clock signal of said set of clock signals, a first superperiod signal. The signal period of said first superperiod signal is a common multiple of the clock signals' signal periods.

Abstract: In order to provide a semiconductor integrated circuit equipped with a clock distribution circuit that enables clock skew to be reduced without requiring great effort and without being affected by temperature variations or voltage variations, and a manufacturing method thereof, in a clock distribution circuit 1 installed in a semiconductor integrated circuit, part of the distribution path of a clock signal that passes from a first selector 11 of a first circuit block 10 that has many buffer stages via a first buffer stage 10A is used, and a distribution path of a clock signal to a second buffer stage 20A of a second circuit block 20 that has few buffer stages is constructed.

Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

Abstract: A clock control circuit in an integrated circuit for providing a differential clock signal to a differential clock tree. The clock control circuit includes: first differential multiplexers configured to select first outputs from the input clock signals; second differential multiplexers coupled to the first differential multiplexers and configured to select second outputs from the first outputs; loop back signal lines configured to feed back the second outputs to at least part of the input clock signals of the first differential multiplexers; and differential signal lines of the differential clock tree coupled to the second outputs.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a gated clock signal in response to (i) a write enable signal and (ii) a system clock signal. The gated clock signal is pulsed active while the write enable signal is active. The second circuit may be configured to generate the write enable signal.

Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

Abstract: A circuit for establishing frequency and phase alignment of clock signals across a domain of analog blocks coupled in a single integrated circuit. Different analog functions are implemented by selectively and electrically coupling different combinations of analog blocks. The analog blocks may be arrayed in a number of columns. The circuit is coupled to the analog blocks to supply a synchronized clock signal to all of the analog blocks in a combination of blocks, even when the blocks are in different columns. The circuit allows the frequency of the clock signal to be changed dynamically depending on the analog function to be achieved. The circuit also establishes phase alignment when a frequency change occurs.

Abstract: Transistor bodies are biased to modify delay in clock buffers.

Abstract: The present invention provides a semiconductor integrated-circuit device capable of achieving higher-density integration and faster operation, and a CMOS circuit operational speeding-up method for easily achieving the operating speeds of CMOS circuits, including existing one. A signal transferring path includes a plurality of CMOS-constructed logic gate circuits provided between one pair of flip-flop circuits for acquiring and holding signals by use of clock signals. The signal transferring path includes a first and a second signal transferring path. The first signal transferring path is constituted by enhancement-type MOSFETs and has a signal transferring delay time equal to, or less than, a permissible signal transferring delay time.

Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

Abstract: A synchronized optical clocking signal is provided to a plurality of optical receivers by providing a layer of a high absorption coefficient material, such as SiGe or Ge, on a front surface of a low absorption coefficient substrate, such as silicon. Diodes are formed in the germanium containing layer for receiving an optical signal and converting the optical signal into an electrical signal. An optical clocking signal is shined on the back surface of the silicon substrate. The light has a wavelength long enough so that it penetrates through the silicon substrate to the germanium containing layer. The wavelength is short enough so that the light is absorbed in the germanium containing layer and converted to the electrical clocking signal used for neighboring devices and circuits. The germanium concentration is graded so that minority carriers are quickly swept across junctions of the diodes and collected.

Abstract: An exemplary reduced-power-consumption network includes a frequency divider coupled through global clock lines to a plurality of double-edge triggered registers. Another exemplary network includes a plurality of individually programmable frequency dividers coupled through local clock lines to a plurality of double-edge triggered registers.

Abstract: The present invention relates to an integrated circuit comprising a first clock circuit delivering a first clock signal, a second clock circuit delivering a second clock signal, a first counting circuit for delivering a time base signal using a clock signal and a counting value, and means for applying the first clock signal and a first counting value to the first counting circuit, so as to produce a first time base signal. According to the present invention, the integrated circuit comprises means for producing a second time base signal using the second clock signal and a second counting value, and means for calibrating the second counting value such that it is equal or proportional to the number of periods of the second clock signal occurring during a determined time interval equal to a period or to a whole number of periods of the first time base signal. Application particularly to the management of a timer in a microprocessor.

Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

Abstract: In integrated circuit (IC) devices, skew concerns between the clock pulses supplied to different latches hinder high speed operation. An IC device therefor includes a first clock processor means to generate a third clock pulse in response to first and second clock pulses with identical phase and frequency, a second clock processor means to generate a fifth clock pulse in response the third clock pulse and a fourth clock pulse with identical phase and frequency, and first and second latch groups each including a plurality of latches, in which the second clock pulse is generated via a buffer or divider from the third clock pulse, a fourth clock pulse is generated via a buffer or divider from the fifth clock pulse, and the third and fifth clock pulses are supplied to the first and second latch groups via a buffer, respectively.

Abstract: A method and related circuitry for driving output signals of a chip is disclosed. The method includes driving output signals with an even number of inverter driving circuits, and keeping an equivalent load of each inverter of the driving circuits substantially identical by keeping impedances of each driving circuit substantially identical.

Abstract: A plurality of clock signal phases are distributed to a circuit and at least one jitter source is coupled between at least two selected clock phases of the plurality of clock signal phases to introduce a jitter between at least the selected two clock signal phases. In a specific embodiment, the clock distribution system provides N clock phases and, if the phases have an order, there is one jitter source provided between each of the first N?1 phases and the following phase, so that each phase has a jitter relative to each other phase. Several implementations are possible for the jitter sources, which can be noise sources or pseudo-random noise sources, depending on which is easier to design and implement in a specific clock distribution system.

Abstract: A clock system for providing a high-speed clock signal to a plurality of integrated circuits is disclosed. The clock system includes an analog signal generator for producing a periodic analog signal of a predetermined frequency and fanout circuitry. The fanout circuitry is coupled to the analog signal generator and includes a transmission line and an RF coupler. The system further includes a plurality of receivers. Each receiver has reference signal input circuitry and clock signal input circuitry. Both the reference signal circuitry and the clock signal circuitry are receptive to coupling locally generated common mode noise. The clock signal circuitry is disposed proximate the RF coupler to provide an RF coupling therebetween.

Abstract: A system and method of generating a clock. A first clock is accessed. A delayed version of the first clock is created. A second clock signal is generated. A first edge of the second clock signal corresponds to a transition of the first clock signal, and a second edge of the second clock signal corresponds to a transition of the delayed version of the first clock signal.

Abstract: A clock modulating circuit includes a first to nth delay circuits, a selection signal generator and a selection circuit. The first delay circuit receives an original clock signal and outputs a delayed clock signal. The second to nth delay circuits receive the delayed signal output from the preceding delay circuit and output delayed clock signals. The selection signal generator outputs a selection signal in response to the original clock signal. The selection signal has an instruction for selecting in ascending order from the first to nth delay circuits and then in descending order from the nth to first delay circuits. The selection circuit is connected to the first to nth delay circuits and the selection signal generator. The selection circuit receives the delayed signals from the first to nth delay circuits and outputs one of the delayed clock signals in response to the selection signal.

Abstract: Devices, methods, and networks that divide and proportionally distribute the drive strength of a clock buffer such that the output drive strength of the clock buffer is divided proportionally among a plurality of outputs from the clock buffer. In one embodiment, the present invention selectively couples adjacent parallel inverters present in a clock buffer to separate, internal distribution wires. The internal distribution wires are selectively coupled to one or more outputs by a connector wire to provide proportional, multiple outputs of the drive strength from the clock buffer to a clock network.

Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.