Abstract: There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.

Abstract: Circuits and methods for latch-tracking pulse generation across process, voltage and temperature (PVT) variations are disclosed. In one embodiment, the method includes receiving a clock input at a pulse generation circuit and generating a pulse at the pulse generation circuit in response to the clock input. The method further includes distributing the pulse to a mimic latch, which writes a mimic storage node through a mimic storage circuit of the mimic latch in response to the pulse. The method further includes terminating generation of the pulse at the pulse generation circuit in response to a transition of the mimic storage node. The method may include receiving a clock enable input at a pulse control circuit coupled to the pulse generation circuit and either suppressing or allowing generation of a pulse in response to a value of the clock enable input.

Abstract: A clock network includes a first plurality of shield wires associated with a first plurality of clock lines and a second plurality of shield wires associated with a second plurality of clock lines. The clock network also includes a first plurality of clock activity program circuits associated with the first plurality of clock lines and a second plurality of clock activity program circuits associated with the second plurality of clock lines, wherein the first and second plurality of shield wires and the first and second plurality clock activity program circuits are configured to reduce power spikes.

Abstract: A clock signal generation circuit includes a first oscillation circuit for generating a first oscillation clock signal having a first frequency; a second oscillation circuit for generating a second oscillation clock signal having a second frequency; a frequency division circuit for generating a frequency division clock signal obtained through dividing the first oscillation clock signal; and a clock selection circuit for outputting the first oscillation clock signal as a high speed clock signal. The clock selection circuit is configured to output the second oscillation clock signal as the low speed clock signal when the second oscillation circuit transmits the second oscillation clock signal, and to output the frequency division clock signal as the low speed clock signal when the second oscillation circuit does not transmit the second oscillation clock signal.

Abstract: A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.

Abstract: Pulse-generator circuits that permit independent control of pulse widths and the delays between successive pulses. In several embodiments, a pulse-generator subcircuit includes a transmission-line segment comprising first and second conductors, configured such that the first conductor is coupled to a first DC potential. The pulse-generator subcircuit further includes a terminating resistor coupled to a first end of the second conductor of the first transmission-line segment; this terminating resistor is matched to the characteristic impedance of the transmission-line segment. The pulse-generator subcircuit further includes first and second switches, controlled by first and second timing signals, respectively, and configured to selectively and independently connect respective first and second ends of the first conductor to a second DC potential.

Abstract: There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. On each of the two or more strata, the clock distribution network includes a clock grid having a plurality of sectors for providing the global clock signals to various chip locations, a multiple-level buffered clock tree for driving the clock grid and including at least a root and a plurality of clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree. Inputs of at least some of the plurality of clock buffers on each of the two or more strata are shorted together using chip-to-chip interconnects to reduce skewing of the global clock signals with respect to the various chip locations.

Abstract: A phase recombination circuit includes a first phase input and a first one-shot pulse generator adapted to receive the first phase input and produce a first signal to pull a signal to a first state. The phase recombination circuit also includes a second phase input in phase relationship with the first phase input, and a second one-shot pulse generator adapted to receive the second phase input and produce a second signal to pull a signal to a second state.

Abstract: An enhanced complementary waveform generator (ECWG) generates two complementary pulse width modulation (PWM) outputs determined by rising and falling event sources. In a simple configuration of the ECWG, the rising and falling event sources are the same signal which is a PWM signal having the desired period and duty cycle. The ECWG converts this single PWM input into dual complementary PWM outputs. The frequency and duty cycle of the dual PWM outputs substantially match those of the single input PWM signal. Blanking and deadband times may be introduced between the dual complementary PWM outputs, and the dual complementary PWM outputs may also be phase delayed.

Abstract: An embodiment is an integrated circuit. The integrated circuit comprises a clock generator and data transmission lines. The clock generator generates clock signals. At least some of the clock signals have a phase difference from an input clock signal input into the clock generator, and at least some of the clock signals have a different phase difference with respect to at least another of the clock signals. Each of the data transmission lines is triggered at least in part by at least one of the clock signals.

Abstract: There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.

Abstract: A circuit for serializing bits including a clock circuit and a serializer. The clock circuit may be configured to generate a plurality of clock signals from a received master clock signal. A plurality of bits may be transmitted to the serializer in response to a transition of a first clock signal. The serializer may comprise a system of latches and a rotary circuit. The system of latches may be configured to receive a first half of the plurality of bits in response to a first transition of a second clock signal and to receive a second half of the plurality of bits in response to a transition of a third clock signal. The rotary circuit may be configured to receive the plurality of bits from the system of latches and to output each bit at a particular time based on a plurality of rotary clock signals.

Abstract: This invention includes a clock tree to which clock signals are distributed, and a phase comparison circuit configured to detect the phase difference between a plurality of feedback clock signals upon receiving the plurality of feedback clock signals output from different branching points of the clock tree. The invention includes a feedback clock signal generation circuit configured to generate a variation-corrected feedback clock signal for correcting a manufacture variation in the semiconductor integrated circuit based on the phase difference detected by the phase comparison circuit. The invention includes a phase regulation circuit configured to delay the clock signal so as to reduce the phase difference between a reference clock signal and the variation-corrected feedback clock signal generated by the feedback clock signal generation circuit.

Abstract: A clock signal generating apparatus includes a first frequency generating circuit, a second frequency generating circuit, and an output circuit. The first frequency generating circuit is arranged to generate a first clock signal having a first oscillation frequency. The second frequency generating circuit is arranged to generate a second clock signal having a second oscillation frequency. The output circuit is arranged to receive the first and second clock signals. The output circuit is able to output one of the first and second clock signals as an output clock signal according to an oscillation frequency control setting provided by an external bounding pad included within the clock signal generating apparatus.

Abstract: Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.

Abstract: A processor frequency adjustment circuit for adjusting a frequency of a processor includes a voltage converting module, a first reference voltage generating module, a clock chip, a voltage comparing module. The voltage converting module converts a pulse voltage into a constant voltage. The first reference voltage generating module generates a first reference voltage. The voltage comparing module is connected with the voltage converting module, the first reference voltage generating module, and the clock chip to compare the constant voltage with the first reference voltage, and generates a first voltage level signal to a first terminal of the clock chip; the clock chip adjusts the frequency of the processor in response to obtaining the first voltage level signal.

Abstract: A clock generator includes a counter receiving a reference clock signal to generate a timing signal based on the reference clock signal, and a plurality of intermittent clock generating units each coupled to a storage unit thereof storing a bit strings data, each of the intermittent clock generating units receiving the reference clock signal and the timing signal. Each of the intermittent clock generating units masks a clock pulse of the reference clock signal based on the bit string data stored in the storage unit thereof to output an intermittent clock signal in response to the timing signal.

Abstract: The delay circuit, such as a clock circuit, of an integrated circuit operates with tolerance of variation in temperature. For example, the delay circuit has a temperature dependent current generator that has an adjustable temperature coefficient, such that a range of temperature coefficients is selectable at a particular current output. Also, the clock circuit of an integrated circuit operates with multiple versions of a current that controls a discharging rate and/or a charging rate between reference signals of timing circuitry.

Abstract: An enhanced complementary waveform generator (ECWG) generates two complementary pulse width modulation (PWM) outputs determined by rising and falling event sources. In a simple configuration of the ECWG, the rising and falling event sources are the same signal which is a PWM signal having the desired period and duty cycle. The ECWG converts this single PWM input into dual complementary PWM outputs. The frequency and duty cycle of the dual PWM outputs substantially match those of the single input PWM signal. Blanking and deadband times may be introduced between the dual complementary PWM outputs, and the dual complementary PWM outputs may also be phase delayed.

Abstract: A double-swing clock generator includes a first double-swing clock generation circuit and a second double-swing clock generation circuit. The first double-swing clock generation circuit is used for receiving a first voltage, a second voltage, a first clock, an inverse first clock, and a third voltage, and outputting a first double-swing clock. The second double-swing clock generation circuit is used for receiving a fourth voltage, the second voltage, the first clock, the inverse first clock, and the third voltage, and outputting a second double-swing clock.

Abstract: A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.

Abstract: Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. One or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.

Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.

Abstract: A clock signal generation circuit includes a first oscillation circuit for generating a first oscillation clock signal having a first frequency; a second oscillation circuit for generating a second oscillation clock signal having a second frequency; a frequency division circuit for generating a frequency division clock signal obtained through dividing the first oscillation clock signal; and a clock selection circuit for outputting the first oscillation clock signal as a high speed clock signal. The clock selection circuit is configured to output the second oscillation clock signal as the low speed clock signal when the second oscillation circuit transmits the second oscillation clock signal, and to output the frequency division clock signal as the low speed clock signal when the second oscillation circuit does not transmit the second oscillation clock signal.

Abstract: A power-supply-independent clock, with controlled THigh and TLow that permits both frequency and duty cycle to be set simultaneously and independently. Depending upon the implementation, the control values can be varied for frequency and duty cycle as determined by the user, or can be dependent upon temperature, power supply variations, or any other variable within the system, design or device that includes the clock.

Abstract: It is an object of the present invention to provide a semiconductor device that has a simple circuit structure, a small scale, and low power consumption, and can generate a desired clock signal. The semiconductor device has a clock generation circuit which generates a clock signal by dividing a modulated carrier wave, a divider circuit which generates a first divided signal by dividing a carrier wave, and a correction circuit which generates a second divided signal by further dividing the first divided signal, and has a function of performing correction for inverting the second divided signal in a period corresponding to a half period of the clock signal during modulation of the carrier wave and selecting whether the correction is performed or not.

Abstract: A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: A method to provide a low-power clock signal or a low-noise clock signal is described herein. It is determined whether a low-power mode or a low-noise mode is in use. A voltage reference input of a low-dropout voltage regulator (LDO) is switched to a low-power voltage reference for low-power mode and to a low-noise voltage reference for low-noise mode. The LDO provides a constant voltage output to a crystal oscillator. A clock signal is generated using the crystal oscillator. The clock signal is limited using a low-power limiter to generate a low-power output clock signal and/or is limited using a low-noise limiter to generate a low-noise clock signal. The low-power output clock signal or the low-noise output clock signal is selected using a mux.

Abstract: The invention relates to a pulse width modulator, more particularly to a cross-coupled pulse width modulator. A crossing input signal modulator according to the present invention comprises: a positive path block which includes a first integrator for performing the first-order integration of feedback signals in first input and output signals and then transmitting the first-order integrated signals to a second integrator, and a second integrator for performing the second-order integration of a signal from the first integrator and a second input signal and then transmitting the second-order integrated signals; and a negative path block which includes a third integrator for performing the first-order integration of feedback signals in the second input and output signals and integration of a signal from the third integrator and the first input signal and then transmitting the second-order integrated signals.

Abstract: A clock distribution network includes a plurality of clock drivers for outputting clock signals. At least one of the plurality of clock drivers has a driving capacity that is not equal to a driving capacity of at least another one of the plurality of clock drivers. The distribution network also includes a grid distribution network for distributing the clock signals output from the plurality of clock drivers.

Abstract: Various embodiments of a semiconductor integrated circuit. According to one exemplary embodiment, a semiconductor integrated circuit includes a multi-phase clock generator that is configured to generate a multi-phase internal clock; a first edge combining unit that is configured to generate a first output clock having a first frequency by combining rising edges of clocks included in the internal clock, and transmit the first output clock to a first port; and a second edge combining unit that is configured to generate a second output clock having a second frequency by combining rising edges of clocks included in the internal clock, and transmit the output clock to a second port.

Abstract: According to an aspect of the embodiment, a skew detecting unit includes at least one over delay path or racing path for detecting skew. A clock adjusting unit sets a set value of delay based on the skew detected by the skew detecting unit. A clock cell adjusts delay in a first clock according to the set value of the delay, and outputs the result as a second clock.

Abstract: Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.

Abstract: A semiconductor memory device can output data according to a predetermined data output timing, in spite of a high frequency of system clock, even when a delay locked loop is disabled. The semiconductor memory device includes a delay locked loop configured to perform a delay locking operation on an internal clock to output delay locked clock, and a data output control unit configured to determine a data output timing, according to whether the delay locked loop is enabled or disabled, in response to a read command.

Abstract: To provide a clock generator capable of suppressing a peak power, the circuit includes a counter receiving a reference clock signal to generate a timing signal based on the reference clock signal; and a plurality of intermittent clock generating units each coupled to a storage unit thereof storing a bit strings data, each of the intermittent clock generating units receiving the reference clock signal and the timing signal. Each of the intermittent clock generating units masks a clock pulse of the reference clock signal based on the bit string data stored in the storage unit thereof to output an intermittent clock signal in response to the timing signal.

Abstract: Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).

Abstract: An electric circuit (30) for generating a clock-sampling signal (CLK) for a sampling device (31) comprises a clock generator (1, 40, 50, 60) for generating a plurality of clock signals (21-24, 51-54, 61-64), a correlation device (L) for correlating a characteristic signal section (LE) of a digital signal (DS) with the plurality of clock signals (21, 22, 23, 24, 51-56, 61-64), and a selecting device (MX) for selecting one of the clock signals (21, 22, 23, 24, 51-55, 61-64) as the clock-sampling signal (CLK) for the sampling device (31) on the basis of the correlation by the correlation device (L). The clock signals (21-24, 51-54, 61-64) have the same cycle duration (T) and are phase-shifted with respect to each other. The sampling device (31) subsequently samples the digital signal (DS) with the clock-sampling signal (CLK).

Abstract: A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.

Abstract: A multilevel input interface device connected to a signal bus including one or more data lines that transmit an M-level signal and a clock line that transmits a transmission clock signal indicating the timings of reading level information for the M-level signal, includes: a threshold value generation unit that produces a plurality of voltage outputs as a plurality of variable comparison reference signals according to the level-varying supply voltage; a level detection unit that compares, in synchronization with the transmission clock signal, the M-value level signal with the variable comparison reference signals and generates a logic output corresponding to an instantaneous value of the M-level signal; and a logic circuit unit that converts the logic output to a data signal.

Abstract: The invention is related to an apparatus and a method for generating an output clock. The method comprises: receiving a transmitted signal comprising at least one data signal and at least one synchronized signal; producing a reference signal according to the synchronization signal; counting the first reference signal according to a free-run clock outputted by a free-run clock generator to produce a counter signal; and generating the output clock according to the counter signal and the free-run clock.

Abstract: There is provided a clock device including: a clock circuit to generate a plurality of clock signals, the clock circuit including a reset part for resetting generation of the clock signals; and a peripheral circuit operating based on the clock signals generated from the clock circuit, the peripheral circuit including: an error detection part for detecting an error in a process performed in the peripheral circuit by using the clock signals, and a determination part for determining whether to reset the clock circuit, based on information of the error detected by the error detection part.

Abstract: Timing setting data include an arbitrary combination of a set timing signal indicating a positive edge timing and a reset timing signal indicating a negative edge timing. A sort unit sorts n pieces of the timing setting data in accordance with timing orders indicated by each of the timing setting data. With reference to the sorted timing setting data an open processor detects continuation of the set timing signals or continuation of the reset timing signals, and invalidates one of the continuous set timing signals or one of the continuous reset timing signals. An edge assigning unit sequentially assigns the set/reset timing signals remaining without being invalidated to, among the m variable delay circuits for setting/resetting, the variable delay circuits for setting/resetting in the ascending order of the frequencies of use thereof by then.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.

Abstract: A semiconductor integrated circuit device includes a target circuit of a low power consumption mode having at least one flip-flop circuit to which a clock signal is supplied in a normal operation mode and in a low power consumption mode, and a logic circuit to which each output of the at least one flip-flop circuit is input, wherein each of the flip-flop circuits includes a selector that selects a normal data signal in the normal operation mode, selects an inverted output of the flip-flop circuit in the low power consumption mode, based on an operation-mode switching signal that designates switching between the normal operation mode and the low power consumption mode, and inputs the selected signal to a data input terminal of the flip-flop circuit.

Abstract: A timing generator reduces operation-dependent power consumption (AC component) and noises generated from a clock distribution circuit itself in distributing a clock, and further reduces a skew attributed to the clock distribution. A clock distribution circuit 20 for distributing the clock to timing generating sections 10-1 to 10-n has a clock main path 21 connected to a main path buffer 24 and a clock return path 26 connected to a return path buffer 27. A load capacity of the main path buffer 24 is equal to that of the return path buffer 27. Biases of the buffers are the same potential and are generated by a delay locked-loop circuit 30. A propagation delay time of the clock distribution circuit is controlled so as to be an integral multiple of a clock period.

Abstract: A method and apparatus for distributing clock signals throughout an integrated circuit is provided. An embodiment comprises a distribution die which contains either the clock signal distribution network by itself, or the clock signal distribution network in tandem with a clock signal generator. The distribution die is electrically connected through an interface technology, such as microbumps, to route the clock signals to the functional circuits on a separate functional die. Alternatively, the distribution die could be electrically connected to more than one die at a time, using vias through the distribution die to route the clock signals to the different die. This separate distribution die reduces the coupling between lines and also helps to prevent signal skew as the signal moves through the distribution network.

Abstract: Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.

Abstract: A clock buffer circuit of a semiconductor device is disclosed which receives an external clock signal and generates an internal clock signal with no duty distortion. The clock buffer circuit includes a first clock buffer for receiving and buffering a normal-phase clock signal, a second clock buffer for receiving and buffering a reverse-phase clock signal, and an internal clock generator for generating an internal clock signal in response to output signals from the first and second clock buffers.