Abstract: A daisy chained clock distribution scheme for distributing a clock signal from a central communications clock driver to the nodes of a massively parallel multi-processor computer or supercomputer. The daisy chained clocking scheme is implemented using point-to-point clock distribution of a differential clock signal to the communication nodes of a plurality of processors in a multicomputer system or to components connected to a common bus in a high speed microprocessor system. Differential signaling is employed wherein the differentiality is maintained including through silicon. In an alternate embodiment, the clock pulse is also regenerated in each node component.

Abstract: A clock distribution system minimizes clock skew in the distribution of clock signals to individual circuit board components in a highly synchronous, high speed computer system. The clock system includes an optical subsystem and an electrical subsystem. The optical subsystem utilizes multiple lasers and an n.times.n passive star coupler to introduce clock redundancy into the system. The lengths of the optical distribution fibers are controlled such that they are of equivalent optical path length. Once delivered to the logic assemblies, the optical clock signals are converted into equivalent electrical clock signals. The electrical subsystem then distributes the converted electrical clock signals to individual circuit board components over equalized fanout paths such that the skew as seen by the individual components is minimized. The system also compensates for skew introduced by the receiver and fanout electronics by tuning the length of the fiber.

Abstract: A duplexed clock switching apparatus of the present invention includes two oscillators constantly working for outputting clock signals, wherein a phase of the stand-by clock signal is kept synchronized to the phase of the clock signal selected from the output signal of the oscillator to be supplied to the apparatus. Each of the duplexed clock switching apparatus of the present invention includes a clock signal generator for generating clock signals of a predetermined frequency independently; a clock selector for receiving clock signals generated by all clock signal generators and selecting one of them; a phase synchronization circuit for synchronizing a phase of a clock signal generated by the clock signal generator to the phase of the selected clock signal; and a clock switching circuit for switching an outputted clock signal to the selected clock signal. With reference to the phase synchronization circuit, it is desirable to include a phase-locked-loop (PLL) circuit.

Abstract: A clock is phase shifted by an amount controlled by the value of a control signal by establishing at least several discrete delay times to be imposed on the clock. The control signal value controls selection of the imposed discrete delay time. An analog-to-digital converter of a phase locked loop responds to intelligence representing variable phase bits and the selected phase shifted clock to control the signal value. The selected replica is derived by at least several cascaded substantially equal time delay units. In one embodiment, a multiplexer responds to the clock, and the signal value, which is Gray coded, to control connections from one of the delay units to an output terminal. In another embodiment, the number of cascaded delay units interposed between the clock and an output terminal is controlled by the signal value.

Abstract: In a semiconductor device including a clock driver which provides clock signals, a plurality of electronic elements which are operable in timed relation to the clock signals, are provided a plurality of circumferentially-wired, lattice-shaped wiring blocks to which the electronic elements are connected and each of which has a center portion, and an interconnecting wiring pattern connected to the center portion. The interconnecting wiring pattern connects the clock driver with the center portion of each circumferentially-wired, lattice-shaped wiring block so that a distance between the clock driver and each center portion is substantially equal to one another in the center portions.

Abstract: In a synchronous integrated circuit including a plurality of functional blocks, the plurality of functional blocks are divided into a plurality of segments. Each of the segments is further divided into classes whose number is dependent upon the density of the functional blocks within each of the segments. A distribution of the functional blocks allocated to one class is homogeneous within the segment to which the class belongs, and one clock buffer is allocated at a substantial center position of the functional blocks within the class.

Abstract: Integrated circuits in which a phase difference between the external and internal clocks can be reduced by decreasing transistor stages from the input of an external clock to the output of an internal clock drive stages and also noise can be reduced which is generated when the clock driver drives at a high speed the internal clock having a heavy load and the noise can be prevented from propagation to other portions to avoid having a bad effect on other circuits, and further the internal clock having the same phase can be supplied to each part of the chip even at a high operating frequency by minimizing skew of the internal clock signal on the chip and still further a demand current can be reduced by eliminating a passing current of the internal clock signal driver.

Abstract: A semiconductor integrated circuit detecting a change in the internal propagation delay and self-compensating such a change. A combination of semiconductor integrated circuits can self-compensate a change in the total propagation delay of the circuit. There is provided a ring oscillator composed of dummy device elements separate from an actually-used logic circuit portion. The oscillating pulses of the ring oscillator are counted relative to a reference pulse signal. The semiconductor integrated circuit has a delay time compensation control circuit block which generates control data used to compensate the change in the propagation delay based on the difference between the first-counted value and a subsequently counted value. In a combination of semiconductor integrated circuits, the delay time compensation control circuit block may be provided for each channel. Alternatively, the delay time compensation control circuit block may be provided for common use by many channels.

Abstract: A low power clocking apparatus and method is used to reduce power consumption by an electronic system or an integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits. Each sub-circuit is configured to operate under control of a clock signal and further includes an apparatus for keeping or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, an integral arbiter circuit disables the clock signal to all the sub-circuits. The arbiter circuit continuously monitors the system bus. Upon detecting that the sub-circuits will require the clock signal, the arbiter will re-enable the clock signal to all of the sub-circuits.

Abstract: A method of adjusting clock skew for a computer system, wherein the computer system includes a clock generator for generating a clock signal, at least one logic module and a clock distribution network for carrying the clock signal from the clock generator to the logic modules, includes deskewing each of the logic modules and also deskewing the distribution network between the clock generator and the logic modules. Deskewing is performed by measuring a delay for the clock signal between a clock input and a test point on the logic module, comparing the measured delay to a desired delay, calculating an amount of adjustment needed to cause the measure delay to equal a desired delay and programming a skew compensator on the logic module with a calculator to mount adjustment.

Abstract: An information processing system comprises a sub-circuits, each performing a part of the processing of the information or data. The operation of the sub-circuits is synchronized by means of clock signals applied to clock inputs of the sub-circuits. The clock signals are derived from a system clock and are transferred to each sub-circuit via the sub-circuit or sub-circuits preceding that sub-circuit in the data processing chain. To avoid deterioration of the clock pulses while they are transferred between the sub-circuits, clock regeneration circuitry is arranged in the chain of sub-circuits. The clock regeneration circuitry is preferably integrated together with the data-processing sub-circuits.

Abstract: A digital pulse shaping and phase modulation network is used for reducing out-of-band spectral energy. This network is used in conjunction with a NCO (numerically controlled oscillator) which includes a linear phase input port. This circuit converts rectangular data pulses into a user programmed shape. The shape pulses are then modulated onto the carrier via the linear phase port. Depending on the preprogrammed pulse shape, the out-of-band spectral energy is significantly reduced.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Abstract: A trace having a closed periphery interconnect topology. The closed periphery interconnect topology can take the form of a substantially circular, oval, square, or polygon loop. An electrical signal driven onto the trace propagates in both clockwise and counter-clockwise directions around the loop. Series terminations can be implemented to optimize performance by providing better matching.

Abstract: A fully differential voltage controlled oscillator having a large common mode rejection ratio is disclosed with a first and a second phase detector disposed between the output of a differential comparator and the input of a differential triangle wave generator to insure 180 degree out of phase operation.

Abstract: A skew due to distribution of a clock inside a gate array is reduced. Phase comparators (14A), (14B) and (14C) are prepared in the peripheral portion of an internal circuit 71. The phase comparator (14C) is selected which is located nearest an element (77C) which receives an internal clock signal (65C) which is to be synchronized in terms of phase with an external clock signal (73). The selected phase comparator (14C) is connected to a charge pump circuit (16). Without forming a plurality of PLL circuits except for the phase comparators, the phase of any desired internal clock signal is synchronized with the phase of the external clock signal.

Abstract: A high frequency clock generator has a plurality of quartz crystals capable of providing various output frequencies coupled to multiple oscillator circuits. The output line from each oscillator circuit is coupled to one or more multiplexers so that the user can select one or more output frequencies at the same time. The multiple clock oscillator circuits and the multiplexer(s) are fabricated as an integrated circuit to minimize the degrading effects of weather and dust, to provide a fixed capacitive value and inverter bandwidth product, and to improve clock generator stability.