Abstract: Use of a variable voltage supply to clamp a diode for shunting signal glitches is described. Clamping the diode to a variable voltage supply enables forward-biasing of the diode, thereby preparing the diode for the glitch and effectively reducing the diode's turn-on time. The voltage of the variable voltage supply is determined by the size of the clamping diode used and the magnitude of the glitch it is designed to shunt. In one embodiment, the variable voltage supply is a temperature compensated voltage supply, such that as the temperature, and hence, the capacitance, of the diode changes, the value of the variable voltage supply also changes accordingly.

Abstract: An integrated circuit is disclosed in which a steering diode is coupled between an input bond pad and a ground bond pad. The steering diode is reverse biased when a voltage applied to the input bond pad exceeds the voltage at the ground bond pad. A circuit coupled between the input bond pad and the ground bond pad includes a transistor having a first electrode coupled the input bond pad and a second electrode coupled to the ground bond pad. There may be other circuit elements between the emitter and the ground bond pad. At least two series coupled diodes are coupled between the input bond pad and the ground bond pad. The at least two series coupled diodes provide ESD protection to the transistor and circuit coupled between the input bond pad and the ground bond pad.

Abstract: An I/O pad voltage protection circuit and method tracks a bias voltage of cascaded stages in order to avoid overvoltage stress in I/O transistors. An overshoot protection circuit controls overshoot current sinking to provide a clamp voltage equal to an I/O pad supply voltage, or other suitable reference voltage, during overshoot conditions, as a function of a reference voltage generated by a reference voltage generating circuit. An undershoot protection circuit includes a reference voltage generating circuit and controls undershoot current sinking to provide a clamp voltage approximately equal to an I/O pad ground voltage, or other suitable reference voltage, during undershoot conditions as a function of a reference voltage generated by the second reference voltage generating circuit.

Abstract: A compensation circuit for minimizing undesirable effects of parasitic components, such as a parasitic capacitance of a controlled electronic device (e.g., transistor) is coupled in parallel with the controlled electronic device in a manner that is effective to decrease the spurious AC signal-coupling of the parasitic component, such that the amplitude of the unwanted AC noise voltage across the load element is very significantly reduced, or effectively minimized. The parametric values of the transfer function of the electronic device in the by-pass compensation circuit are such as to attenuate the unwanted AC noise voltage across the load, by a factor that approximates the amplitude of the spurious signal, thereby effectively minimizing its unwanted contribution to the load voltage.

Abstract: A protection device includes a switching transistor (M11), connected between the gate of the output transistor (TS1) and ground, and a control circuit (CM), connected to the gate of the switching transistor (M11), which are capable of ensuring that the switching transistor (M11) is off when there is no electrostatic discharge at the drain of the output transistor (TS1) and capable of turning the switching transistor (M11) on when there is an electrostatic discharge at the drain of the output transistor (TS1).

Abstract: A noise canceling circuit that eliminates noise from an AC current of an AC power supply is provided with a changeover device that brings the noise canceling circuit into and out of conduction with a secondary side of a transformer in accordance with an on-off state of a switch. The noise canceling circuit includes a filter portion. The changeover device may be a relay or triac.

Abstract: A high-side, low-side driver that controls voltage from a voltage source to an inductive or resistive load includes a power transistor with a gate, a source and a drain. The driver is configured in a high-side configuration when the load is connected between the source and ground and the drain is connected to the voltage source and in a low-side configuration when the load is connected between the drain and the voltage source and the source is connected to ground. A gate drive circuit turns the power transistor on and off. The positive clamp circuit is connected to the drain and the voltage source. The positive clamp circuit provides a recirculation path for inductive energy that is stored in the inductive load when a loss of reverse battery condition occurs or when ground is lost.

Abstract: A semiconductor device is provided with a signal terminal, a high potential side power supply terminal, a low potential side power supply terminal, a first wiring connected to the high potential side power supply terminal, a second wiring connected to the low potential side power supply terminal, and an internal circuit to which power is supplied from the first and second wirings. Further the semiconductor device is provided with a first and a second resistance elements whose one end is connected to a first node, a first protection element having a first terminal connected to the first wiring and a second terminal connected to the other end of the first resistance element, a second protection element having a third terminal connected to the other end of the second resistance element and a fourth terminal connected to the second wiring, and a third protection element having a fifth terminal connected to the first wiring and a sixth terminal connected to the second wiring.

Abstract: The present invention provides a buffer for voltage ringing and overshooting suppression that improves the ESD protection. The buffer comprises a transistor and a resistance modulator. The resistance modulator is connected in series between an IC pad and a power node. The resistance modulator provides a first resistance during normal circuit operation, and provides a second resistance that is lower than the first resistance during an ESD event.

Abstract: A noise limiter of a semiconductor integrated circuit device includes a diode-connected N channel MOS transistor between a bus line and a line of a potential lower than the power supply potential by a threshold voltage, and a diode-connected P channel MOS transistor between a line of a potential higher than the ground potential by a threshold voltage and the bus line. The potential of the bus line is limited between the level of the power supply potential and the ground potential, so that the noise level of the bus line is reduced.

Abstract: A transient current producing method, a transient producing circuit, a related semiconductor integrated circuit and logical circuit are provided, which are capable of preventing a flow of a steady state current, consuming little power and switching at high speed. A transient current occurring at a time of switching of a CMOS circuit is amplified to a predetermined value. This amplification prevents the flow of the steady state current in the circuit. The transient current occurring at the time of switching of the CMOS circuit is converted to a transient voltage. The conversion of the transient current to the transient voltage having a predetermined value and the amplification of the transient current allow a simple configuration of the circuit. The transient current is a feedthrough current which flows from a terminal of a power supply to a ground at the time of switching of the CMOS circuit.

Abstract: A time domain filter circuit is provided with a switch for prohibiting inputting for the time between a change of an input signal and discharging a capacitor to 0, prior to a monostable multivibrator, so that a change of the next input signal is not accepted for a fixed time period since the input signal has been inverted. The time domain filter circuit detects a change of an input signal relative to an output signal, and detects a predetermined fixed time period based on the timing of the change by the monostable multivibrator using a charging time constant of the capacitor, so that an output signal level is changed so as to correspond to the input signal after the predetermined fixed time period elapses.

Abstract: The present invention relates to a circuit for protecting inputs and outputs on semiconductor devices. The protective circuit is particularly useful on high-speed inputs or outputs (such as in radio frequency applications where signal frequency is on the order of 100 MHz or greater and where it is necessary to minimize capacitive loading. Briefly, the present invention utilizes two FETs to shunt harmful electrostatic charges to a low impedance power bus and protect input and output circuit elements from damage or degradation. When a high voltage transient surge is detected, the drain-gate capacitance of one of the FETs couples the voltage to the gate electrode and biases one of the two transistors in the low impedance state so that the surge is absorbed without damage to the input or output circuit. Significantly, the capacitive loading of the protection circuit of the present invention is typically a fraction of a picoFarad and more particularly on the order of several hundred femtofarads.

Abstract: A semiconductor device including a current source having a first node coupled to a terminal, and a second node for extracting a current in response to an electrostatic discharge (ESD) on the terminal. The semiconductor device further including a transistor having a control electrode, a first current electrode coupled to the terminal, and a second current electrode coupled to the second node of the current source, and including a resistive element coupled to a first voltage reference node and the second node of the current source. The transistor of the semiconductor device is biased by detecting a negative voltage event (such as an ESD) at a first current electrode of the transistor and biasing a second current electrode of the transistor in response to detecting the negative voltage event, wherein the biasing of the second current electrode is for preventing a forward biasing of an p-n junction associated with the transistor.

Abstract: An output buffer circuit is provided, which is capable of obtaining a large drive power when the level of an input signal changes, while allowing a through current to flow in suppressed amounts. A first P-channel MOS transistor and a first N-channel MOS transistor are connected in series with a power supply. The pair of transistors are exclusively switched on and off by an input signal such that the first and second switching elements are not simultaneously on or off, to deliver an output signal corresponding to the input signal, from a common junction between the first and second switching elements. A second P-channel MOS transistor is connected in parallel with the first P-channel MOS transistor as an auxiliary transistor. A second N-channel MOS transistor is connected in parallel with the first N-channel MOS transistor as an auxiliary transistor.

Abstract: A driver circuit and a receiver circuit. The driver circuit is coupled to drive two complementary signals and the receiver is coupled to receive the two complementary signals. The receiver circuit generates a reference voltage from the two complementary signals.

Abstract: A method and devices for a current dump circuit that includes a first termination device, a second termination device, and a current dump device. The first termination device resides outside the die of an IC. One end of the first termination device is operatively connected to a first voltage regulator. Another end of the first termination is device operatively connected to a signal line of the IC. The second termination device resides on a die of the IC. One end of the second termination device is operatively connected to a second voltage regulator. Another end of the second termination device is operatively connected to the signal line of the IC. The current dump device provides a path to remove any current flow between the first voltage regulator and the second voltage regulator.

Abstract: A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.

Abstract: A semiconductor protection device is used to suppress a surge voltage to a preset value or less, the surge voltage being caused at each turn-OFF time of 50 Hz to 20 kHz of a main IGBT functioning as a switch of a power converting system. The semiconductor protection device includes a protection IGBT for forming a bypass connected in parallel with the main IGBT and an electric field sensing element connected in a reverse direction between the collector of the main IGBT and the gate of the protection IGBT. When the surge voltage exceeds a preset value which is a breakdown voltage of the electric field sensing element, the protection IGBT is turned ON so as to cause a current generated by energy of the surge voltage to be bypassed.

Abstract: A method and apparatus is disclosed for reducing electrical noise from noise spikes in an electrical information signal. The invention can provide protection of a data storage system from soft errors rate due to noise spikes appearing in the signal from the input transducer. A cancellation signal for the low frequency component (i.e. in the system bandwidth) of the noise signal is generated. The cancellation signal is derived from a frequency band that appears in the noise spike, but does not appear in the system bandwidth for the information signal. The cancellation signal is generated in the preferred embodiment by a cancellation signal generator comprising a high pass filter and a mixer. The mixer generates a cancellation signal by processing the high frequency portion using a waveform above the normal high frequency cutoff to reconstitute the low frequency component of the noise spike in the normal frequency band.

Abstract: A noise suppression circuit for suppressing noises above and below reference voltages is provided. The noise suppression circuit for suppressing noises includes a clamping transistor, a feedback circuit, and a presetting means for presetting an internal latch of the noise suppression circuit to a predetermined state. The predetermined state is a high state or a low state depending upon the type of noise suppression accomplished by the circuit. After the occurrence of a noise coupling event, the clamping transistor restores the state of a data input of a circuit to which the suppression circuit is providing protection. The feedback circuit then turns off the clamping transistor after a predetermined amount of time.

Abstract: To a first node at a boosted potential, a control circuit is connected for controlling a potential of the first node so that the potential of the first node does not exceed a predetermined potential, wherein the control circuit has a capacitor connected between the first node and a second node, a first switching transistor having a source-drain current path inserted between the second node and the ground node and a gate to which a control signal is input, and a second switching transistor having a source-drain current path inserted between the first node and the ground node, and a gate connected to the second node.

Abstract: An output buffer circuit is provided, which decreases a delay time of change of a digital output signal with respect to change of a digital input signal and which is capable of higher-speed switching operation. This output buffer circuit is comprised of a pair of a first p-channel MOSFET and a first n-channel MOSFET located in an output stage through which an output signal is derived; a first clamp circuit for clamping a gate voltage of the first p-channel MOSFET at a first clamp level for a first specific period, thereby increasing a rising rate of the output signal; and a second clamp circuit for clamping a gate voltage of the first n-channel MOSFET at a second clamp level for a second specific period, thereby increasing a falling rate of the output signal. A first resistor is connected to the first clamp circuit for suppressing a current flowing through the first clamp circuit. A second resistor is connected to the second clamp circuit for suppressing a current flowing through the second clamp circuit.

Abstract: An output circuit has an n-channel constant voltage circuit and p-channel constant voltage circuit. The output circuit includes a p-channel MOS transistor and an n-channel MOS transistor at the output stage thereof. The n-channel constant voltage circuit controls the drive of the p-channel MOS transistor, and causes current flowing through the p-channel MOS transistor so that current path through the p-channel MOS transistor to be constant or substantially constant. The p-channel constant voltage circuit controls the drive of the n-channel MOS transistor, and causes current flowing through the n-channel MOS transistor so that current path through the n-channel MOS transistor to be constant or substantially constant.

Abstract: A switching device includes a phase controlling circuit (801) which shifts and outputs a phase of a command signal, and a plurality of switching units (110) connected in parallel between a power supply (101) and a load (102).

Abstract: A semiconductor integrated circuit device has an output circuit formed in a CMOS structure and composed of a P-channel MOS transistor that has its gate connected to an input terminal, has its source connected to a power source line, and has its drain connected to an output terminal and an N-channel MOS transistor that has its gate connected to the input terminal, has its source connected to ground, and has its drain connected to the output terminal. A first protection diode is formed in parallel with the source-drain channel of the P-channel MOS transistor. A first NPN-type transistor is so formed that its base is connected to ground and its collector-emitter path is connected in parallel with the source-drain channel of the P-channel MOS transistor. A second protection diode is formed in parallel with the source-drain channel of the N-channel MOS transistor. A thyristor circuit is provided in parallel with the source-drain channel of the N-channel MOS transistor.

Abstract: A write driver circuit for selectively controlling a direction of write current flow through a magnetic head having an inductive coil includes a source of first and second write currents. A forward drive switch directly sinks the first write current and sinks the second write current through the coil in a first direction. A reverse drive switch directly sinks the second write current and sinks the first write current through the coil in a second direction opposite the first direction. A control circuit operates the forward and reverse drive switches so that write current flows through the coil in a selected direction. An overshoot reduction circuit may be provided to reduce write current overshoot through the coil. An active subcircuit generates a compensation signal based on a voltage across the head exceeding a predetermined threshold. The first and second write currents are adjusted in response to the active subcircuit based on the compensation signal.

Abstract: After an output signal is inverted by an inverter circuit, the resultant signal is differentiated by a differentiating circuit. The connecting states of selectors are changed so that only when the signal level of the differentiated output exceeds a predetermined threshold value, the output signal is sent through a resistor. After the output signal is buffered by a buffering circuit, the resultant signal is differentiated by a differentiating circuit. The connecting states of selectors are changed so that only when the signal level of the differentiated output exceeds a predetermined threshold value, the output signal is sent through a resistor.

Abstract: A drive circuit for driving a power device is provided which includes a first ground that provides a current path of drive current that flows when the power device is driven, and a second ground that is used by a protection circuit that monitors an operating state of the power device.

Abstract: The invention relates to circuitry for protecting n-channel load driving devices from reverse voltage conditions and for inhibiting the flow of destructive currents through such devices under reverse voltage conditions. According to one embodiment of the invention, a circuit is provided for protecting an n-channel high side load driving device from negative battery and negative transient operating conditions.

Abstract: A method and circuit for reducing the leading edge spike in a current sense signal. The current sense signal is a measure of the current through a switched power device controlled by a switching regulator controller. The slew rate of the current sense signal is limited to prevent the slew rate from exceeding a predetermined maximum. The limited slew rate signal is provided to the switching regulator controller. A transconductance amplifier may be used to limit the slew rate of the current sense signal. A capacitor at the output of the transconductance amplifier contributes to controlling the maximum slew rate of the amplifier. The capacitor is charged by the current output of the amplifier to provide a voltage signal for use in place of the original current sense signal. A switch may be provided for selecting between the slew rate limited current sense signal and the original current sense signal.

Abstract: A noise suppression circuit for suppressing noises above and below reference voltages is disclosed. The noise suppression circuit for suppressing noises includes a means for generating a power-on-reset signal, a clamping transistor, and a feedback circuit. The means for generating a power-on-reset signal presets an internal latch of the noise suppression circuit to a predetermined state, such as a logical high state. The clamping transistor restores the state of a data input of a circuit to which the noise suppression circuit is providing protection, after the occurrence of a noise coupling event. The feedback circuit then turns off the clamping transistor after a predetermined amount of time.

Abstract: A digitally controlled signal attenuator circuit which allows an incoming DC-clamped signal to be selectively attenuated using a set of digital control signals while maintaining its DC clamping. Multiple stages of such a circuit can be cascaded to provide for multiple forms of signal attenuation without affecting the clamping. Preferred forms of the attenuator circuit use pass transistors and transmission gates as switches for selectively altering the resistance values of resistive circuits connected in shunt to and in series with the signal being attenuated. In the case of where the subject signal is a variable DC signal such a brightness control voltage, such circuit configurations also allow the output signal voltage range to include values which are more negative than the DC clamp voltage as well as more positive.

Abstract: To provide a pull-up circuit and a pull-down circuit having the same withstand voltage performance to other neighboring circuit elements without needing special layout consideration, a pull-up circuit of the invention having an nMOS pull-up transistor (N1) connected between a first node (A2) and a pull-up node (OU) comprises a pMOS transistor (P2), a drain of said pMOS transistor (P2) connected to the first node (A2), a source and a substrate of said pMOS transistor (P2) connected to a positive power supply (Vcc), and a gate of said pMOS transistor (P2) controlled with a pull-up signal; and a pull-down circuit of the invention having a pMOS transistor (P1) connected between a first node (B2) and a pull-down node (OD) comprises an nMOS transistor (N2), a drain of said nMOS transistor (N2) connected to the first node (B2), a source and a substrate of said nMOS transistor (N2) connected to a negative power supply (GND), and a gate of said nMOS transistor (N2) controlled with a pull-down signal.

Abstract: A device for the protection of an integrated circuit input/output pin against electrostatic discharges includes a first diode between a positive power supply line and an internal connection node for connection to the pin, and a second diode between the internal node and a second negative or zero supply line. The device also includes a protection transistor series-connected between the positive power supply line and the first diode, and a stack of N diodes, where N is equal to one or more, series-connected between the control electrode of the protection transistor and the first diode.

Abstract: An overshoot and damping control circuit for high speed L-R-C drivers. By properly configuring four transistors in conjunction with a high speed driver, negative feedback can be utilized to generate a spike of current to correct for overshoot which results when driving an inductive load with high speed signals. This same configuration also provides the additional benefit of providing a signal which dampens the ringing which results from driving an inductive load with a high speed signal.

Abstract: The invention relates to a predistortion circuit for an analog signal in a video communication network. In one embodiment the circuit according to the invention includes a primary branch connecting an input to an output, a delay circuit for delaying a signal in the primary branch, a first coupler/shunting device which samples a fraction of the input signal, a secondary branch connected to the shunting output of the coupler/shunting device, the secondary branch including a second-harmonic generator, and a second coupler/shunting device which receives the output signal from the secondary branch and adds it to the signal at the output of the primary branch. The circuit according to the invention makes possible a symmetrical filter with improved performance characteristics and low manufacturing cost.

Abstract: The fine protection circuit arrangement is to reduce the remaining residual impulses on gas tube charge eliminators. This is to be achieved by means of a cascading of a gas tube charge eliminator or a .lambda./4 shorting stub with a fine protection circuit. The fine protection circuit connected to the gas tube circuit eliminator or .lambda./4 shorting stub reduces the relatively high residual voltage at the output of the gas tube charge eliminator or .lambda./4 shorting stub to a minimal value.

Abstract: A high-frequency radio signal receiving apparatus for digital communication includes a receiving antenna for receiving a high-frequency radio wave, a frequency converter for converting a signal supplied from the receiving antenna through a wide-band bandpass filter into a signal of an intermediate frequency band, an impulsive noise detecting unit for detecting impulsive noise on the basis of a signal outputted from the frequency converter. The apparatus further includes an impulsive noise correcting unit for correcting the signal outputted from the frequency converter in dependence on a signal outputted from the impulsive noise detecting unit, and a demodulating unit for demodulating a signal outputted from the impulsive noise correcting unit and supplied by way of a narrow-band bandpass filter.

Abstract: An output circuit is constructed such that a load capacitor is not charged by an external power supply but by a first charge storage element within a semiconductor chip that is charged before the load capacitor. The charge stored in the load capacitor is released not directly to the ground but to a second charge storage element within the semiconductor chip and discharged before discharging of the load capacitor.

Abstract: A clamping circuit useful in reducing ringing on a transmission line is described. The clamping circuit includes a pair of transistors coupled between the transmission line and opposite terminals of a voltage source. An enable circuit monitors the transmission line for transitions, both low-to-high and high-to-low, and enables the transistors to be biased such that they connect the transmission line to the voltage source in the presence of ringing.

Abstract: An input circuit is made up of an external signal input portion which inputs an external signal, a voltage level converting circuit which has an input terminal for inputting a signal from the external signal input circuit and which has an output terminal for outputng the signal to the internal circuit after a voltage level was converted, a first power supply terminal which has a first potential for driving the voltage level converting circuit, a second power supply terminal which has a second potential for driving the voltage level converting circuit, and a noise control portion which couples to the input terminal of the voltage level converting circuit, which controls a noise from the first power supply terminal and/or the second power supply terminal, and which has a first capacitor. Accordingly, the input circuit could be applied the stable signal to the internal circuit.

Abstract: The present invention relates to a method for setup of a signal in multicarrier modulation, including clipping the signal, in amplitude, with respect to a threshold value, and of reinjecting, with a delay and on the signal to be set up, a clipping noise redistributed, at least partly, outside the useful slip of the signal in multicarrier modulation.

Abstract: A jamming signal cancellation method and apparatus for removing an undesired in-band CW jamming signal from a desired spread spectrum signal. The jamming cancellation apparatus includes a limiter, a summer, and a feedback loop. The feedback loop includes the summer, a harmonic filter, a mixer, a loop/filter amplifier, and an adjustable gain control (AGC). The limiter limits the waveform of the input signal and issues a limited signal to the AGC and the mixer. The AGC controls the amplitude of the limited signal and passes a controlled amplitude signal to the summer. The summer takes a difference between the input signal and the controlled amplitude signal and passes a difference signal to the filter. The filter filters the harmonics that were created by the limiter and passes an output signal to the mixer. The mixer multiplies the filtered signal by the limited signal to provide an error signal that is proportional to the amplitude of the fundamental frequency in the difference signal.

Abstract: An apparatus for protecting an integrated circuit against damage from electrostatic discharges (ESD) includes a single ESD bus that is connected to multiple input pads through a respective diode. The ESD bus is isolated from the positive power supply bus V.sub.DD. The ESD bus is coupled to the negative power supply bus V.sub.SS by a FET-triggered SCR circuit. ESD charge on an input pad forward biases the respective diode and charges the ESD bus. When the voltage of the ESD bus reaches a predetermined threshold voltage, the FET breaks down, and triggers the SCR circuit to shunt the charge on the ESD bus to V.sub.SS. The threshold voltage is selected such that, in normal operation, voltages higher than V.sub.DD may be applied to the input pad without input leakage current.

Abstract: A decoupling circuit for a mixed voltage integrated circuit chip reduces noise on a high voltage power supply while reducing noise coupling to a low voltage power supply and allowing a thin oxide capacitor dielectric (preferably formed by a process common to the gate insulators of field effect transistors on the chip) to be used for good area-efficiency of the filter capacitors. A series connection of capacitors to ground is used in combination with a resistive charging connection connected to a low voltage power supply to prevent a voltage exceeding a breakdown voltage of the thin oxide being applied to the capacitors. The resistive charging connection in combination with a capacitive voltage divider action of the series connected capacitances provides improved noise attenuation coupled to the low voltage supply.

Abstract: When energizing a shunt capacitor in a circuit that includes an ac power supply and a switch, the shunt capacitor is initially precharged to a predetermined voltage with a direct current voltage. Thereafter, the switch is closed at an instant of voltage peak of the ac power supply with the same polarity as the predetermined voltage.

Abstract: An apparatus and method for suppressing the effects of thermal asperities in readback signals of a hard disc drive are disclosed. A suppression circuit is provided having a clamping path that establishes an electrical short between a readback signal path transmitting the readback signal and a reference line for the readback signal in order to remove substantially all of the energy associated with the thermal asperity from the readback signal. The suppression circuit further includes a compensation path operably coupled between the readback signal path and the reference line to subsequently provide baseline compensation for the readback signal by introducing a non-zero impedance between the readback signal path and the reference line.

Abstract: A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.

Abstract: A circuit structure which avoids a latchup effect. An N-well is formed in a P-type substrate. An N-type contact is formed in the N-well. A PMOS is located on the N-well. A gate of the PMOS connects to an input terminal and a source region of the PMOS connects to a voltage source. A first NMOS and a second NMOS are located on the P-type substrate. A gate of the first NMOS connects to the input terminal, a source region of the first NMOS connects to a ground terminal, and a drain region of the first NMOS connects to an output terminal and a drain region of the PMOS. A gate of the second NMOS connects to the output terminal, a source region of the second NMOS connects to a voltage source, and a drain region of the second NMOS connects to the N-type contact.