Abstract: An active RC integrator filter with finite operational amplifier bandwidth can be compensated by biasing the operational amplifier input stage such that its transconductance becomes a function of the resistance. Thereafter, by inserting another resistance of the same material in series with the integrating capacitor, a zero results in the overall transfer function of the filter according to the present invention. In this manner, the passband peaking of the active RC integrator filter resulting from the integrator phase shift can be avoided.

Abstract: A charge integration circuit incorporates first and second capacitors, and first and second reference voltage supplies. A first switch controls integration of charge in the first capacitor and selectively resets the first capacitor to the first reference voltage. A second switch selectively resets the second capacitor to the first reference voltage. A current mirror coupled to the capacitors effects discharge of the second capacitor by a quantity of charge equivalent to the charge integrated on the first capacitor so as to effectively transfer charge therebetween at the end of an integration period.

Abstract: An electrical network creates a differential voltage signal and comprises a plurality of first impedance elements of substantially equal values which are connected to form an impedance bridge. The impedance of at least one of the first impedance elements changes in response to at least one selected external condition to which the first impedance elements are exposed. The network also comprises a second impedance element which has two nodes. The second impedance element is connected at these nodes between a first pair of the first impedance elements. The differential voltages are measured between these nodes and between another node or nodes with magnitudes and signs being dependent upon the change in the impedance of the first impedance elements.

Abstract: To decode an attenuated multi-level signal (42) in a receive interface (120) of communication apparatus, first (134) and second (150) diode pumps co-operate with a biasing chain to ensure that threshold reference levels used by respective positive (52) and negative (54) data comparators are dynamically adjusted to a level dependent upon the attenuated multi-level signal (42) applied to the diode pumps. Particularly, a voltage divider (138-144) acts dynamically to bias differential inputs to the respective positive (52) and negative (54) data comparators, with a ratio between a biasing chain of resistors (138-144) and a common input resistor 128 determining the threshold reference levels used to assign logical levels for the reconstruction of symbols encoded within the multi-level signal (42).

Abstract: Integrated circuitry for selectively introducing capacitance and for controlling the transconductance transfer function of one or more amplifiers includes concatenated differential amplifiers with one or more pairs of switchable capacitive components differentially connected across outputs of the differential amplifiers to facilitate operation over a wide range of operating frequencies under control of external signals.

Abstract: An integrator circuit is disclosed which overcomes problems in the art described above. In accordance with the present invention, an integrator circuit includes a differential input transconductance stage which converts an input differential signal to a differential current at first and second internal nodes. These two internal nodes are buffered from an integrating capacitor by two pass transistors, the conductance of which is automatically adjusted in response to the voltage at the two nodes. In this manner, the first and second nodes act as nearly ideal current sources. Thus, the integrating capacitor sees a nearly infinite impedance, thereby allowing the integrator circuit to achieve a large RC time constant while employing relatively small internal resistances. Further, the integrator circuit is fully differential and includes a floating capacitor having equal leakages on each of its plates. Being responsive only to differential signals, the integrator circuit thus ignores common mode leakages.

Abstract: A measurement amplifier has an integrator circuit (2) and a reference current source (33) which supplies a reference current to the input of the integrator when the voltage set at the output of the integrator (2) exceeds or falls below a reference voltage. In addition, a differentiator, for example, is provided which receives the output voltage of the integrator (2) and supplies an output signal which is proportional to the variation in time of the output voltage of the integrator. The output voltage of the differentiator is proportional to the input current to be measured by the measurement amplifier. The measurement amplifier allows very weak input currents to be rapidly and accurately detected.

Abstract: A non-linear integrator of a closed loop integration system selectively modifies the gain of the closed loop integration system in order to avoid system saturation while still experiencing high gain in a desired linear portion of the system. A non-linear integrator structure and method allow the gain of the closed loop integration system to be selectively modified in order to avoid saturation while experiencing high gain. The non-linear integrator includes an amplifier, a current source element which generates a bias input signal, a bias circuit which provides the bias input signal to the amplifier and allows the bias input signal to be selectively modified, a storage element coupled to the amplifier, and a gain element, coupled to the storage element, which produces an output signal determined by voltage on the storage element. A voltage input signal and a bias input signal are supplied to the amplifier which generates an amplifier output signal.

Abstract: An integrator is disclosed that is capable of outputting the same integration result with respect to the same bit pattern even if there are fluctuations in the integrating period, semiconductor device process, or the power supply voltage. The disclosed integrator includes: (1) a first integrator having a first amplifier, for integrating a reference voltage during an integrating period, (2) a second integrator having a second amplifier, for integrating an input signal during the integrating period, and (3) control means for outputting a signal regulating a gain of the first amplifier to the first amplifier so that an output of the first integrator varies in correspondence with the integrating period, and for regulating a gain of the second amplifier by means of the signal.

Abstract: A wide band, high-order, programmable video filter is implemented using transimpedance-based active integrators. An input voltage which may for instance represent a composite video signal is converted to a current in a linear manner using resistors and provided to a current amplifier at low impedance virtual ground nodes. The current is multiplied by a gain factor .beta..sub.R within the current amplifier and supplied to integrating capacitors connected in a feedback configuration around a high input impedance differential amplifier to establish an integrated differential voltage output. The transimpedance-based active integrators may be interconnected to realize wide-band, high-order video filters suitable for use in accordance with CCIR 601 standards. Input voltage swings are not restricted by a transistor's limited range of linear operation or voltage swing limitations of internal nodes but rather may allowed to swing as long as the bias currents sustain input current excursions.

Abstract: The present invention is a charge amplifier that directly produces a low impedance voltage output proportional to the charge at its input. The invention consists of an operational amplifier, an input capacitor, a feedback capacitor and a feedback resistor in a parallel configuration. The change amplifier of the present invention can be said to be a differentiator followed by an integrator so that the "noisy" differentiation process precedes the integration and, thus the integration produces less signal degradation.

Abstract: An SC-integrator comprises an amplifier connected to a circuit network, which includes an integrating capacitor and a storage capacitor. The storage capacitor is connected via a first switch to the output of the amplifier and via a second switch directly to one side of a switching circuit capacitor, which is also connected by means of third and fourth switches to ground and the inverting input of the amplifier, respectively. The other side of the switching circuit capacitor is connected by means of a fifth switch to an input voltage Vin, via a sixth switch to ground, and by means of a seventh switch to a reference voltage Vref. The SC integrator uses a storage capacitor of relatively low capacitance value, since the storage capacitor is connected in parallel with the switching circuit capacitor when effecting a reversal of the voltage polarity across the integrating capacitor.

Abstract: A filter circuit that consumes very little electric power. The active filter is a linear inverter constructed by 1) an inverting amplifying portion composed of an odd number of MOS inverters serially connected, 2) a grounded capacitance connected between an output of the inverting amplifying portion and ground, 3) a balancing resistance having a pair of resistances for connecting an output of one of the MOS inverters, other than the last MOS inverter, to the supply voltage and the ground, respectively, and 4) a feedback impedance for connecting the output and input of the inverting amplifying portion. A coupling capacitance is connected to the input of the linear inverter and a plurality of filter circuits are connected to an input of the coupling capacitance.

Abstract: A programmable analog array (10) comprises an array (11) of cells, each cell including analog circuitry (12), a switch control circuit (18), and a digital storage element (16). The switch control circuit (18) receives a clock signal and sequentially configures the circuits within the analog circuitry (12) to realize different circuit functions in accordance with configuration data stored in different digital memory units (17A-17D) within digital storage element (16). During a time interval, the analog signals generated by the analog circuitry (12) before that time interval are stored in an analog storage element (14), which is constructed from a portion of a capacitor network (54) in the analog circuitry (12) and is partitioned into a set of analog memory units (56A-56D). Each analog memory unit (56A-56D) stores the analog signal for a corresponding phase of the clock signal.

Abstract: A numerical voltage controlled oscillator comprising an integrator for generating an estimated sine waveform and an estimated cosine waveform from a variable control signal; a normalizer, connected to the integrator, for generating a normalization factor from the estimated sine waveform and the estimated cosine waveform; and a multiplier, connected to the normalizer, for multiplying the normalization factor with the estimated sine waveform and the estimated cosine waveform. The multiplication of the estimated sine waveform and the normalization factor produces the sine waveform and the multiplication of the estimated cosine waveform and the normalization factor produces the cosine waveform. The frequency and phase of the sine and cosine waveforms vary with changes in amplitude of the variable control signal.

Abstract: A sign bit integrator and method for generating a signal to correct an offset in a signal processing system that can distort the output from the system. A charge pulse is generated when the sign of a input signal is sampled in order to provide an offset correction signal with a polarity opposite that of offsets in the system. The charge pulse is provided to a pair of transistors whose size ratio sets the magnitude of the charge pulse. The polarity of the charge pulse is set responsive to a sign bit in the input signal. An integrator capacitor provides the offset correction signal to the signal processing system. A third transistor may be switchably substituted for one of the pair of transistors to change the ratio of sizes and thus change the magnitude of the charge pulse to thereby change the speed with which the offset correction is made. The sign bit integrator and method may be used to correct distortion in a voice signal in a telephone system.

Abstract: The invention relates to a method and an arrangement for controlling a loop filter of a digital phase lock, the loop filter filtering a difference signal, which comes from a phase comparator at a predetermined bandwidth and is proportional to a phase error. To reduce oscillation in the adjusting method and to eliminate the errors caused by noise, the loop filter is adjusted non-linearly on the basis of the difference signal from the phase comparator in such a manner that the bandwidth of the loop filter changes.

Abstract: An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied to one of the differential inputs through a first input network, and a signal indicative of the DC offset component of the signal to be integrated is applied to the other of the differential inputs through a second input network. A pair of electronic switches in the first and second input networks define an integrating period when they are closed. The first and second input networks are substantially symmetrically constructed of matched components so that error components introduced by the electronic switches appear symmetrically in both input circuits and, hence, are nullified by the common mode rejection of the integrating opamp. The signal indicative of the DC offset component is provided by a sample and hold circuit actuated as the integrating period begins.

Abstract: There is disclosed a rectangular filter which has a simple configuration and is capable of producing an improved rectangular wave. An input step wave is differentiated by a differentiator circuit and amplified by a first amplifier. The output from the amplifier is inverted by an inverting amplifier having a gain of -1. The output from the first amplifier is integrated by an integrator circuit having a time constant equal to the time constant of the differentiator circuit. The output from the inverting amplifier and the output from the integrator circuit are summed up by an adding circuit. The input signal is faithfully reproduced at the output of the adding circuit. After a given time passes since the input signal has been applied, the capacitor of the integrator circuit is shorted out. In this way, a rectangular wave is obtained. There is also disclosed a filter amplifier comprising this rectangular filter and a gated integrator for integrating the output from the rectangular filter for a predetermined time.

Abstract: Circuits embodying the invention include means for sensing certain characteristics (e.g. speed of response and conductivity) of the transistors formed on an integrated circuit (IC) and for using the sensed results to control the operation and structure of a circuit formed on the IC. An output driver circuit embodying the invention includes numerous pull-up transistors connected in parallel between a high power supply line and an output terminal and numerous pull-down transistors connected in parallel between the output terminal and the low power supply line. The number of transistors which are turned-on at any one time is selectively controlled as a function of the characteristics (e.g. conductivity and speed of response) of the transistors of the circuit. The higher the speed of response or the conductivity of the transistors, the fewer the number of pull-up or pull-down transistors which are turned-on.

Abstract: A timing generator, which is simple in construction and is capable of high speed operation with excellent linearity and low power consumption, wherein a delayed timing signal is generated by delaying an input timing signal. The generator comprises a switch having one end thereof connected to a first voltage source and which is controlled by the input timing signal, a current source provided between the other end of the switch and a second voltage source; a charge injection circuit generating a voltage signal which is turned ON and OFF in accordance with the input timing signal; a capacitor provided between the output end of the charge injection circuit and the other end of the switch; and a comparator generating a delayed timing signal by comparing the voltage at the other end of the switch with a desired voltage, wherein the delay time of the delayed timing signal is adjusted by controlling either the voltage outputted from the charge injection circuit or the current from the current source.

Abstract: A double direct injection dual band focal plane array input circuit provides simultaneous and separate integration of the current from two sensors which share a common node. The sensors are constant voltage and variable current sensors such as HgCdTe infrared photodiodes. The sensor voltage biases are independently adjustable. Multiple integration of the signal from one sensor may be performed within one integration time of the other sensor. The circuit is used in staring infrared dual band focal plane arrays and may be used process information from more than two sensors.

Abstract: An integrating circuit includes first and second amplifiers for use during a zero-integrate mode and a X10 mode, respectively. The first amplifier is a low gain amplifier to ensure stability, whereas the second amplifier is a high gain amplifier to improve accuracy. During the zero-integrate mode, switches couple an integrator input lead to the first amplifier output lead and decouple it from the second amplifier output lead. During the X10 mode, the switches decouple the integrator input lead from the first amplifier output lead and couple it to the second amplifier output lead.

Abstract: An accumulator-based phase locked loop reduces phase noise by shifting the energy of the phase noise to higher frequencies. A second accumulator is inserted between a first accumulator and a pulse generator to integrate a phase error from the first accumulator referenced to a clock signal. The output of the pulse generator is an approximation frequency signal that is compared with a comparable frequency signal derived from a reference signal to produce an error signal to control the frequency of the clock signal.

Abstract: An integrator includes a capacitor and a bootstrap circuit for detecting any leaking charge from the capacitor and replacing it. The integrator also includes a charge injection circuit for adjusting the charge applied to the capacitor in response to a digital control input to the charge injection circuit. The bootstrap circuit has two transistors to sense leaking charge, and two further transistors forming a differential pair. The bootstrap circuit uses positive feedback and unity gain to replenish the lost charge.

Abstract: A voltage regulation circuit that includes a sample and hold circuit for sampling an input voltage and for holding a reference voltage generated in response to the input voltage. The sample and hold circuit includes a capacitor that holds the reference voltage. The voltage regulation circuit also includes a regulator circuit coupled to the capacitor of the sample and hold circuit. The regulator circuit outputs an output voltage using the reference voltage supplied by the capacitor. The voltage regulation circuit may be used to provide a high precision programming voltage for programming memory cells having two or more analog states.

Abstract: A transconductance-capacitor filter system (8) is provided which includes a transconductance-capacitor filter 10 having a first node (NODE 1) and a second node (NODE 2). A current sensor circuit 12 is coupled to the first node (NODE 1) and the second node (NODE 2).

Abstract: A two-wire constant current powered transducer (10) for detecting, integrating and transmitting an acceleration signal (50) received from a piezoelectric crystal (12). The crystal is operatively coupled to rotating machinery (M) such that rotating anomalies correlative of wear or potential failure can be detected early enough for preventative maintenance. The transducer (10) includes two stages (30, 40). The first stage (30) is an integrator which integrates the acceleration to velocity. The second stage (40) is a gain stage. The gain stage operates with a PNP transistor emitter follower to control the output DC bias level and route the integrated acceleration signal back to the control system.

Abstract: A ramp generator has an integrator, which provides a ramp output, and a counter, which counts a clock signal during the rise period. The counter and clock are arranged so that when the actual rise time is equal to the desired rise time, the counter overflows and returns to zero. If the rise time is too slow, the counter will contain a count at the end of the rise period. A register is connected to receive this count and an adder adds the contents of the register to the contents of the adder repeatedly each time a clock pulse is generated. The adder has an output connected to the input of the integrator and, each time the adder overflows, supplies a correction pulse to the integrator so that its rise rate is increased.

Abstract: An active filter circuit has differential transistors having first conductivity type bipolar transistors and load transistors having second conductivity type bipolar transistors. A connecting node between the differential transistors and the load transistors is driven by a middle electric potential. Voltage dependent characteristics of earth capacitance including parasitic capacitances parasitic to the differential transistors and the load transistors can be kept constant by offsetting the voltage dependent characteristics of the parasitic capacitances. It is thereby possible to make the active filter circuit small in size and the consumed electric power reduced.

Abstract: A switched current bilinear integrator comprising interconnected current memory cells (M1, M2) in which, during a first phase of a clock cycle, an input current is fed to the inputs of the current memory cells and during a second phase of the clock cycle an inverted version (A1) of the input current is fed to the inputs of the current memory cells. The output of the integrator is obtained by combining the output (optionally scaled) of the first current memory cell (M1) with an inverted (A2) version of the output (optionally scaled) of the second memory cell (M2). A lossy integrator may be formed by feeding back to the input a scaled version of the current stored in the second current memory cell and an inverted, scaled version of the current stored in the first memoy cell.

Abstract: A complete type integrator is disclosed which is designed such that the time-constant thereof can be controlled; wide input and output dynamic ranges can be achieved; operation with low power supply voltage is possible; and no offset voltage is generated. More specifically, the integrator comprises an amplifier circuit having a combination of a first and a second differential amplifier circuit (A1, A2) and connected to the input side of an integrator circuit; and an offset eliminating circuit connected to that portion of the amplifier circuit where the input signal (9) is applied. The offset eliminating circuit comprises a combination of a first, a second and a third current-mirror circuit (B1, B2, B3).

Abstract: An estimating circuit for application in estimating or deriving the value V.sub.rms.sup.2 or V.sub.peak.sup.2, of a line voltage V.sub.AC provides fast response time and a substantially ripple free value for these signals by the utilization of a controlled harmonic oscillator whose output precisely tracks the input voltage waveform. Two out of phase (by .pi./2) sine wave signals are derived from the input sine wave and these two out of phase signals are squared and summed to derive or estimate the desired square of the sine waveform signal at a fast response time while substantially excluding ripple of the estimated out of phase sine waves. An estimating circuit, described herein, comprises two integrator circuits series connected into a substantially closed loop. The output of the second integrator circuit is fed back to the input of the first integrator circuit. The output of each individual integrator circuit is a voltage sine wave separated in phase from the output of the other integrator by .pi.

Abstract: A MOSFET wherein cell includes a MOSFET transistor having a gate connected to an input voltage signal for integration, a source grounded through a high resistance, and a drain connected to a power source. An output capacitor is connected to the source of the MOSFET transistor to complete the MOSFET cell.

Abstract: A reference period generating circuit is provided which generates a pulse having a width corresponding/to a reference period T.sub.1 in response to the input of a trigger pulse. A switch, a first resistor and a second resistor are connected in series between the first and second reference voltages. The node between the first and second resistors is connected to an inverting terminal of an operational amplifier. A non-inverting terminal thereof is connected to a third reference voltage. A clamping circuit is provided to clamp the output voltage of the operational amplifier to a predetermined value. By comparing the output voltage with a predetermined reference value by means of a comparator, a pulse representative of a timing period is generated.

Abstract: A signal integration circuit having a first MOSFET including a drain connected to a power source and a gate connected to a plural number of the first capacitances in parallel; and an input means connected to each capacitance; in which each input means comprises; the second MOSFET whose source is connected to the first capacitance through a resistance, which receives an input pulse signal, and whose gate is grounded through the second capacitance, and the third MOSFET whose source is connected to a gate of the second MOSFET, whose drain is connected to a power source, and whose gate receives a pulse signal for setting weight; a gate of the first MOSFET receiving a reference saw-tooth signal, a source of the first MOSFET grounded through the third capacitance, and an output pulse signal being output from this source of said first MOSFET.

Abstract: The circuit is adapted for integration of pulse signals of the shape U(t)=U.sub.0 exp(-t/.tau.), wherein the time constant .tau. can be determined in advance by a calibration measurement, in particular signals from a scintillation detector. The purpose is to treat pile-up phenomena, without measuring the integration time, wherein the measured integral is corrupted because the time distance between two pulses becomes smaller than the integration time for the first pulse. The circuit comprises an integrator (4, 5, 6, R, C) for the pulse signal and a summator (3, R.sub.1 -R.sub.3) for forming a weighted sum of the pulse signal (on 1, 2) and the integrated signal (from 4, 5), the weight of the pulse signal and the weight of the integrated signal having such a relation to each other that the result signal (on 8) is proportional to the sum of the time integral of the pulse signal and .tau. times the pulse signal.

Abstract: To set the drop-out detection level constant in the drop-out detecting circuit used for a magnetic recording apparatus, without regulating the output level of a magnetic recording head and the gain of a preamplifier, the detecting circuit comprises an envelope detection section for detecting the envelope of a reproduced signal; a voltage division section for dividing the output signal voltage of the envelope detection section; and a comparator for comparing the output signal of the voltage division section with the reproduced signal to detect a drop-out of the reproduced signal. Therefore, it is possible to reduce the number of parts and the number of adjustment process to reduce the manufacturing cost thereof. Further, to detect the drop-out portion throughout as defective tape locations, irrespective of the length of the drop-out portion, the detecting circuit further comprises a drop-out start detection section, a drop-out end detection section, and an OR gate.

Abstract: An integrating circuit is formed in the present invention, of which the active element is a pair of bipolar transistors (T5/T6) or a CMOS transistor (T8) which with the aid of switches (s81 to s88) controls the storing of a sample charge from the signal voltage (Us) in a sampling capacitor (Ci) and the discharging of the sample into an integrating capacitor (Co). The circuit only consumes current while charges are being transferred.

Abstract: An integration circuit includes a differential amplifier constituted by at least two bipolar transistors serving as amplifying elements, a capacitor connected, as a load, across the collection electrodes of the differential amplifier, and a field-effect transistor having source and drain electrodes connected between the emitter electrodes of the two bipolar transistors. A control voltage is applied to the gate electrode of the field-effect transistor. By changing the resistance value between the source and drain electrodes of the field-effect transistor using a gate voltage, the transconductance of the differential amplifier is changed over a wide range. As a result, the time constant of the integration circuit is changed, such that if the integration circuit is used for an active filter, for example, the cut-off frequency can be changed by changing the time constant of the integration circuit.

Abstract: A circuit having a first integrator 46 and a sensor 20 for sensing a difference between an output voltage of the first integrator and a trip voltage provides a signal indicative of whether the output voltage is greater than the trip voltage. Resetting circuitry 40, 42 and 44 is coupled to the sensor 20 for softly bringing the output voltage lower than the trip voltage when the signal from the sensor 20 indicates that the output voltage is greater than the trip voltage.