Abstract: The invention provides an electronic device for reducing simultaneous switching noise (SSN). The electronic device includes: a driver, driving an external device according to an input signal, and including: an input end, receiving the input signal; a positive output end, coupled to an external capacitor of the external device; and a negative output end, coupled to a variable capacitor; and a loading calibration circuit, generating an adjusting signal to adjust a first capacitance of the variable capacitor so as to make the first capacitance approximately equal to a second capacitance of the external capacitor.

Abstract: A first constant voltage is supplied to a variable capacitance in a switched capacitor, and the variable capacitance is effectively charged to the first constant voltage in each cycle of a sampling clock. A current generated by charging the calibration resistance is averaged, and a resultant current is compared against a current generated by applying a second constant voltage to a resistance. The capacitance value of the variable capacitance is adjusted in accordance with a result of the comparison. Thus the variable capacitance is calibrated so as to have a target value.

Abstract: A method is intended to make it possible to drive a PTC electrical load element with a switching unit with the highest possible operational reliability. For this purpose, the electric current is switched off if a predetermined current threshold value is exceeded, the magnitude of the current threshold value being determined from the operating parameters of the load element.

Abstract: A temperature compensation circuit for generating a temperature compensating reference voltage (VREF) may include a Bandgap reference circuit configured to generate a Bandgap reference voltage (VBGR) that is substantially temperature independent and a proportional-to-absolute-temperature reference voltage (VPTAT) that varies substantially in proportion to absolute temperature. The circuit may also include an operational amplifier that is connected to the Bandgap reference circuit and that has an output on which VREF is based. The circuit may also include a feedback circuit that is connected to the operational amplifier and to the Bandgap reference circuit and that is configured so as to cause VREF to be substantially equal to VPTAT times a constant k1, minus VBGR times a constant k2.

Abstract: This document discusses, among other things, a compensation circuit configured to modulate a control voltage of a switch over a range of ambient temperatures during a conduction state of the switch to maintain a specified resistance between first and second nodes of the switch. The compensation circuit can include a temperature-insensitive resistor configured to provide a sense current, a current mirror configured to provide a mirror current using the sense current, and a temperature-sensitive resistor configured to provide the control voltage using the mirror current.

Abstract: A control circuit for a transistor arrangement comprises a monitoring arrangement (60) for monitoring the current flow and voltage across the transistor arrangement (50) and means (62) for determining if the current and voltage values define an operating point which falls within a stable operating region. The stable operating region comprises a region having a boundary (30) which comprises an electro-thermal instability line.

Abstract: The number of power-gating transistors on an integrated circuit used for power reduction in a sleep mode is controlled during a wake state to adjust the current flow and hence voltage drop across the power-gating transistors as a function of aging of these transistors and/or a function of temperature of the integrated circuit. In this way, the supply voltage to the integrated circuit may be better tailored to minimize current leakage when the integrated circuit is young or operating at low temperatures.

Abstract: General speaking, a resistor of high resistivity has a negative-temperature-coefficient and a resistor of low resistivity has a positive-temperature-coefficient. Utilizing this characteristic, an appropriate proportion between the above resistors can be found to make a combined resistor with an approximate zero-temperature-coefficient. The combined resistor can be used to design a circuit for generating voltage and current with approximate zero-temperature-coefficients.

Abstract: A power supply circuit includes a PWM controller, which is capable of providing pulse signals to the CPU, a temperature feedback circuit coupled to the PWM controller, and a temperature sensor. The temperature sensor is coupled to the temperature feedback circuit, the temperature sensor is located adjacent the CPU, and capable of detects a temperature of the CPU. The PWM controller is capable of adjusting the pulse signals to maintain the pulse signals stably when the temperature sensor detects the temperature of the CPU rising.

Abstract: A gate drive device which can suppress the fluctuation of an internal power source voltage and output voltage, while reducing the number of parts by omitting a bypass capacitor connected in parallel with a semiconductor integrated circuit, is provided. The gate drive device drives the gate of an active element with a large input capacity, such as an IGBT or MOSFET, and includes a semiconductor integrated circuit. The semiconductor integrated circuit has an internal power source based on an external power source, such as a battery. The semiconductor integrated circuit incorporates a voltage drop suppressing circuit, configured so that, if an input external power source voltage momentarily drops below a minimum operating voltage, a drop of an internal power source voltage below the minimum operating voltage, and a sharp drop in a voltage output to the gate, are prevented by the voltage drop suppressing circuit.

Abstract: A solid state relay has independent charge pumps isolating each gate of a full bridge to achieve faster and proper gate turn on. The low side MOSFETs of the bridge are the current sensing device reducing loss and allowing a device controlled by the relay to achieve peak performance. Dynamic braking is achieved by the two low side MOSFETs being fully conducted and applying a load across the DC motor. Addition of a microprocessor to the device provides undervoltage sensing, current vs time readings, motor stall sensing, and motor temperature sensing. Motor temperature is detected by checking impedance of the motor at microsecond pulses to see if the motor is getting hot.

Abstract: This document discusses, among other things, a compensation circuit configured to modulate a control voltage of a switch over a range of ambient temperatures during a conduction state of the switch to maintain a specified resistance between first and second nodes of the switch. The compensation circuit can include a temperature-insensitive resistor configured to provide a sense current, a current mirror configured to provide a mirror current using the sense current, and a temperature-sensitive resistor configured to provide the control voltage using the mirror current.

Abstract: A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.

Abstract: A method is intended to make it possible to drive a PTC electrical load element with a switching unit with the highest possible operational reliability. For this purpose, the electric current is switched off if a predetermined current threshold value is exceeded, the magnitude of the current threshold value being determined from the operating parameters of the load element.

Abstract: An embodiment method for power switch temperature control comprises monitoring a power transistor for a delta-temperature fault, and monitoring the power transistor for an over-temperature fault. If a delta-temperature fault is detected, then the power transistor is commanded to turn off. If an over-temperature fault is detected, then the power transistor is commanded to turn off, and delta-temperature hysteresis cycling is disabled.

Abstract: A device includes a first circuit and an adjustment circuit. The adjustment circuit performs an adjustment on impedance of the first circuit. The adjustment circuit discontinues the adjustment on impedance while the first circuit is in an activated state.

Abstract: An embodiment of a logarithmic circuit may include a logging transistor, and a multi-tanh circuit arranged to provide temperature compensation to the logging transistor, where the multi-tanh circuit comprises a multiplicity of multi-tanh cells. In another embodiment, a logarithmic circuit may include a logging transistor, and a multi-tanh circuit arranged to provide temperature compensation to the logging transistor, where the multi-tanh circuit includes a first set of outputs arranged to provide an output signal and a second set of one or more outputs that are diverted.

Abstract: A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.

Abstract: An enhanced transistor gate drive is disclosed in which a pair of Kelvin sense leads measure the voltage potential across at the gate and source of the transistor. The difference in the voltage potential of the Kelvin sense lead from the gate and the Kelvin sense lead of the source is provided to a voltage controlled current source, which compares the output of the voltage differentiator to an oscillating voltage input. Changes to the voltage difference between the Kelvin sense connectors will result in more or less voltage being applied at the gate of the transistor, thereby parasitic inductance in the transistor from causing the device to switch on and off.

Abstract: An embodiment of a control circuit is proposed for turning on a power switching device, the switching device turning on in response to a control signal exceeding a threshold value. The control circuit includes pre-charging means for providing the control signal at a pre-charging value not reaching the threshold value, and soft turn-on means for gradually increasing the control signal from the pre-charging value to a turn-on value exceeding the threshold value; the pre-charging means includes means for sensing an indication of the threshold value, and means for setting the pre-charging value according to the sensed threshold value.

Abstract: The present invention relates to a device for connecting and breaking DC power comprising an input DC power (DC-In) arranged to be connected to a circuit board (1) and to the collector port (C) of an insulated gate bipolar transistor (IGBT). The insulated gate bipolar transistor (IGBT) is arranged to be connected to the circuit board (1). An output DC power (DC-Out) is arranged to be connected to the emitter port (E) of the insulated gate bipolar transistor (IGBT) and the circuit board (1). The circuit board (1) is arranged to be connected to the gate port (G) of the insulated gate bipolar transistor (IGBT) and the circuit board (1) is designed to monitor predetermined conditions of the input and output DC power (DC-In, DC-Out).

Abstract: A circuit configuration having a detection unit designed to generate an output signal that is representative of a load current of a transistor switch, depending on an input signal that is representative of the load current of the transistor switch. The detection unit includes a temperature compensation unit that is designed to take into account the temperature of the transistor switch. The detection unit further includes a delay unit that is designed to delay the detection of the input signal until a prescribed switch-on time period, relative to a switch-on procedure of the transistor switch, has passed. The detection unit is designed in an application-specific integrated circuit.

Abstract: The transistor arrangement contains a first and a second field effect transistor comprising a first and a second source drain connection and a control connection for applying a first or a second signal. The two field effect transistors are of the same conductive type. The transistor arrangement is configured in such a manner that the first signal can be applied in an alternating manner to the control connection of the first field effect transistor and the second signal can be applied in a simultaneous manner to the control connection of the second field effect transistor, and/or the second signal can be applied to the control connection of the first field effect transistor and the first signal can be applied simultaneously to the control connection of the second field effect transistor.

Abstract: AFE circuitry handles both voltage and current input signals. In one embodiment, both a voltage path and a current path are provided from the input. Switching circuitry selects one of the paths. A switch also turns on or off a current-to-voltage conversion circuit used to convert a current input into a voltage. In one embodiment, noise is significantly reduced by using a dedicated ground pin or terminal for the negative reference of a differential circuit. This applies the same external board noise, which is on the input signal, to the negative reference, so the noise is canceled in the differential signal. In one embodiment, temperature compensation is provided via an IPTAT circuit which is used to shift the voltage up in order to balance the decrease in DC voltage with increasing temperature.

Abstract: A Voltage-to-Current converter includes a current mirror having first and second poles, a first transistor coupled between the first pole of the current mirror and a low voltage through a first resistor, a second transistor coupled between the second pole of the current mirror and a low voltage through a second resistor wherein the second resistor is substantially identical with the first resistor, and wherein the output current is dependent on resistance of the first resistor, the input voltage signal applied to the gate of the first transistor, and a reference voltage signal applied to the gate of the second resistor.

Abstract: A programmable gain amplifier comprises a current source that generates a first current based on a first transfer function. A voltage amplifier receives an input voltage signal and generates an output voltage signal based on a gain A, wherein the gain A is based on a control current and a second transfer function. A compensation module generates the control current based on the first current and a mapping function, wherein the mapping function is based on the first transfer function and the second transfer function to reduce the effect of an independent variable on an overall transfer function that relates the first current to the gain A.

Abstract: Embodiments of the invention are related to a power transistor and a method for controlling a power transistor. In one embodiment a power transistor comprises a power semiconductor body with a plurality of power transistor cells each having a control electrode and a current path. The power transistor furthermore comprises a temperature sensor formed by at least one transistor cell in the power semiconductor body whose control electrode is coupled to one electrode of the current path forming a reversed biased pn-junction.

Abstract: A compensated control circuit includes a combination module that generates a control variable based on n signals and a process module that generates an output signal based on an input signal and the control variable wherein n is a positive integer.

Abstract: Provided is a pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.

Abstract: A semiconductor memory device controls an over driving period according to fluctuation of a supply voltage VDD. The semiconductor memory device includes a bit line sense amplifier, a sense amplifying driver and an over driving controller. The over driving controller includes a delay unit for delaying an input signal, a supply voltage detector for detecting the level of the supply voltage VDD, a delaying controller for controlling a delay time of the delay unit in response to an output of the supply voltage detector, and an output unit for outputting a over driving pulse, whose width is controlled according to the fluctuation of the supply voltage VDD, by performing a logic operation to the input signal and an output of the delay unit.

Abstract: An internal voltage generator for use in a semiconductor memory device includes a first voltage detection unit, a second voltage detection unit, a detection signal generation unit, and an internal voltage generation unit. The first voltage detection unit detects a voltage level of an internal voltage changing linearly depending on a temperature variation to output a first detection signal. The second voltage detection unit detects the voltage level having a constant value without concerning the temperature variation to output a second detection signal. The detection signal output unit combines the first and the second detection signal to generate a combined detection signal for detecting the voltage level linearly varying according to the temperature variation in a first range of temperature and detecting the voltage level having the constant value in a second range of temperature.

Abstract: A high voltage power supply apparatus and a method of correcting current output from the high voltage power supply apparatus. The high voltage power supply apparatus includes a switching unit; a transformer; a pulse width modulation signal processing unit, which receives a pulse width modulation signal changed for environmental conditions, converts the received pulse width modulation signal into a direct current (DC) voltage, and outputs the converted signal as a reference signal; a drive control signal generating unit, which compares an output current signal output from the transformer with the reference signal, and outputs a drive control signal to drive the switching unit; and an output current detecting unit, which detects the output current signal. Accordingly, the magnitude of current output from the high voltage power supply apparatus can vary according to environmental conditions and the current can be uniformly output without an output error.

Abstract: A gate-off-voltage-generating circuit that can enhance display quality at low temperatures, a driving device, and a liquid crystal display having the same are provided. The driving device includes a boost converter to receive and boost a first input voltage, and output a driving voltage and a pulse signal; a gate-on voltage generator to receive the driving voltage and output a gate-on voltage; and a gate-off voltage generator including a first temperature-compensation unit to receive the driving voltage and output a first temperature-dependent variable voltage, the level of which varies according to the ambient temperature, a first voltage follower to receive and transfer the first temperature-dependent variable voltage, and a first charge-pumping unit to shift the first temperature-dependent variable voltage by the amplitude of the pulse signal and output a gate-off voltage.

Abstract: An interface circuit includes an input terminal, a controlled current sink, a current measurement arrangement, and a logic circuit. The input terminal is configured to receive an input signal. The controlled current sink is operably coupled to the input terminal, and is operable to controllably take up a current from the input terminal according to a transmission signal. The current measurement arrangement is configured to generate a current measurement signal based on the current taken up by the current sink. The logic circuit is operably coupled to receive the current measurement signal and the input signal, and is configured to generate a signal depending on the input signal.

Abstract: A transistor arrangement with temperature compensation is disclosed with a transistor having at least one adjustable geometric parameter. A temperature measuring means outputs a temperature-dependent signal, depending on which a control unit drives the geometric parameter of the transistor in such a way that the electrical characteristic quantities thereof are temperature-independent. The adjustable geometric parameter may be the channel width of the transistor.

Abstract: An amplitude setting circuit for setting an amplitude level of its output signal corresponding to an input signal. By setting a current flowing through a first diode-connected transistor (Q5) and a current flowing through a first drive transistor (Q1) to be in a predetermined relationship, variation with temperature in potential at a first connection point of the first drive transistor (Q1) and a first conductivity-type transistor (M1) is removed, and by setting a current flowing through a second diode-connected transistor (Q6) and a current flowing through a second drive transistor (Q4) to be in a predetermined relationship, variation with temperature in potential at a second connection point of a second conductivity-type transistor (M2) and the second drive transistor (Q4) is removed.

Abstract: A driving device using a CMOS inverter performs a stable operation by using a compensating circuit to compensate variation widths when the process condition or external environment is changed. The driving device comprises a power regulating unit for regulating a driving voltage level depending on characteristics of a MOS transistor and a delay unit comprising a plurality of CMOS inverters driven by the driving voltage regulated by the power regulating unit.

Abstract: According to one embodiment a semiconductor device is provided. The device includes a first compensator to generate a first compensated signal and a first limiter to control operation of the first compensator. Furthermore, a second compensator to generate a second compensated signal and a second limiter to control operation of the second compensator is provided. An output device is adapted to receive the first compensated signal and the second compensated signal to drive an output.

Abstract: A slew-rate controlled output driver for use in a semiconductor device includes a PVT variation detection unit having a delay line for receiving a reference clock in order to detect a delay amount variation of the delay line determined according to process, voltage and temperature (PVT) variation; a selection signal generation unit for generating a driving selection signal which corresponds to a detection signal generated by the PVT variation detection unit; and an output driving unit having a plurality of driver units controlled by an output data and the driving selection signal for driving an output terminal with a driving strength which corresponds to the PVT variation.

Abstract: A capacitor charging circuit comprises, power transfer circuitry, power switching control circuitry and voltage measurement circuitry. The power transfer circuitry transfers power from a power source to a capacitor. The power switching control circuitry controls the switching that causes power to be delivered to the power transfer circuitry. The voltage measurement circuitry indirectly measures the output voltage to determine when to stop charging the capacitor.

Abstract: A temperature compensation circuit consists of a thermo sensitive resistance, a fixed resistance, a logic buffer, and a logic inverter, without incorporating any operational amplifier. A resistance value of the thermo sensitive resistance is changed by temperature change. The fixed resistance has a small temperature changes that is smaller than that of the thermo sensitive resistance. Both the fixed resistance and the thermo sensitive resistance are connected electrically to an output terminal of the temperature compensation circuit. The logic buffer sets the other terminal of the fixed resistance to a first voltage that is one of a voltage level of a power source and a ground level. The logic inverter sets the other terminal of the thermo sensitive resistance to a second voltage that is reversed to the first voltage.

Abstract: One exemplary device has a plurality of leads with termination impedances, and a standard impedance. Among the termination impedances are master impedances arranged to be calibrated by comparison with the standard impedance and slave impedances arranged to be calibrated in accordance with an associated master impedance.

Abstract: A thermal management system is described which may be implemented on a semiconductor die. The system may include a thermal sensor thermally coupled to the die to sense the temperature of the die and generate an output representing the sensed temperature, and an adjustable compensation circuit coupled to the thermal sensor to compensate the thermal sensor output. The adjustable compensation circuit may be applied to the thermal sensor or to a threshold.

Abstract: A temperature compensation circuit for effectively compensating the difference of a switching timing due to temperature change of a switching element included in a logic circuit is provided. The temperature compensation circuit includes a temperature detecting section for detecting a value corresponding to the temperature of the switching element, and a correction section for correcting the voltage of a logic signal inputted from a previous circuit to the logic circuit in order to reduce the difference of the switching timing due to the temperature change of the switching element based on the value corresponding to the temperature.

Abstract: An accurate temperature monitoring system that uses a precision current control circuit to apply accurately ratioed currents to a semiconductor device, which may be a bipolar junction transistor (BJT), used for sensing temperature. A change in base-emitter voltage (?VBE) proportional to the temperature of the BJT may be captured and provided to an ADC, which may generate a numeric value corresponding to that temperature. The precision current control circuit may be configured to generate a reference current, capture the base current of the BJT, generate a combined current equivalent to a sum total of the base current and a multiple of the reference current, and provide the combined current to the emitter of the BJT. In response to this combined current, the collector current of the BJT will be equivalent to the multiple of the reference current. The ratios of the various collector currents conducted by the BJT may thus be accurately controlled, leading to more accurate temperature measurements.

Abstract: A reference voltage generator uses a conventional forward junction voltage generating device and a conventional thermal generator to generate a thermal voltage. The forward junction voltage and the thermal voltages have respective thermal sensitivities that act oppositely to each other so that, when the forward junction voltage is combined with the thermal voltage to produce a reference voltage, the reference voltage is substantially insensitive to temperature. The forward junction voltage and the thermal voltage are combined to produce the reference voltage in a manner that avoids generating any voltage having a magnitude that is greater than the magnitude of the sum of the forward voltage and the thermal voltage.

Abstract: An on-chip temperature detection device includes: a bipolar type power transistor; a mirror transistor in which a collector current, which is proportional to a collector current of the power transistor, flows; a current detection section that detects the collector current of the mirror transistor; a voltage detection section that detects a voltage between a base and an emitter of the power transistor; and a calculation section that calculates a chip temperature of the power transistor, based upon the collector current of the mirror transistor detected by the current detection section, and upon the voltage between the base and the emitter of the power transistor detected by the voltage detection section.

Abstract: A precise downhole clock that compensates for drift includes a prescaler configured to receive electrical pulses from an oscillator. The prescaler is configured to output a series of clock pulses. The prescaler outputs each clock pulse after counting a preloaded number of electrical pulses from the oscillator. The prescaler is operably connected to a compensator module for adjusting the number loaded into the prescaler. By adjusting the number that is loaded into the prescaler, the timing may be advanced or retarded to more accurately synchronize the clock pulses with a reference time source. The compensator module is controlled by a counter-based trigger module configured to trigger the compensator module to load a value into the prescaler. Finally, a time-base logic module is configured to calculate the drift of the downhole clock by comparing the time of the downhole clock with a reference time source.

Abstract: An on-DRAM termination resistance control circuit is capable of controlling resistance of an IC termination and minimizing area for the resistance control circuit by using a simplified circuit scheme. The on-DRAM termination resistance control circuit includes a push-up resistance adjusting unit, a pull-down resistance adjusting unit and resistance adjustment control unit. The push-up resistance adjusting unit adjusts resistances of a first and a second inner resistors based on an external reference resistor. The pull-down resistance adjusting unit adjusts a resistance of a third resistor based on the second inner resistor that is adjusted by adjustment of the push-up resistance control unit. The resistance adjustment control unit controls to alternatively repeat the operation of the push-up resistance adjusting unit and the pull-down resistance adjusting unit for a predetermined number of adjustment times.

Abstract: Delays through components of a programmable device are determined transparently to the user through the use of mimic paths. For each delay path to be measured, at least one mimic path is created that has similar components and characteristics to the actual path to be measured. A signal fed through this mimic path will experience similar delay to a signal passing through the actual path, which can be affected by temperature and voltage variations during operation. A swept clock signal can be passed to a register latching the mimic signal data, producing output that can be fed to lead/lag logic to determine a current value of the delay through the mimic path. This delay can be compared to a previous delay determination to approximate an adjustment to be made to a sampling clock used to latch the actual data into the appropriate register at the middle of the latching window.