Abstract: A frequency-responsive integrated circuit (IC) for determining when the frequency of a clock pulse input signal is below a predetermined threshold level, the IC including a capacitor charged up at a nearly constant rate by a current source. If the capacitor voltage reaches one-third of the DC power voltage, and input pulses are received, the capacitor is discharged to start another charge-up cycle. If no input pulses were received, the capacitor continues to charge up until its voltage reaches two-thirds of the DC power voltage, at which point an output signal is produced indicating that the input frequency is below the predetermined threshold level.

Abstract: A compensation circuit 10 is disclosed herein. The circuit includes a control circuit 14 including a delay element 18 with a delay sensitive to at least one parameter which causes variations in delay and also comprises a compensated driver circuit 16. The compensated driver circuit 16 has a control input B coupled to the control circuit 14 and a signal input C coupled to an input circuit 12. The delay of an output signal OUT of the compensated driver circuit 16 is controlled in part by the control circuit 14 which modifies the delay of the output signal OUT in response to variation of the parameter. Other systems and methods and numerous variations are also disclosed.

Abstract: A circuit for controlled discharge of energy stored in an inductive load, comprising an active semiconductor device (T) connected serially with the inductive load (L) between first and second terminals of a voltage supply source and having a control terminal for connection to a driver circuit (C), and a control circuit (R1, R2, COMP) connected between the inductive load and said control terminal. The control circuit comprises a voltage divider (R1, R2) connected between the inductive load (L) and the first terminal of the voltage supply source, and a comparator (COMP) having first and second input terminals respectively connected to the voltage divider and to a voltage reference and an output terminal which is coupled to the control terminal of the active element (T).

Abstract: A method and circuit for tuning an equivalent resistor in a filter so that the filter is insensitive to temperature changes in which an amplifier output is connected to a common gate of plural MOSFETs for providing equivalent resistances, and in which one input to the amplifier is connected to a reference resistor and the other input to the amplifier is connected to an equivalent resistor that includes one of the plural MOSFETs. An input current to the reference resistor and to the equivalent resistor's MOSFET is inversely proportional to the MOSFET's conduction parameter, k (i.e., .mu.C.sub.ox /2), so that both the inputs to the amplifier vary to change the amplifier output voltage to the common gate. The amplifier output changes render the filter insensitive to temperature changes.

Abstract: A driver for providing binary signals from a data system to a transmission line is disclosed. A first n-channel transistor has its drain coupled to the transmission line and its source coupled to ground. The channel of the first n-channel transistor has a width that is greater than its length. A first inverter stage conducts current from a first voltage supply to the gate of the first n-channel transistor in order to switch the first n-channel transistor into a conductive state and conducts current from the gate of the first n-channel transistor to ground in order to switch the first n-channel transistor into a non-conductive state. A discharge circuit provides a discharge path from the gate of the first n-channel transistor to ground during a discharge time period and then removes the discharge path at the end of the discharge time period.

Abstract: Circuits embodying the invention include means for sensing certain characteristics (e.g. speed of response and conductivity) of the transistors formed on an integrated circuit (IC) and for using the sensed results to control the operation and structure of a circuit formed on the IC. An output driver circuit embodying the invention includes numerous pull-up transistors connected in parallel between a high power supply line and an output terminal and numerous pull-down transistors connected in parallel between the output terminal and the low power supply line. The number of transistors which are turned-on at any one time is selectively controlled as a function of the characteristics (e.g. conductivity and speed of response) of the transistors of the circuit. The higher the speed of response or the conductivity of the transistors, the fewer the number of pull-up or pull-down transistors which are turned-on.

Abstract: A storage charge reduction circuit for reducing the storage charge of a first bipolar transistor. The circuit includes a second field effect transistor connectable between the base of the first bipolar transistor and ground for conducting a compensation current from the base of the first bipolar transistor to ground. A third bipolar transistor is connected in series with a first resistor for conducting a first current from a first voltage supply through the first resistor to ground. Current mirror circuitry sets the gate-source voltage of the second field effect transistor so that the compensation current is proportional to the first current. The first current and the compensation current increase when temperature increases. In a preferred embodiment, the storage charge reduction circuit is used in a transmission line driver. The driver includes an output bipolar transistor connectable between the transmission line and ground for conducting current from the transmission line to ground.

Abstract: An automotive sensor arrangement including an automotive sensor coupled via first and second wires to signal sensor evaluation means, a signal conditioning circuit comprising a first gate means connected to provide a bias operating voltage signal on said first wire to the sensor, a second gate means of similar construction to the first gate means and mounted in the same environment and first gate means, the second gate means being coupled to the second wire of the leas means for receive the voltage signal bears a predetermined relationship to the switching point voltage of the second gate means.

Abstract: Pulse techniques are used to periodically monitor a desired environmental condition, such as pressure. A solid-state switch is connected between a power source and a load. In the off state of the switch, power from the source drives a timer circuit which supplies a short voltage pulse to a circuit for sensing the environmental condition. At the same time, the pulse is supplied to associated circuitry for temperature compensation, amplification of the resulting sensing circuit signal, and a comparator circuit which determines whether or not a signal of the condition sensed exceeds a predetermined threshold. If such signal exceeds the threshold, the solid-state switch is turned on to connect the voltage source to the load. Turning on the switch results in substantially eliminating the voltage drop between the switch terminals, which previously was used to actuate the timer.

Abstract: A novel compensation device for conditioning or generating signals to have an arbitrarily defined shape, produced to an arbitrarily specified accuracy. The device comprises a plurality of bounded polynomial function generators having outputs summed into a summing network to produce a signal which is the composite of the effects of all of the polynomial generators. Accuracy is achieved through the use of fusible link trimming of the compensation circuits, which are configured to provide mathematically well-behaved polynomial functions with predictable responses to the programming, and which produce effects only over desired segments of the range of interest. The result is a monotonic signal with no discontinuities, which can be made arbitrarily close to a specified signal.

Abstract: A field programmable analog array cell (10) uses programmable impedance blocks (12, 18, 22, 24) in the feed-forward and feed-back paths of an amplifier (14) to set the overall function of the array. The impedance blocks use switches (34, 38, 42, 46) to program the desired impedance value. The switches induce leakage currents into the amplifier inputs which cause drift in the output voltage. A compensation circuit (28) providing a compensation current of opposite polarity to the leakage current to the same amplifier input to cancel its effects. Alternately, a compensation circuit (30) provides a compensation current having the same polarity as the leakage current to the opposite amplifier input to cancel its effects. A p-channel transistor (50) and n-channel transistor (54) are sized to one-half the total diffusion area of like semiconductor devices in the switching circuits.

Abstract: A process monitor for a CMOS integrated circuit includes first and second delay units that are connected in a ring to constitute a ring oscillator that generates pulses having different phases at the outputs of the delay units respectively. The delay units affect the frequency of the pulses and also the rising and falling edges of the pulses differently depending on the process factor of PMOS and NMOS transistors in the delay units. The process factor can be computed from the frequency, or the ratio of the phase differences between the rising and falling edges of the pulses at the outputs of the first and second delay units. The oscillatory configuration of the monitor is highly sensitive to variations in process factor, and enables the monitor to be embodied by a relatively small number of elements that can fit in two input/output slots in a standard integrated circuit layout.

Abstract: This invention deals with the problem of an error voltage in a MOSFET analog switch sample and hold circuit caused by the turn off charge in the MOSFET analog switch. The invention provides a compensating circuit which can be adjusted to exactly compensate for the turn off charge which causes the error so that the error can be reduced to zero or nearly zero. The compensating circuit can be used in both open loop and closed loop sample and hold circuits. The compensating circuit can be used in combination with a Miller feedback circuit for eliminating the error voltage.

Abstract: A MOSFET protection circuit includes a switch element which is thermally coupled to the MOSFET and switches the MOSFET off by establishing a connection between the gate and source electrodes thereof when a critical temperature is reached. The switch element also generates a temperature-dependent signal which controls a voltage reducing element connected between the gate and source electrodes of the MOSFET. The voltage reducing element is activated at a temperature which is lower than the critical temperature so that the gate-source voltage of the MOSFET and the current flowing therethrough is reduced as a result at the second temperature. The temperature rise is thereby slowed.

Abstract: A protective circuit having enhanced and accurate thermal shutdown temperatures. The protective circuit establishes the thermal shutdown temperature within a predetermined range and provides an output signal when the thermal shutdown temperature is exceeded. The protective circuit, in one embodiment, comprises a current generator for supplying a predetermined collector current I.sub.c1, a current mirror arrangement for supplying a collector current I.sub.c2 which has a mirror response to that of the collector current I.sub.c1, a resistor arranged to have the mirror collector current I.sub.c2 flowing therethrough, and the combination of a resistor and a bipolar transistor serving as a thermal sensor. The current generator comprises at least a pair of bipolar transistors selected from one of the NPN and PNP types with each of said pair operating with different current densities. The base electrodes of the pair are interconnected by a resistor. The collector current I.sub.

Abstract: A driving circuit is provided for a power transistor connected to an inductive load. A detection resistor is placed between ground and the emitter of the power transistor. The driving circuit has a first portion which is capable of generating a first current which is a non-linear function of the voltage across the detection resistance. A second portion of the driving circuit is used to generate a base current for the power transistor that is proportional to the first current. The non-linear function of the first current compensates for the non-linear gain with respect to collector current of the power transistor.

Abstract: Voltage translator apparatus to translate TTL or CMOS logic level inputs to 0/-5 V logic levels that is insensitive to temperative and bias supply variation. A unique circuit structure comprises a level shift stage employing transistors configured to level shift a source of operating potential to a controlling potential to be applied to a predriver stage. The controlling potential is a function of the input logic levels. The predriver stage drives an output stage capable of providing complementary 0/-5 V logic outputs. The configuration is such as to afford low power consumption as well as proper operation over wide bias supply and temperature ranges.

Abstract: A sense amplifier is provided that has improved speed from input to output, particularly during low-to-high transitions on the output and minimizes power consumption. By removing the product term window circuit from the critical node, the overall speed of the amplifier is maximized. In addition, circuitry is included to speed up low-to-high transitions, high-to-low transitions and provide increased noise immunity over temperature variations.

Abstract: A temperature compensation circuit (54 and 56, FIG. 3 ) is disclosed for maintaining the voltage at a first node. The amount of time the voltage at the first node is maintained is dependent upon the temperature of a temperature sensitive element (96). The circuit comprises a bleed-off transistor (86) and at least one temperature sensitive element (97). The first terminal (90) of the bleed-off transistor (86) is coupled to the first node and the second terminal (88) is coupled to a first voltage level. The control electrode (92) of the bleed-off transistor (86) is coupled to the first terminal (94) of the temperature sensitive element (96). The other pole of the element is coupled to a second voltage level. The element is operable to generate a voltage drop across its poles dependent upon its temperature.

Abstract: A method and apparatus for limiting current through a switching device supplying current to a load. A control evaluates a model representing the switching device temperature as a nonlinear function of current and time. The model compares the temperature of the switching device to a maximum allowable temperature. The current limit is defaulted to peak current; and in response to the model detecting a temperature in excess of the maximum allowable temperature, a nominal current limit is set. The current limit reset to peak current after the model detects a switching device temperature a predetermined magnitude below the maximum allowable temperature.