Abstract: Thermal management of an electronic switch, that provides power to a load, is achieved by monitoring a switch temperature of the electronic switch. When the switch temperature exceeds a first set temperature, the control signal is modified such that an average power dissipated by the electronic switch is reduced. In one embodiment, the control signal is modified by increasing a slew rate of the control signal when the switch temperature exceeds the first set temperature. In another embodiment, a frequency of the control signal is reduced when the switch temperature exceeds the first set temperature.

Abstract: A semiconductor switching device has a first semiconductor element, a second semiconductor element, and a comparator. The first semiconductor element has a first main electrode, a second main electrode, and a control electrode. The second semiconductor element has a first main electrode connected to the first main electrode of the first semiconductor element, a control electrode connected to the control electrode of the fist semiconductor element, and a second main electrode connected to a circuit that consists of a resistor and a constant current source that are connected in parallel with each other. The comparator compares potentials of the second main electrodes of the first and second semiconductor elements with each other. If the potential of the second main electrode of the first semiconductor element exceeds the potential of the second main electrode of the second semiconductor element, it is determined that there is a break in the load.

Abstract: An integrated circuit includes a terminal supplying a digital signal, a controllable driver circuit connected to the terminal and outputting the digital signal, and a comparator device. An actuating circuit actuates the driver circuit as a function of a clock signal. The comparator device compares the timing of signal transitions of the clock signal with transitions of the digital signal. The comparator has a first comparator input for receiving the clock signal and a second comparator input connected to the driver output for receiving the digital signal. The comparator device outputs an output signal having a first state if a signal transition of the clock signal at the first input takes place before a signal transition of the digital signal at the second input, and outputs a second state if the clock signal transition takes place after digital signal transition. In a test mode, the invention compares the clock and digital signal timings with a high degree of accuracy.

Abstract: Curvature in the temperature response of junction voltage of a diode or transistor is compensated by circuitry which offsets the curvature at temperatures below a reference temperature and at temperatures above a reference temperature. Two current sources are provided including a first current source of current proportional to absolute temperature (PTAT) less a current complimentary to absolute temperature (CTAT) and a second current source of PTAT plus beta times CTAT (PTAT+&bgr;CTAT).

Abstract: A pulse signal output circuit charges and discharges a capacitor in response to a clock signal and outputs a pulse signal having a pulse width determined by a time for charging and discharging the capacitor. A control signal generation circuit outputs a control signal in response to the pulse signal, where the control signal has a first voltage level determined by the pulse width. An output circuit has a first output transistor and a first regulating transistor connected in series between the first power supply node and the output terminal. The first output transistor is operated in response to a signal transferred from inside or outside a semiconductor device, and the first regulating transistor is operated in response to the control signal.

Abstract: A data transmission circuit is provided for compensating for a difference between data transmission speed occurring at start and end portions of a data line. The circuit minimizes a time delay caused by resistance/capacitance loading of the data line through which data is transmitted, thereby improving data transmission speed. The data transmission circuit of the present invention includes a compensation circuit to compensate for the time delay between the data signals at the start and end portions of the data line. The compensation circuit is adapted to amplify and rapidly develop a data signal at the end portion of the data line through which a data signal is enabled from its high state to its low state and transmitted as a data signal at the end portion of the data line.

Abstract: A circuit and method are disclosed for biasing a power transistor to offset unwanted variations in the operating characteristics thereof. The circuit includes a correction transistor having the same device structure as the structure of the power transistor. In addition, one or more dimensions of the correction transistor is scaled relative to corresponding dimensions of the power transistor. The correction transistor is biased so that the ratio of drain currents of the correction transistor and the power transistor is the same as the size ratio thereof. In this way, the output signal of the correction transistor is based upon an unwanted variation in the operating characteristics of the power transistor. The output terminal of the correction transistor is amplified and coupled to the control terminal of the power transistor so that the bias signal applied to the control terminal thereof offsets the unwanted variation in the operating characteristics of the power transistor.

Abstract: For use with a semiconductor switch that exhibits a temperature-dependent electrical characteristic and a current sense circuit that employs the characteristic of the switch to derive a switch current signal, a temperature compensation circuit, method of operation thereof and controller employing the same. In one embodiment, the circuit includes: (1) an electrical component, locatable in thermal communication with the switch and having a temperature-dependent electrical characteristic that bears an inverse relationship to the characteristic of the switch, that generates an intermediate signal based on an actual temperature of the switch and (2) a signal conditioning circuit, coupled to the electrical component, that scales the intermediate signal to yield a compensation signal that counteracts temperature-dependent variations in the switch current signal.

Abstract: An output buffer provides a stable, predetermined low voltage differential over power supply, temperature, and process variations yet has a high speed of operation. More particularly, a data path of an output buffer includes an emitter-coupled differential amplifier followed by an output section of two level-shifting emitter followers. A predetermined operating current biases the differential amplifier for unsaturated operation and a reference current biases the output section for unsaturated operation. The data path remains unencumbered by compensation circuitry to preserve high speed operation. Instead, a voltage compensator biases the differential amplifier to compensate, at least in part, for variations in a supply voltage. In addition, a variable biasing current to the voltage compensator with a predetermined temperature coefficient may further temperature compensate the differential amplifier.

Abstract: A leakage current correcting circuit for reducing a leakage current flowing into an output of a circuit in a high impedance state. The configuration includes a correcting unit having a current detecting circuit for detecting a leakage current and outputting a current equal to a detected leakage current, and a current supply circuit for receiving the output current from the current detecting circuit as an input and causing a current for offsetting the leakage current flowing into the output of the circuit in a high impedance state.

Abstract: A device (DC) is provided for compensating process and operating parameters variations in a CMOS integrated circuit. The device comprises means (CP, CT) for generating a first and a second compensation signals which depend on quality indexes of the fabrication process of the P and N transistors of the integrated circuit and on the operating temperature, and which are capable of compensating deviations of the controlled quantity from the desired value, due to the deviation of the quality indexes and temperature, respectively, from a typical value which would originate the desired value for the output parameter. The compensating device also can be implemented in the form of CMOS integrated circuit, preferably jointly with the device (OS) to be subjected to compensation (FIG. 1).

Abstract: A circuit and method for providing temperature stability in an FM quadrature detector. The circuit includes a feedback branch that feeds a portion of the dc output voltage to a varactor diode that is connected in parallel with a capacitor of an LC circuit in the quadrature detector. When the ambient temperature of the LC circuit of the quadrature detector changes, the resonant frequency shifts from the desired center value and a dc voltage is introduced at the output of the quadrature detector. The dc voltage is input to the varactor diode via the feedback circuit branch, and the capacitance of the varactor diode, which is dependent on the dc voltage applied to it, causes the overall capacitance of the LC circuit to change. The change in overall capacitance of the LC circuit caused by the capacitance of the varactor diode causes the resonant frequency of the quadrature detector to shift to be more closely maintained at the desired center frequency.

Abstract: Control circuitry is used to provide a uniform temperature distribution between multiple power supplies on a chip which drive a single load. The power supplies each include a MOSFET with a source to drain path connecting VDD to the single load. The control circuitry includes a bipolar diode placed close to the MOSFET in each power supply unit, each diode providing a voltage varying inversely proportional to temperature changes resulting from power dissipated by its respective MOSFET. The control circuitry further includes components in each power supply unit to provide the voltage from the bipolar diode with the lowest voltage (or highest temperature) on a bus external to the power supply units. The bus voltage is then examined in the control circuitry in each of the power supply units and if the bipolar diode voltage in a unit is equal to the bus voltage, that unit does not increase current from its respective MOSFET to the load since it has the highest temperature.

Abstract: A DC offset compensation circuit (34) for compensating for a DC offset voltage of a signal amplifier (24) includes a first sample and hold circuit (40) having an input receiving an amplifier output signal (VOUT2) and an output supplying the sampled and held output signal (VOUT2) to a non-inverting input of a comparator 42. A first digital-to-analog (D/A) circuit (46) is responsive to a number of digital input signals to produce an analog DC target signal at an output (VD) thereof. The analog DC target signal is provided to an input of a second sample and hold circuit (50) having an output supplying the sampled and held analog DC target signal to an inverting input of the comparator 42. The output of the comparator 42 is provided to an offset cancellation control circuit (56) including a state machine (66) and a counter circuit (68) operable to modify a count value (OFFDAC) thereof depending upon statuses of a number of input control signals (CLK1, CLK2, STRT, STP) and the comparator output signal (CO).

Abstract: Disclosed is a data output buffer improving the drivability, by increasing the power supply voltage and keeping the power supply voltage constant, without being modification and increase of the manufacturing process of the device. Furthermore, the improvement of the drivability may increase the speed of the data output buffer and decrease the chip area.

Abstract: For use with a semiconductor switch that exhibits a temperature-dependent electrical characteristic and a current sense circuit that employs the characteristic of the switch to derive a switch current signal, a temperature compensation circuit, method of operation thereof and controller employing the same. In one embodiment, the circuit includes: (1) an electrical component, locatable in thermal communication with the switch and having a temperature-dependent electrical characteristic that bears an inverse relationship to the characteristic of the switch, that generates an intermediate signal based on an actual temperature of the switch and (2) a signal conditioning circuit, coupled to the electrical component, that scales the intermediate signal to yield a compensation signal that counteracts temperature-dependent variations in the switch current signal.

Abstract: The circuit configuration for sensing when a critical temperature of a component has been exceeded makes use of at least one sense transistor which has a temperature-dependent current/voltage characteristic and which is thermally connected to the component. A current source is connected in series with the sense transistor. A circuit device for compensating for parasitic leakage currents at the sense transistor is provided. The circuit device has a measurement transistor and two current mirror circuits. By compensating for leakage currents, the proper operation of the temperature sensor is guaranteed over the entire temperature range and the destruction of the component is prevented.

Abstract: Process monitoring circuitry according to the invention incorporates additional routing structures that approximate signal delays due to long metal routing paths. The additional process monitor circuitry builds upon existing approaches without increasing the die size of an integrated circuit through the utilization of excess silicon space available between the bonding pads and the scribe lines of an integrated circuit wafer. More specifically, supplemental metal routing lines and vias are included in the delay paths of process monitor circuitry and located on the integrated circuit such that impact to other metal signal lines/vias used in the actual design is minimized. The supplemental metal routing lines are disposed in unused routable silicon space, such that no silicon area penalty is suffered as a result of having long metal routing lines.

Abstract: A reference circuit includes a first resistive element and a current source. The first resistive element is adapted to produce an output voltage based on a first current and a resistance of the first resistive element. The resistance of the first resistive element is a function of a temperature of the current. The current source includes a second resistive element that has a resistance that is a function of the temperature. The current source is adapted to adjust the first current to minimize variation of the output voltage with the temperature based on the resistance of the second resistive element.

Abstract: A looped circuit for generating a variable bias voltage. The looped circuit includes a variable current source having a current output that is dependent upon the variable bias voltage. The looped circuit also includes a capacitor that is periodically coupled to the current source for a predetermined period of time, wherein the current source charges the capacitor during each predetermined period of time. At least one subcircuit is provided for varying the variable bias voltage, wherein the variable bias voltage automatically causes the current source to charge the capacitor to a predetermined reference voltage during each predetermined period of time. Accordingly, the generated bias voltage will vary with temperature and other external variables. However, the ratio of the current produced by the current source divided by the capacitance of the capacitor is equal to the ratio of the predetermined reference voltage divided by the referenced predetermined period of time.

Abstract: A circuit for compensating a silicon strain gauge pressure transmitter. The circuit includes: a current source, an embodiment of which may include an amplifying device and means for supplying the current source with an electric potential, a strain gauge bridge, a plurality of resistances that includes a feedback resistance, a series resistance, a current sampling resistance, and a load with parameters. The key to this invention is to add a series resistance and a feedback resistance to the circuit which eliminates the need for R.sub.c, the current sample resistor, to be a thermistor, and increases the operating temperature range of the sensor by compensating the sensor's parameter variations with temperature.

Abstract: A temperature compensation circuit is provided for use in conjunction with a Hall effect element in which the temperature compensating resistors, or epitaxial resistors, are not placed in the signal loop as portions of the feedback loops of amplifiers. The circuit therefore permits a higher degree of linearity and temperature compensation without inducing the problems that are normally caused by varying voltage potentials across the epitaxial resistors. One embodiment of the circuit also provides a means for clamping, or truncating the output voltage of the circuit to a preselected percentage of the supply voltage even though the supply voltage may vary during the operation of the device. The circuit utilizes several external trimmable resistors to perform final adjustment on the circuit in order to permit individual variations from component to component to be compensated.

Abstract: Disclosed is a circuit and method for compensating DC output level variations in a differential emitter-coupled logic circuit. The DC output level compensating differential emitter-coupled logic circuit includes a differential pair, an output stage, and a compensation circuit. The differential pair is configured to receive a differential signal and is operative to generate a differential signal. The output stage is coupled to the differential pair to receive the differential signal and is operative to generate a differential output signal at a DC output voltage level. The compensation circuit is coupled to the differential pair and the output stage and is operative to develop a compensating voltage drop in the differential pair so as to compensate for a change in the DC output voltage level when the temperature varies such that the output stage outputs the differential output signal at the DC output voltage level.

Abstract: A driver circuit having a temperature correction circuit for producing an output signal with high precision amplitude and timing by correcting the temperature changes in the amplitude and timing. The temperature correction circuit includes a temperature detector for detecting the temperature change in output elements, a timing adjustment circuit for correcting the timing of an output signal relative to an input signal upon receiving the temperature detection signal from the temperature detector, and a bias circuit for correcting the output amplitude and impedance of the output signal.

Abstract: An output buffer translates digital input signals which toggle between ground and V.sub.DDL to signals which toggle between ground and V.sub.DDH. The technology dielectric breakdown voltage limit is less than the magnitude of V.sub.DDH, such that use of a traditional output stage would subject transistors' dielectrics to voltages which exceed their dielectric breakdown limit, and would thus be damaged. Predrive circuits (40, 50) control output stage (70) transistors' (72, 78) gates, and voltage dropping circuits control output stage (70) transistors (74, 76). These control signals are generated specifically to maximize output stage transistor drive strengths, thereby minimizing output stage size. Output buffer functions when V.sub.DDL =V.sub.DDH, and its performance is V.sub.DDL independent. Temperature compensation is incorporated into the output buffer by deliberately offsetting temperature effects on output stage transistor drive strengths.

Abstract: An integrated circuit comprising a power transistor and a circuit arrangement. The circuit arrangement is thermally coupled to the power transistor and operates in a temperature-dependent fashion. The integrated circuit includes a pnp or npn transistor with a temperature dependent resistor coupled between the base and emitter of the transistor. The off-state current of the transistor changes as a function of temperature and initiates a change in a base current of the power transistor.

Abstract: A compensation circuit which accounts for variations in both temperature and V.sub.CC supply voltage on an integrated circuit. The compensation circuit includes four quasi-independent compensation current sources, each of which generates a corresponding compensation current. The first compensation current source generates a first compensation current which has a positive slope with respect to temperature. The second compensation current source generates a second compensation current which has a negative slope with respect to temperature. The third compensation current source generates a third compensation current which has a negative slope with respect to the V.sub.CC supply voltage. The fourth compensation current source generates a fourth compensation current which has a positive slope with respect to the V.sub.CC supply voltage. The first, second, third and fourth compensation currents are summed to create a total compensation current.

Abstract: An interface output stage includes a pull-up circuit and a pull-down circuit connected to a positive power supply signal line having a first voltage, an output signal line having an output voltage and a negative power supply signal line having a second voltage. The pull-up circuit includes a single output transistor and a body snatcher circuit, both interconnected between the positive power supply signal line and the output signal line. The body snatcher circuit ties the bodies of the output transistor and the transistors forming the body snatcher circuit to either the first voltage or the output voltage. The pull-down circuit is designed generally similar to the pull-up circuit to tie bodies of its transistors to either the output voltage or the second voltage.

Abstract: A monitor within an integrated circuit is disclosed for providing a signal which is proportional to an integrated circuits operating environment. A differential gain cell within the integrated circuit is biased with a bias circuit. A first environment sensitive circuit provides a signal to the first input of the differential gain cell and a second environment sensitive circuit provides a signal with a known relationship to the first environment sensitive signal to the second input of the differential gain cell. The signal produced by the second environment sensitive circuit has a known operational relationship with the signal produced by the first environment sensitive circuit such that changes in the integrated circuit operating environment produce a deviation between the two signals. The differential gain cell in response to the signal received on its first input and second input produces a signal which is responsive to the operating environment of the integrated circuit.

Abstract: A driver circuit having a temperature correction circuit for providing a relatively stable output amplitude and timing by detecting electric consumption of an output stage of the driver circuit and correcting the changes in the amplitude and timing of an output signal therefrom. The temperature correction circuit includes a temperature detection part for detecting temperature change in a pair of output elements, an output timing temperature correction part for correcting the output timing of the output signal relative to an input signal upon receiving the temperature detection signal from the temperature detection part, and an output amplitude and impedance temperature correction part for correcting output amplitudes and output impedance of the output signal.

Abstract: A high swing interface output stage integrated circuit for interfacing a data communications device with a data bus which may operate at voltage ranges outside the supply voltage of the interface circuit. An output terminal of the integrated circuit is coupled to a positive supply rail of the circuit through a substrate NPN transistor, and to a ground rail through first and second NMOS FETS. A third MOS FET also formed is coupled between the common connection of the first and second NMOS FETS and the gate of the second NMOS FET for holding the second NMOS FET off in the event of the voltage on the output terminal being driven below the ground voltage of the circuit. Other NMOS and PMOS FETS in the circuit control the operation of the circuit for determining the high and low states of the voltage on the output terminal.

Abstract: A supply and temperature dependent linear signal generating circuit includes four transistors each having a unique current flowing therethrough and connected together to form a current multiplier. A first one of the currents is designed to be supply dependent and preferably adjustable in magnitude, a second one is designed to exhibit a specific temperature dependence, the third is designed to be both supply and temperature independent and the fourth current is defined as a ratio of the first three. The fourth current is, in one embodiment, impressed upon a network defined by a resistor divider and a voltage source to thereby define an output voltage V(T) that is both supply and temperature dependent according to the following equation:V(T)=KX*(T-TN),wherein KX is the slope of V(T) over temperature, T is the operating temperature and TN is a reference temperature at which V(T) is equal to zero. Preferably, TN is adjustable via the adjustable magnitude of the first current.

Abstract: A capacitor is connected between the gate of a transistor that is an object of threshold voltage compensation and an input terminal. A switching device is connected between a current source connected to one terminal of the transistor and the gate of the transistor. A second switching device is connected between the input terminal and a terminal to which a reference voltage is applied. The switching device is turned ON so that the transistor is diode-connected. The switching device is turned ON, thus applying the reference voltage to the input terminal. A reference voltage is applied to a current inflow terminal connected to another terminal of the transistor. After charge dependent on the threshold voltage of the transistor is accumulated in the capacitor, the switching device is turned OFF. With this control, a difference of a threshold voltage from another deriving from the fine structure of transistors as well as a difference in threshold voltage between adjoining transistors can be compensated for.

Abstract: A system and method for regulating temperature of a microprocessor include an oscillator having a frequency which varies based on temperature of the microprocessor wherein the oscillator is connected to the clock input of the microprocessor. The system and method allow operation of the microprocessor at reduced clock frequencies in an attempt to reduce heat generation and stabilize the microprocessor temperature prior to occurrence of a permanent failure due to an operation at excessive temperature.

Abstract: A circuit for generating a signal with a 50% duty cycle comprises an oscillator that provides a first control signal, a reference generator that provides a first reference signal, a control circuit that provides a second control signal and that is responsive to the first reference signal, a first current source load inverter that provides the second reference signal and that is responsive to the second control signal, and an output circuit that provides an output signal having a duty cycle substantially equal to 50% and a frequency substantially equal to that of the first control signal. The output circuit further includes a second current source load inverter that is responsive to both the first and second control signals.

Abstract: A CMOS analog divider/multiplier/ratiometry circuit that provides a ratiometric output of two or more inputs, where the output is insensitive to process parameters and temperature variations effecting the circuit. The analog divider/multiplier/ratiometry circuit includes a multiplier portion made up of six FET devices. The six FET devices are electrically connected together so that first and second current outputs from the multiplier portion are insensitive to process parameter and temperature variations effecting the circuit. A first input current is applied to a gate terminal of one of the FET devices and a second input current is applied to a gate terminal of the FET devices in the multiplier portion of the circuit. The first and second input currents are based on currents generated by first and second linear voltage-to-current converter input circuits that are responsive to first and second input voltage, respectively, whose ratio or product is to be determined at the output of the circuit.

Abstract: A dynamic voltage reference circuit for generating one or more control signals for use in controlling a delay circuit or other circuit that requires compensation for process variations. The control signals are generated without drawing DC current at times other than when the active edge is propagating through the delay circuit. As a result, a reference generator with reduced power consumption is realized.

Abstract: A temperature compensation circuit which includes a signal detecting circuit provided on a signal supply path which outputs logic signals to a target circuit. Also included are switch elements which turn current on/off to heater elements each time the signal detecting circuit detects that the logic signals are being applied to the target circuit. The power source of the invention therefore only needs to endure the same amount of current applied to the target circuit which leads to a reduction in power consumption.

Abstract: The gating circuit has a power transistor (T1, T2, T3) and a current measuring resistor (R5) connected with the power transistor so that a voltage drop at the measuring resistor is a measure of a current flow in the power transistor. This voltage drop is used to trigger a current regulating transistor (T5) and a temperature measuring transistor (T9). Below a predetermined temperature, the current flow is limited solely by the current regulating transistor (T5). Above this predetermined temperature the collector current is further reduced via the temperature measuring transistor (T9) and a further transistor (T10) so as to protect the power transistor from thermal overload.

Abstract: A switch-control integrated circuit for a switch-mode power supply (SMPS) capable of consistently limiting the peak current value of an output supply voltage irrespective of a temperature change. The circuit includes a switching transistor of the SMPS and a sensing resistor coupled to a drain of the switching transistor for sensing a drain current of the switching transistor to produce a peak current value detection voltage. A voltage generating circuit generates a feedback voltage which varies depending on the temperature condition equal to that of the sensing resistor. A comparator compares the temperature dependent voltage, received at a first input, with the temperature dependent peak current value detection voltage, received at a second input, to produce a temperature independent control signal. A protection circuit, coupled between the comparator and the switching transistor, interrupts the control signal if an abnormal operation of the voltage generating section is detected.

Abstract: The speed gap between rise and fall times of a buffer biased by a power supply having a power supply voltage, the speed gap varying in a first manner with respect to the power supply voltage and in a second manner inverse to the first manner with respect to a bias current supplied to the buffer, is controlled by generating the bias current such that the bias current varies inversely with respect to the power supply voltage, thereby compensating for fluctuations in the power supply voltage and maintaining the speed gap within a predetermined range when the power supply voltage is greater than a power supply voltage threshold level.

Abstract: A circuit for a sense amplifier (14) for use with a memory device (10). The circuit includes two devices (40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second device (42) drives the sense amplifier (14) with a second current level, different from the first current level. The selector (44) is coupled to the first and second devices (40 and 42) so as to selectively couple one of the first and second devices (40 and 42) to the sense amplifier (14) based on a power supply voltage of the memory device (10).

Abstract: A CMOS current reference is provided that is relatively independent of supply voltage and generates a substantially steady current. The current reference includes a plurality of P-channel FETs and a plurality of zero threshold voltage N-channel FETs that provide a high level of voltage supply rejection at relatively low supply voltage levels (1.5 to 3.3 volts). Utilization of the P-channel FETs and the zero threshold voltage N-channel FETs in a current mirror and cascade configuration reduces the sensitivity of the current to variations in the supply voltage. The current reference exhibits higher offset voltage capabilities. In addition, the CMOS current reference may be designed to compensate for process variations since the current will increase as the channel length of the zero threshold voltage N-channel FETs increases.

Abstract: An integrated circuit including a temperature threshold detector. This detector includes two MOS transistors with a same type of conductivity, circuitry for applying to the second transistor a gate-source voltage higher than the gate-source voltage of the first transistor by a value Vbe, VbE being the drop in voltage at the terminals of a forward-biased PN junction, and a comparator for comparing the currents flowing in the two transistors. The current in the second transistor diminishes faster than the current in the first transistor. If the dimensions of the transistors are accurately chosen, the curves pertaining to the diminishing of current (or curves deduced from these curves by homothetic transformation) intersect one another for a certain temperature. The detection of equality of the currents therefore enables a detection of the passage through this temperature.

Abstract: A process monitor for a CMOS integrated circuit includes first and second delay units that are connected in a ring to constitute a ring oscillator that generates pulses having different phases at the outputs of the delay units respectively. The delay units affect the frequency of the pulses and also the rising and falling edges of the pulses differently depending on the process factor of PMOS and NMOS transistors in the delay units. The process factor can be computed from the frequency, or the ratio of the phase differences between the rising and falling edges of the pulses at the outputs of the first and second delay units. The oscillatory configuration of the monitor is highly sensitive to variations in process factor, and enables the monitor to be embodied by a relatively small number of elements that can fit in two input/output slots in a standard integrated circuit layout.

Abstract: A high input resistance circuit that produces an output signal with a voltage gain of unity includes an input section, a feedback section, a high input resistance amplification section, and an output section. In the input section, transistors 1.sub.a and 1.sub.b form a differential amplification circuit using transistors 2.sub.a and 2.sub.b as emitter resistors, respectively. A feedback circuit is formed by transistors 3.sub.a and 3.sub.b whose collectors are connected to bases of transistors 1.sub.a, 1.sub.b, respectively, and whose emitters are connected to the collector of transistor 8.sub.b of the output section. The bases of transistors 3.sub.a and 3.sub.b are provided a bias from a bias terminal 106 so as to suppress a collector current. In the high input resistance amplification section, transistors 4.sub.a and 4.sub.b form an emitter follower circuit using transistors 5.sub.a, 5.sub.b and resistors R.sub.1, R.sub.2 as emitter resistors, respectively. In the output section, transistors 6.sub.a and 6.

Abstract: The inventor has created several methods to eliminate or greatly reduce the ground loop problem. The inventor has discover that ground loop distortion is caused by the switching from positive to negative in alternating current. He has designed several devices to eliminate this problem. In his first embodiment he places a set of two diodes either cathode to cathode or anode to anode, or a neon bulb, or piezoelectric crystals in parallel with all the capacitors in an amplifier or other electronic device. These sets of diodes eliminate the ground loop distortion within the amplifier or electronic device. The applicant has also devises several power supply that eliminate or greatly reduce the ground loop distortion in an amplifier or electronic device they are attached to. Also the applicant has found that by attaching two diodes either anode to anode or cathode to cathode, or a neon bulb, or a piezoelectric crystals between an audio, video or digital cable and its ground will reduce distortion within the cable.

Abstract: A process for evaluating acceptability of a digital circuit having a first type of circuit element for a first change of state and a second type of circuit element for a second change of state, the process comprising: generating a leading edge of a first pulse with a pulse generation circuit formed on a substrate in common with the digital circuit and having elements of the first and the second type; generating a trailing edge of a first pulse with a pulse generation circuit formed on a substrate in common with the digital circuit and having elements of the first and the second type; generating an accepted-rejected signal, functionally related to the width of the pulse.

Abstract: A line driver having two halves arranged in a push-pull configuration. Each half has a pass transistor, connected between a power supply rail and an output terminal, and an amplifier with an output coupled to the output terminal. Only one of the pass transistors conducts at any given time. A sense transistor, coupled between the power supply rail and the input of the amplifier, varies the output of the amplifier to compensate for variations in the conductivity of the conducting pass transistor. Preferably, the current density in the sense transistor is substantially the same as in the conducting pass transistor.

Abstract: A compensating circuit (8) is used with a switched capacitor circuit (10) which includes a switched capacitor arrangement (12) and an op-amp (1) having a first input (14) coupled to a switched capacitor (11), a second input and an output (16). A sampling circuit (19,17,23) samples an error signal at the first input (14) of the op-amp (1) and an amplifier (15) coupled to receive the sampled error signal provides a compensation signal in dependence upon the sampled error signal. The compensation signal provides an offset signal for the second input of the op-amp (1), such that propagation of the error signal to the output (16) of the op-amp (1) is substantially reduced.