With Capacitive Bootstrapping Patents (Class 327/390)
  • Patent number: 10396579
    Abstract: An electronic circuit is disclosed. The electronic circuit includes a GaN substrate, a first power supply node on the substrate, an output node, a signal node, and an output component on the substrate, where the output component is configured to generate a voltage at the output node based at least in part on a voltage at the signal node. The electronic circuit also includes a capacitor coupled to the signal node, where, the capacitor is configured to selectively cause the voltage at the signal node to be greater than the voltage of the first power supply node, such that the output component causes the voltage at the output node to be substantially equal to the voltage of the first power supply node.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: August 27, 2019
    Assignee: NAVITAS SEMICONDUCTOR, INC.
    Inventors: Daniel Marvin Kinzer, Santosh Sharma, Ju Zhang
  • Patent number: 10355686
    Abstract: Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 16, 2019
    Assignee: Maxlinear, Inc.
    Inventors: Yongjian Tang, Xuefeng Chen
  • Patent number: 10250250
    Abstract: The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: April 2, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Siddharth Devarajan, Lawrence A. Singer
  • Patent number: 10236770
    Abstract: The present disclosure relates to a high-voltage generator with multi-stage selection in low-voltage transistor process which include a boosted circuit, a plurality of switch and a feedback circuit. The boosted circuit includes multiple charge pump, so that can generate a DC output voltage higher or lower than the input signal. Turning on or turning off each switch controlled by a control signal respectively. Both ends of the circuit is connected to the output end of the high-voltage generator and charge pumps. By controlling the turning on or turning off each switch, it determines the magnitude of the boost and it also can ensure that switches will not be damaged due to excessive voltage difference.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: March 19, 2019
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Ming-Dou Ker, Li-Chin Yu
  • Patent number: 10198052
    Abstract: Embodiments are described including those for controlling peak current consumption of a multi-chip memory package during power-up. In one embodiment, each memory device of the multi-chip package includes a power level detector used to compare an internal voltage signal to a threshold. A current limiter controls the ramping rate of the internal voltage signal in response to the power level detector as the internal voltage signal ramps up towards the threshold.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: February 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: June Lee
  • Patent number: 10050621
    Abstract: A semiconductor device includes a power transistor and a driving circuit. The driving circuit is coupled to and is configured to drive the power transistor and includes first and second stages. The second stage is coupled between the first stage and the power transistor. Each of the first and second stages includes a pair of enhancement-mode high-electron-mobility transistors (HEMTs). The construction as such lowers a static current of the driving circuit.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chan-Hong Chern, Chu Fu Chen, Chun Lin Tsai, Mark Chen, King-Yuen Wong, Ming-Cheng Lin, Tysh-Bin Liu
  • Patent number: 9972586
    Abstract: In order to realize a silicon PUF of lower power consumption, a semiconductor device includes first and second MIS transistors of the same conductive type in off-state coupled in series, as a PUF element. The PUF element outputs a signal of high level or low level depending on the potential of a connection node of the first and the second MIS transistors. Preferably, the MIS transistors are fin-type FETs.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: May 15, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Takeshi Okagaki
  • Patent number: 9847713
    Abstract: A charge pump circuit having first and second input nodes to be coupled to a first power source, and top and bottom output nodes and an intermediate node. The charge pump circuit produces i) a voltage at the top output node that is higher than a voltage of the intermediate node, and ii) a voltage at the bottom output node that is lower than the voltage of the intermediate node. A bias voltage source has i) an input that is to be coupled to a second power source and ii) an output that produces an output voltage, which is a predetermined proportion of an input voltage at the input and that follows the input voltage downward and upward as the input voltage sags and recovers, respectively. The output of the bias voltage source is directly connected to the intermediate node of the output stage. Other embodiments are also described.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: December 19, 2017
    Assignee: APPLE INC.
    Inventors: David C. Breece, III, Roderick B. Hogan, Nathan A. Johanningsmeier
  • Patent number: 9813057
    Abstract: A sampling circuit for sampling an input voltage and generating an output voltage, comprising six switches, a capacitor and a voltage buffer. The first switch has a control terminal and makes the output voltage equal to the input voltage when switching on. The second switch is coupled to a first terminal of the capacitor and a first level. The third switch is coupled to a second terminal of the capacitor and a second level. The fourth switch is coupled to the first terminal of the capacitor and the control terminal. The fifth switch is coupled to the control terminal and the second level. The voltage buffer has large input impedance, and has an input receiving the input voltage, an output providing a voltage equal or close to the input voltage. The sixth switch is coupled to the second terminal of the capacitor and the output of the voltage buffer.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: November 7, 2017
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ming-Cheng Chiang, Li-Lung Kao
  • Patent number: 9781371
    Abstract: A solid state image sensor includes a pixel array, as well as charge-to-voltage converters, reset gates, and amplifiers each shared by a plurality of pixels in the array. The voltage level of the reset gate power supply is set higher than the voltage level of the amplifier power supply. Additionally, charge overflowing from photodetectors in the pixels may be discarded into the charge-to-voltage converters. The image sensor may also include a row scanner configured such that, while scanning a row in the pixel array to read out signals therefrom, the row scanner resets the charge in the photodetectors of the pixels sharing a charge-to-voltage converter with pixels on the readout row. The charge reset is conducted simultaneously with or prior to reading out the signals from the pixels on the readout row.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: October 3, 2017
    Assignee: Sony Corporation
    Inventors: Takeshi Yanagita, Keiji Mabuchi, Hiroaki Ishiwata
  • Patent number: 9755582
    Abstract: A switch circuit comprising: a plurality of switches; a switching module; and a capacitor, having a first terminal and a second terminal, wherein the first terminal is coupled to a predetermined voltage, and the second terminal is coupled to a control terminal of at least the switch in a conductive mode via the switching module, to thereby control a conductive state for the at least one switch.
    Type: Grant
    Filed: July 29, 2012
    Date of Patent: September 5, 2017
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jian-Ru Lin, Shin-Syong Huang
  • Patent number: 9641166
    Abstract: An apparatus and method for implementing a bootstrapped switching circuit having improved (i.e. faster) turn-on time is provided. In an embodiment, an inner switching loop is implemented in a bootstrapped switching circuit where the inner switching loop is configured to turn on an input switch in the bootstrapped drive circuit independent of the drive circuit output. The embodiment decouples the inner switching loop circuitry from the output drive circuit of the bootstrapped switching circuit, which typically has a larger load capacitance than the inner switching loop. This allows the inner switching loop to turn on the input switch in the bootstrapped switching circuit faster and decreases the turn-on time of the bootstrapped switching circuit.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: May 2, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventors: Siddharth Devarajan, Lawrence A. Singer
  • Patent number: 9621157
    Abstract: A sampling circuit for sampling an input voltage and generating an output voltage, comprising six switches, a capacitor and a voltage buffer. The first switch has a control terminal and makes the output voltage equal to the input voltage when switching on. The second switch is coupled to a first terminal of the capacitor and a first level. The third switch is coupled to a second terminal of the capacitor and a second level. The fourth switch is coupled to the first terminal of the capacitor and the control terminal. The fifth switch is coupled to the control terminal and the second level. The voltage buffer has large input impedance, and has an input receiving the input voltage, an output providing a voltage equal or close to the input voltage. The sixth switch is coupled to the second terminal of the capacitor and the output of the voltage buffer.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: April 11, 2017
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ming-Cheng Chiang, Li-Lung Kao
  • Patent number: 9584020
    Abstract: Devices and methods provide a duty cycle clamping device for preventing an output voltage of a power converter from decreasing as the duty cycle of a pulse width modulation (PWM) signal driving the power converter increases, the clamping device including duty cycle clamping circuitry configured to determine a critical duty cycle for the PWM signal based on an input voltage, a top voltage of a flying capacitor and a bottom voltage of the flying capacitor, and configured to clamp an actual duty cycle of the PWM signal at the critical duty cycle if a desired duty cycle exceeds the critical duty cycle.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: February 28, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Rendon Holloway
  • Patent number: 9559713
    Abstract: An analog-to-digital converter (ADC) is used for dynamic tracking nonlinearity correction. The correction employs an analog sampling technique to determine the signal derivative by measuring the derivative current arising from sampling an analog input signal undergoing analog-to-digital conversion, at the sampling instant. The analog derivative sampling technique achieves significant reduction in power consumption with less complexity compared with a digital approach, with strong improvements in HD3, SDFR, and IM3 measures.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: January 31, 2017
    Assignee: Broadcom Corporation
    Inventors: Rong Wu, Tianwei Li
  • Patent number: 9479882
    Abstract: An audio accessory key detection system (40) includes a host circuit (2-3) coupled to communicate via a microphone line (7) with an accessory circuit (3-3) in either a MSFT mode or a digital communication mode. Depletion mode transistors (44-1,2,3) in the accessory circuit are coupled between keys (15-1,2,3) of the accessory circuit, respectively. The depletion mode transistors are allowed to remain conductive for MSFT mode operation. For digital communications mode operation, the host circuit sends a command via the microphone line to a key detector and controller circuit (29A) in the accessory circuit. In response, a voltage is generated to turn the depletion mode transistors off so as to allow digital communications mode operation between the accessory circuit and the host circuit.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: October 25, 2016
    Assignee: Texas Instruments Incorporated
    Inventors: Ball Fan, Wenpang David Wang, Christopher Michael Graves
  • Patent number: 9466493
    Abstract: A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: October 11, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Huei Chen, Chien Chi Tien, Kao-Cheng Lin, Jung-Hsuan Chen
  • Patent number: 9401727
    Abstract: In a time-interleaved Analog to Digital Converter, circuit components and capacitances may be shared among a plurality of sample and hold circuits in each of two sets. The two shared circuits alternate, on different half-periods of a master clock signal, between charging a capacitance and sampling an input in an overlapping manner such that one is charging while the other is sampling. One sample and hold circuit is activated during each successive half-period (following a charging half-period) by independent, sequential, non-overlapping clocking signals. To improve SNDR, at least one switch is bootstrapped by driving its gate terminal with the voltage of a capacitor configured between the gate and the input signal. By sharing at least some components among multiple sample and hold circuits, the number of gates driven by clock signals is reduced, reducing clock distribution and calibration complexity, and the circuit area is reduced.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: July 26, 2016
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Daniele Mastantuono, Mattias Palm, Roland Strandberg
  • Patent number: 9378844
    Abstract: Electric charge is stored, in accordance with a bias voltage, in a gate of a transistor performing switching operation between an input terminal and an output terminal, and the gate is brought into an electrically floating state at the time of completing the storage of electric charge in the gate. One electrode of a capacitor is connected to the gate in an electrically floating state, and the potential of the other electrode of the capacitor is increased, so that the voltage of the gate is increased using capacitive coupling. The potential of the gate of the transistor is increased, and the bias voltage is sampled without being decreased. Each of the transistor performing switching operation and a transistor connected to the gate of the transistor is a transistor with an extremely low off-state current.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: June 28, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kei Takahashi
  • Patent number: 9325312
    Abstract: An input control circuit that can be used to drive analog switches of analog modules such as an analog-to-digital converter (ADC) enables a sampling switch to receive a higher input voltage than the voltage rating of the devices comprising the sampling switch without risk of damage and without the need for a resistor divider network. The input control circuit and switch both receive an input voltage to be processed and the input control circuit generates a control signal for the switch that is derived from a pre-charged capacitor. The control circuit permits the design and manufacture of high voltage analog modules using low voltage devices, which can save on mask costs without any performance trade-offs.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: April 26, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Mayank Jain, Sanjoy K. Dey
  • Patent number: 9287002
    Abstract: A sampling circuit may include a sampling capacitance, an electronic sampling switch, and a switch controller. The electronic sampling switch may have a control input that controls whether the electronic sampling switch is in a sample state or a hold state. The electronic sampling switch may connect the sampling capacitance to an input signal while in the sample state and disconnect the sampling capacitance from the input signal while in the hold state. The switch controller may control the control input to the electronic sampling switch so as to cause the electronic sampling switch to be in the sample state during one period and the hold state during another period. While in the sample state, the switch controller may cause the impedance of the electronic sampling switch that is seen by the input signal to be substantially independent of the voltage of the input signal.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: March 15, 2016
    Assignee: LINEAR TECHNOLOGY CORPORATION
    Inventor: David M. Thomas
  • Patent number: 9247172
    Abstract: A solid state image sensor includes a pixel array, as well as charge-to-voltage converters, reset gates, and amplifiers each shared by a plurality of pixels in the array. The voltage level of the reset gate power supply is set higher than the voltage level of the amplifier power supply. Additionally, charge overflowing from photodetectors in the pixels may be discarded into the charge-to-voltage converters. The image sensor may also include a row scanner configured such that, while scanning a row in the pixel array to read out signals therefrom, the row scanner resets the charge in the photodetectors of the pixels sharing a charge-to-voltage converter with pixels on the readout row. The charge reset is conducted simultaneously with or prior to reading out the signals from the pixels on the readout row.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: January 26, 2016
    Assignee: Sony Corporation
    Inventors: Takeshi Yanagita, Keiji Mabuchi, Hiroaki Ishiwata
  • Patent number: 9218513
    Abstract: A switching circuit is linearized by using a capacitor to apply a drive voltage to an FET, wherein the drive voltage is independent of the signal switched by the switching circuit.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 22, 2015
    Assignee: Sequans Communications
    Inventors: Thomas Winiecki, Olujide Adeyemi Adeniran
  • Patent number: 9152497
    Abstract: A storage module may include a NAND-type flash memory array and one or more controllers configured to increase gate bias voltage levels applied to gates in the memory array to overcome possible gate shorts and recover data identified as being uncorrectable. The increased gate bias voltages may be applied to gates of a single type of transistor or to different types of transistors in the memory array, including drain select transistors, source select transistors, or floating gate transistors.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: October 6, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Dana Lee, Abhijeet Manohar
  • Patent number: 9093232
    Abstract: An electronic switch may include transfer transistor having a first conduction terminal for receiving an input signal, a second conduction terminal, and a control terminal. The transfer transistor may enable/disable a transfer of the input signal from the first conduction terminal to the second conduction terminal according to a control signal. The control signal may take a first value and a second value different from the first value, a difference between the first value and the second value defining, in absolute value, an operative value of the control signal. The electronic switch may further comprise a driving circuit for receiving the input signal and the control signal, and for providing a driving signal equal to the sum between the input signal and the operative value of the control signal to the control terminal of the transfer transistor.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: July 28, 2015
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Enrico Castaldo, Antonino Conte, SantiNunzioAntonino Pagano, Stefania Rinaldi
  • Patent number: 9024558
    Abstract: A bridge output circuit includes an output terminal, a high side transistor, a low side transistor, a high side driver for controlling a gate voltage of the high side transistor, a low side driver for controlling a gate voltage of the low side transistor, and a controller for controlling the high side and low side drivers. The low side driver includes a first current source, a second current source, and a first assist circuit. The controller is configured to control the turning-on and turning-off states of the first current source, the second current source and the first assist circuit.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: May 5, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Hisashi Sugie
  • Patent number: 9019000
    Abstract: A driver circuit for a semiconductor switching device includes a drive power source, a capacitor and four switches, which form a bridge circuit. The capacitor is provided between the four switches. In one cycle of application of a voltage to a gate of the semiconductor switching device to turn on the semiconductor switch, the first and the second switches, which are diagonal, are turned off and the third and the fourth switches, which are diagonal, are turned on to charge the capacitor. Then only the first switch is turned on to apply the voltage to the gate, and lastly only the second switch is turned on to discharge the capacitor thereby to apply a negative voltage to the gate of the semiconductor switching device.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: April 28, 2015
    Assignee: DENSO CORPORATION
    Inventor: Kazuhiro Umetani
  • Publication number: 20150109161
    Abstract: A bootstrapped switch circuit capable of operating at input signals from far below the negative supply rail to far beyond the positive supply rail may include (a) a switch having a first terminal coupled to an input terminal, a second terminal coupled to an output terminal, and a control terminal; (b) a charge pump coupled to one or more clock signals and isolated from a timing circuit via a first capacitor and a second capacitor, the charge pump generating an output voltage; and (c) a logic circuit coupled to one or more clock signals and isolated from the timing control circuit via a third capacitor and a fourth capacitor, wherein the logic circuit provides a control signal to the control terminal of the switch that is derived from the output voltage of the charge pump.
    Type: Application
    Filed: January 16, 2014
    Publication date: April 23, 2015
    Applicant: Linear Technology Corporation
    Inventor: Gerd TRAMPITSCH
  • Patent number: 8994439
    Abstract: A semiconductor device which has reduced power consumption and includes a selection transistor is provided. A semiconductor device in which the number of wirings and terminals for inputting a power supply potential is reduced and which operates at high speed is provided. A buffer circuit connected to a gate line connected to a gate of the selection transistor has a function of generating a potential higher than a high power supply potential by using the high power supply potential and outputs the potential depending on the selection signal. A bootstrap circuit boosts a high power supply potential that is input to an inverter that is the closest to an output side among a plurality of inverters included in a buffer circuit. Further, by providing a delay circuit in the buffer circuit, the bootstrap circuit starts to boost a potential at the timing later than the input of the selection signal.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Makoto Kaneyasu, Kouhei Toyotaka
  • Patent number: 8981843
    Abstract: This document discusses, among other things, a control circuit, such as a translator circuit, configured to reduce voltage stress of first and second transistors when a first voltage received by the first transistor exceeds a voltage rating of at least one of the first or second transistors.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 17, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Nickole Gagne, Kenneth P. Snowdon
  • Publication number: 20150042547
    Abstract: A gate driver, including multiple stages of gate driving circuits, wherein each stage of the gate driving circuits includes an input part configured to generate a Q node signal in response to a carry signal of one of previous stages and a clock signal, the Q node signal being applied to Q node, an output part configured to output a gate output signal to a gate output terminal in response to the Q node signal, and a charge sharing part connected to the gate output terminal of a present stage and a gate output terminal of one of next stages, the charge sharing part configured to operate charge-sharing between the gate output signal of the present stage and a gate output signal of one of the next stages in response to a select signal.
    Type: Application
    Filed: June 23, 2014
    Publication date: February 12, 2015
    Inventors: Oh-Kyong KWON, Yeong-Keun KWON, Jong-Hee KIM, Ji-Sun KIM, Jae-Keun LIM, Chong-Chul CHAI
  • Patent number: 8907701
    Abstract: The present invention discloses a CMOS differential logic circuit. The CMOS differential logic circuit includes a precharge differential logic unit, which is precharged to a source voltage in response to a clock signal and is configured to output voltage having an increased load-driving ability using a boosting voltage; a voltage-boosting unit, which is pulled down by a ground voltage in response to the clock signal and is configured to boost the pulled-down voltage using capacitive coupling and output the boosting voltage; and a switching unit, which is configured to couple the precharge differential logic unit and the voltage-boosting unit in response to the clock signal. The propagation delay of a signal from the input terminal to the output terminal of a circuit in a low-source-voltage environment can be reduced, and the operating speed of the circuit and energy efficiency of the operation thereof can be improved.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: December 9, 2014
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Bai Sun Kong, Jong Woo Kim, Joo Seong Kim
  • Patent number: 8866652
    Abstract: An example apparatus, system, and method for sampling in an interleaved sampling circuit having multiple channels. In an embodiment, an input clock is used to synchronize the transitions of sampling clocks from a first to second voltage level, relative to one another. The sampling clocks are input to a sampling circuit. The input clock switches a common switch that pulls each sampling clock to the second voltage level through a common path on input clock transitions from a first to a second clock state. The transition from the first to a second voltage level of each sampling clock triggers a sample taken on one of the channels. The first voltage level may be boosted to drive switches on in the sampling circuit. Synchronizing transitions of the outputs through the common switch and common path reduces timing mismatch between the sampling clocks controlling the channels.
    Type: Grant
    Filed: August 24, 2013
    Date of Patent: October 21, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Lawrence A. Singer, Siddharth Devarajan
  • Publication number: 20140266395
    Abstract: A coupling apparatus having a first branch and a second branch is disclosed. The first branch generally comprises (A) a first switch group configured to connect an input signal to an output node through a first capacitor, and (B) second switch group configured to connect either (i) a second signal, or (ii) a ground voltage, to the output node through a second capacitor. The second branch generally comprises (A) a third switch group configured to connect the input signal to the output node through a third capacitor, and (B) a fourth switch group configured to connect either (i) the second signal, or (ii) the ground voltage, to the output node through a fourth capacitor.
    Type: Application
    Filed: May 6, 2013
    Publication date: September 18, 2014
    Applicant: LSI Corporation
    Inventor: LSI Corporation
  • Patent number: 8810303
    Abstract: A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: August 19, 2014
    Assignee: Dialog Semiconductor GmbH
    Inventors: Michael Brauer, Stephan Drebinger
  • Patent number: 8786002
    Abstract: In terms of achieving a reduction in the cost of an antenna switch, there is provided a technology capable of minimizing harmonic distortion generated in the antenna switch even when the antenna switch is particularly formed of field effect transistors formed over a silicon substrate. Between the source region and the drain region of each of a plurality of MISFETs coupled in series, a distortion compensating capacitance circuit is coupled which has a voltage dependency such that, in either of the cases where a positive voltage is applied to the drain region based on the potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, the capacitance decreases to a value smaller than that in a state where the potential of the source region and the potential of the drain region are at the same level.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: July 22, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Masao Kondo, Masatoshi Morikawa, Satoshi Goto
  • Patent number: 8749022
    Abstract: A capacitor device includes a substrate including a first well having a first conductivity type and a first voltage applied thereto and a second well having a second conductivity type and a second voltage applied thereto; and a gate electrode disposed on an upper portion of the first well or an upper portion of the second well in such a way that the gate electrode is insulated from the first well or the second well, wherein capacitances of the capacitor device include a first capacitance between the first well and the second well and a second capacitance between the first well or the second well and the gate electrode.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Ryul Chang, Hwa-Sook Shin
  • Patent number: 8664979
    Abstract: Various exemplary embodiments relate to a tracking system and method. The system includes a transistor switch having a gate node and a source node, a power source circuit connected to the gate node, and a bootstrapping circuit connected to the source node and to the gate node. The power source circuit charges the switch during a first tracking phase, and the bootstrapping circuit charges the switch during a second tracking phase.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: March 4, 2014
    Assignee: NXP B.V.
    Inventors: Konstantinos Doris, Erwin Janssen, Anton Zanikopoulos, Alessandro Murroni
  • Patent number: 8653995
    Abstract: This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: February 18, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventor: Franz Kuttner
  • Patent number: 8624662
    Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: January 7, 2014
    Assignee: Transphorm Inc.
    Inventors: Primit Parikh, James Honea, Carl C. Blake, Jr., Robert Coffie, Yifeng Wu, Umesh Mishra
  • Patent number: 8604862
    Abstract: A bootstrapped switch circuit includes a first switch transistor to receive an input signal and a second switch transistor to provide an output signal. The sources of the switch transistors may be coupled. A voltage source may be coupled to the sources of the switch transistors and at least one of the gates of the switch transistors. The voltage source may generate a control voltage to activate at least one of the switch transistors based on a bias current. A voltage source driver may be coupled to the voltage source to generate the bias current based on a bias voltage. The bias voltage may include a first voltage approximately corresponding to an overdrive voltage of at least one of the switch transistors and a second voltage approximately corresponding to a threshold voltage of the switch transistors.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: December 10, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Christian Steffen Birk, Gerard Mora Puchalt
  • Patent number: 8587460
    Abstract: An A/D conversion apparatus includes first to M-th ADC connected in parallel converting an analog input signal to digital signals in response to M-phase sampling signals, a reference A/D conversion circuit that converts the analog input signal to a digital signal in response to a divided-by-(n×M+1) sampling signal; and a control unit that compares, for each period of (n×M+1) clock cycles, one of the digital signals from a corresponding one of first to M-th ADC with the digital signal from the reference ADC in a predetermined order of the first to M-th ADC, and generates a compensation control signal based on the comparison result for supply to the corresponding ADC.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: November 19, 2013
    Assignee: NEC Corporation
    Inventors: Hidemi Noguchi, Yasushi Amamiya
  • Patent number: 8575986
    Abstract: A level shift circuit includes an input port to which an input signal is input, a first signal amplifying unit configured to amplify the input signal input to the input port, a node at the first signal amplifying unit to output the amplified signal, a level shift input port to which a level shift voltage for controlling a DC level of the node is input, a first supply voltage configured to drive the first signal amplifying unit, and a level shift voltage generation circuit configured to generate the first supply voltage and the level shift voltage.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: November 5, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Hironori Sumitomo
  • Publication number: 20130278324
    Abstract: A semiconductor device which has reduced power consumption and includes a selection transistor is provided. A semiconductor device in which the number of wirings and terminals for inputting a power supply potential is reduced and which operates at high speed is provided. A buffer circuit connected to a gate line connected to a gate of the selection transistor has a function of generating a potential higher than a high power supply potential by using the high power supply potential and outputs the potential depending on the selection signal. A bootstrap circuit boosts a high power supply potential that is input to an inverter that is the closest to an output side among a plurality of inverters included in a buffer circuit. Further, by providing a delay circuit in the buffer circuit, the bootstrap circuit starts to boost a potential at the timing later than the input of the selection signal.
    Type: Application
    Filed: April 15, 2013
    Publication date: October 24, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Makoto KANEYASU, Kouhei TOYOTAKA
  • Patent number: 8536928
    Abstract: An integrated circuit (IC) comprises a transistor circuit and a voltage generator circuit. The voltage generator circuit is configured to generate an activation voltage for the transistor circuit using an output voltage at an output of the transistor circuit, and maintain a gate-source voltage (VGS) of the transistor circuit at a substantially constant voltage above the output voltage when a magnitude of the generated activation voltage is less than a device voltage rating of the IC and when the magnitude of the generated activation voltage meets or exceeds the device voltage rating of the IC.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: September 17, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Nickole Gagne, Jouni Mika Kalervo Vuorinen
  • Patent number: 8525574
    Abstract: In one embodiment, a bootstrap switch circuit has (i) a switch device that selectively provides a input signal as an output signal and bootstrap circuitry that provides a relatively high-voltage control signal to the gate of the switch device to turn on the switch device while preventing any over-voltage conditions from being applied to the switch device. The bootstrap circuitry includes a capacitor and a number of transistors configured as either switches or inverters. The circuit has two operating phases: one in which the capacitor gets charged while the switch device is turned off and the other in which the charged capacitor is isolated and used to generate the high-voltage control signal to be a fixed voltage difference above the current voltage level of the input signal applied to the switch device, thereby preventing an over-voltage condition.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: September 3, 2013
    Assignee: LSI Corporation
    Inventor: Abhishek Duggal
  • Patent number: 8502594
    Abstract: A switch circuit is described, where a switch to be controlled is formed of two NMOS transistors having their source terminals connected together and their gate terminals connected together. Their drain terminals are the input and output terminals of the switch. A driver circuit controls a bootstrap circuit that is formed of a latching circuit and a capacitor. When the switch is in an off state, the driver circuit connects the capacitor to a charging voltage source for charging the capacitor to a bootstrap voltage, and applies a non-zero voltage across the latching circuit. When the driver circuit is controlled to turn on the switch, the driver circuit disconnects the capacitor from the charging voltage source, and the latching circuit becomes conductive and effectively connects the capacitor across the gate and source terminals of the switch to turn it on with the bootstrap voltage. The bootstrap voltage across the capacitor maintains the latching circuit in a latched conductive state.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: August 6, 2013
    Assignee: Linear Technology Corporation
    Inventor: Jesper Steensgaard-Madsen
  • Publication number: 20130154715
    Abstract: Systems and methods are disclosed for operating a highly linearized resistance for a switch through use of a bootstrapped features. In one exemplary implementation, there is provided a method and system that implements a method for operating a circuit configured to provide a highly linearized resistance including receiving a signal via a bootstrapped switch, coupling the received signal to a gate if the received signal is high, receiving a signal via a switch control input coupled to a high impedance element. Moreover, the method includes coupling the high impedance element to the gate and turning off the switch via a gate turn off when the gate turn off pulls the gate low.
    Type: Application
    Filed: June 18, 2012
    Publication date: June 20, 2013
    Applicant: Supertex, Inc.
    Inventors: Benedict C.K. Choy, James T. Walker, Ming-Yuan Yeh
  • Patent number: 8461880
    Abstract: A pre-drive circuit with an output buffer that may contain a bootstrap circuit is described. The bootstrap circuit may be configured to output a voltage level greater in magnitude than the supply voltage that the bootstrap circuit is coupled with. The pre-drive circuit may contain a timing circuit. The timing circuit may be configured to at least partially determine when the bootstrap circuit outputs a voltage greater in magnitude than the supply voltage. The pre-drive circuit may also contain a pre-drive buffer circuit. This pre-drive buffer circuit may be capable of three outputs: (1) logical zero, or roughly electrical ground; (2) logical one, or roughly the level of the voltage supply, and (3) an outputted voltage greater than the voltage supply.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: June 11, 2013
    Assignee: Silicon Labs Spectra, Inc.
    Inventor: Huan Huu Tran
  • Patent number: 8325072
    Abstract: A digital-to-analog converter converts a digital input signal into an analog output signal. The digital-to-analog converter includes an input selector configured to input the digital input signal and an output terminal configured to output the analog signal. An array of current source cells is provided. Each current source cell includes a current source transistor having a gate terminal and a source terminal, a current source switch for coupling the source terminal to the output terminal based on the digital input signal, and a compensation capacitor configured to compensate a capacitive feedback between the gate terminal and the source terminal when the source terminal is coupled to the output terminal. At least one of the current source cells further includes a calibration circuit configured to detect a voltage variation at the gate terminal and provide a compensation voltage for the compensation capacitor.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: December 4, 2012
    Assignee: Intel Mobile Communications GmbH
    Inventor: Franz Kuttner