Abstract: A method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches is disclosed. A circuit arrangement configured to control a first NMOS switch is described. The arrangement comprises voltage provisioning means configured to supply a gate voltage to a gate terminal of the first NMOS switch; current provisioning means configured to provide a current; a first control stage configured to provide and/or remove a connection between the gate terminal of the first NMOS switch and the voltage provisioning means, thereby switching the first NMOS switch to an on-state and/or an off-state, respectively; and a first feedback control link between an output terminal of the first NMOS switch and the current provisioning means configured to control the slew-rate of a voltage at the first output terminal.

Abstract: In terms of achieving a reduction in the cost of an antenna switch, there is provided a technology capable of minimizing harmonic distortion generated in the antenna switch even when the antenna switch is particularly formed of field effect transistors formed over a silicon substrate. Between the source region and the drain region of each of a plurality of MISFETs coupled in series, a distortion compensating capacitance circuit is coupled which has a voltage dependency such that, in either of the cases where a positive voltage is applied to the drain region based on the potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, the capacitance decreases to a value smaller than that in a state where the potential of the source region and the potential of the drain region are at the same level.

Abstract: A capacitor device includes a substrate including a first well having a first conductivity type and a first voltage applied thereto and a second well having a second conductivity type and a second voltage applied thereto; and a gate electrode disposed on an upper portion of the first well or an upper portion of the second well in such a way that the gate electrode is insulated from the first well or the second well, wherein capacitances of the capacitor device include a first capacitance between the first well and the second well and a second capacitance between the first well or the second well and the gate electrode.

Abstract: Various exemplary embodiments relate to a tracking system and method. The system includes a transistor switch having a gate node and a source node, a power source circuit connected to the gate node, and a bootstrapping circuit connected to the source node and to the gate node. The power source circuit charges the switch during a first tracking phase, and the bootstrapping circuit charges the switch during a second tracking phase.

Abstract: This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit.

Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.

Abstract: A bootstrapped switch circuit includes a first switch transistor to receive an input signal and a second switch transistor to provide an output signal. The sources of the switch transistors may be coupled. A voltage source may be coupled to the sources of the switch transistors and at least one of the gates of the switch transistors. The voltage source may generate a control voltage to activate at least one of the switch transistors based on a bias current. A voltage source driver may be coupled to the voltage source to generate the bias current based on a bias voltage. The bias voltage may include a first voltage approximately corresponding to an overdrive voltage of at least one of the switch transistors and a second voltage approximately corresponding to a threshold voltage of the switch transistors.

Abstract: An A/D conversion apparatus includes first to M-th ADC connected in parallel converting an analog input signal to digital signals in response to M-phase sampling signals, a reference A/D conversion circuit that converts the analog input signal to a digital signal in response to a divided-by-(n×M+1) sampling signal; and a control unit that compares, for each period of (n×M+1) clock cycles, one of the digital signals from a corresponding one of first to M-th ADC with the digital signal from the reference ADC in a predetermined order of the first to M-th ADC, and generates a compensation control signal based on the comparison result for supply to the corresponding ADC.

Abstract: A level shift circuit includes an input port to which an input signal is input, a first signal amplifying unit configured to amplify the input signal input to the input port, a node at the first signal amplifying unit to output the amplified signal, a level shift input port to which a level shift voltage for controlling a DC level of the node is input, a first supply voltage configured to drive the first signal amplifying unit, and a level shift voltage generation circuit configured to generate the first supply voltage and the level shift voltage.

Abstract: A semiconductor device which has reduced power consumption and includes a selection transistor is provided. A semiconductor device in which the number of wirings and terminals for inputting a power supply potential is reduced and which operates at high speed is provided. A buffer circuit connected to a gate line connected to a gate of the selection transistor has a function of generating a potential higher than a high power supply potential by using the high power supply potential and outputs the potential depending on the selection signal. A bootstrap circuit boosts a high power supply potential that is input to an inverter that is the closest to an output side among a plurality of inverters included in a buffer circuit. Further, by providing a delay circuit in the buffer circuit, the bootstrap circuit starts to boost a potential at the timing later than the input of the selection signal.

Abstract: An integrated circuit (IC) comprises a transistor circuit and a voltage generator circuit. The voltage generator circuit is configured to generate an activation voltage for the transistor circuit using an output voltage at an output of the transistor circuit, and maintain a gate-source voltage (VGS) of the transistor circuit at a substantially constant voltage above the output voltage when a magnitude of the generated activation voltage is less than a device voltage rating of the IC and when the magnitude of the generated activation voltage meets or exceeds the device voltage rating of the IC.

Abstract: In one embodiment, a bootstrap switch circuit has (i) a switch device that selectively provides a input signal as an output signal and bootstrap circuitry that provides a relatively high-voltage control signal to the gate of the switch device to turn on the switch device while preventing any over-voltage conditions from being applied to the switch device. The bootstrap circuitry includes a capacitor and a number of transistors configured as either switches or inverters. The circuit has two operating phases: one in which the capacitor gets charged while the switch device is turned off and the other in which the charged capacitor is isolated and used to generate the high-voltage control signal to be a fixed voltage difference above the current voltage level of the input signal applied to the switch device, thereby preventing an over-voltage condition.

Abstract: A switch circuit is described, where a switch to be controlled is formed of two NMOS transistors having their source terminals connected together and their gate terminals connected together. Their drain terminals are the input and output terminals of the switch. A driver circuit controls a bootstrap circuit that is formed of a latching circuit and a capacitor. When the switch is in an off state, the driver circuit connects the capacitor to a charging voltage source for charging the capacitor to a bootstrap voltage, and applies a non-zero voltage across the latching circuit. When the driver circuit is controlled to turn on the switch, the driver circuit disconnects the capacitor from the charging voltage source, and the latching circuit becomes conductive and effectively connects the capacitor across the gate and source terminals of the switch to turn it on with the bootstrap voltage. The bootstrap voltage across the capacitor maintains the latching circuit in a latched conductive state.

Abstract: Systems and methods are disclosed for operating a highly linearized resistance for a switch through use of a bootstrapped features. In one exemplary implementation, there is provided a method and system that implements a method for operating a circuit configured to provide a highly linearized resistance including receiving a signal via a bootstrapped switch, coupling the received signal to a gate if the received signal is high, receiving a signal via a switch control input coupled to a high impedance element. Moreover, the method includes coupling the high impedance element to the gate and turning off the switch via a gate turn off when the gate turn off pulls the gate low.

Abstract: A pre-drive circuit with an output buffer that may contain a bootstrap circuit is described. The bootstrap circuit may be configured to output a voltage level greater in magnitude than the supply voltage that the bootstrap circuit is coupled with. The pre-drive circuit may contain a timing circuit. The timing circuit may be configured to at least partially determine when the bootstrap circuit outputs a voltage greater in magnitude than the supply voltage. The pre-drive circuit may also contain a pre-drive buffer circuit. This pre-drive buffer circuit may be capable of three outputs: (1) logical zero, or roughly electrical ground; (2) logical one, or roughly the level of the voltage supply, and (3) an outputted voltage greater than the voltage supply.

Abstract: A digital-to-analog converter converts a digital input signal into an analog output signal. The digital-to-analog converter includes an input selector configured to input the digital input signal and an output terminal configured to output the analog signal. An array of current source cells is provided. Each current source cell includes a current source transistor having a gate terminal and a source terminal, a current source switch for coupling the source terminal to the output terminal based on the digital input signal, and a compensation capacitor configured to compensate a capacitive feedback between the gate terminal and the source terminal when the source terminal is coupled to the output terminal. At least one of the current source cells further includes a calibration circuit configured to detect a voltage variation at the gate terminal and provide a compensation voltage for the compensation capacitor.

Abstract: A track-and-hold circuit includes a bootstrapped clock generator and a track-and-hold unit. The bootstrapped clock generator receives an input voltage signal and generates a sampling control signal having a voltage level lower than or equal to a level of a power supply voltage by maintaining an initial level of a boost capacitor voltage at a level lower than the level of the power supply voltage. The boost capacitor voltage is a voltage that is charged across a boost capacitor included in the bootstrapped clock generator and the sampling control signal is generated based on a clock signal. The track-and-hold unit samples and holds the input voltage signal in response to the sampling control signal to generate a sampled signal.

Abstract: There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance (205) is provided between a gate and a source of a TFT (203) connected to an output node, and a circuit formed of TFTs (201) and (202) has a function to bring a node ? into a floating state. When the node ? is in the floating state, a potential of the node ? is caused higher than VDD by using gate-source capacitance coupling of the TFT (203) through the capacitance (205), thus an output signal having an amplitude of VDD-GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

Abstract: A technique to implement a stable and high impedance current sink or source onto a display substrate using a single device. The high output current source or sink circuit includes an input that receives a fixed reference current and provides the reference current to a node in the current source or sink circuit during a calibration operation of the current source or sink circuit. The circuit further includes a first transistor and a second transistor series-connected to the node such that the reference current adjusts the voltage at the node to allow the reference current to pass through the series-connected transistors during the calibration operation. The circuit includes one or more storage devices connected to the node, and an output transistor connected to the node to source or sink an output current from current stored in the one or more storage devices to a drive an active matrix display with a bias current corresponding to the output current.

Abstract: A circuit for recovering charge at the gate of an output transistor arranged to drive the output of a switching circuit such as a switching regulator or controller. A substantial portion of the charge for each switching cycle is recovered under a wide range of load conditions for the switching circuit, e.g., no load, partial load, or full load. Also, charge recovery operates effectively with a switching circuit that is arranged to switch in a synchronous or asynchronous manner. Additionally, if the output voltage of a switching circuit is 12 or more volts, the amount of charge that can be saved can be relatively substantial.

Abstract: In accordance with an embodiment, a converter includes a circuit and method for charging a bootstrap capacitor. The circuit monitors a voltage across the bootstrap capacitor and enables charging the bootstrap capacitor in response to the voltage across the bootstrap capacitor being less than a threshold voltage.

Abstract: A bootstrap circuit comprises: a first transistor connecting a first power supply with an output node; and a second transistor applying a first input signal to a gate node of the first transistor and having a conductivity type identical to that of the first transistor. A second input signal obtained by inverting a level of the first input signal, delaying the inverted signal, and adding a direct current bias to the delayed signal is inputted to a gate node of the second transistor.

Abstract: A motor driver circuit for driving the gate node of a high-side driver transistor to a boosted voltage from a charge pump draws little or no static current from the charge pump. The gate node is pulled to the boosted voltage by a p-channel pullup-control transistor that is driven by p-channel transistors that are pumped by capacitors that cut off current flow to ground from the charge pump. An n-channel output-shorting transistor shorts the gate node to the output when the high-side driver is turned off. A coupling capacitor initializes the shorting transistor for each output transition. A p-channel output-sensing transistor generates a feedback to a second stage that drives the coupling capacitor. P-channel diode transistors and an n-channel equalizing transistor control the voltage on the coupling capacitor.

Abstract: A highly efficient rectifier can readily replace a two-terminal diode. Its conduction losses are reduced from that of the two-terminal diode. Connected between the source and drain of a MOSFET including a parasitic diode are a micro-power converter section for boosting a conduction voltage Vds between the source and drain to a predetermined voltage, and a self-drive control section that operates based on a voltage output from the micro-power converter section. When the source and drain are conductive with each other, the micro-power converter section generates, from the conduction voltage Vds, a power source voltage for the self-drive control section, and the self-drive control section (4) continues drive control of the MOSFET.

Abstract: A bootstrapped switch circuit can include at least one transistor, to receive an input signal and allow the input signal to pass through as an output signal based on a control signal, and a voltage-controlled voltage source, to provide first and second voltages between a gate and a source of the at least one transistor in response to the control signal. The voltage-controlled voltage source can include a differential pair and a current source. A gate of one of the differential pair can receive the control signal and a gate of the other of the differential pair can receive a logical inverse of the control signal. The current source can provide a current to connected sources of the differential pair. The first voltage can turn on the at least one transistor and be produced in response to a first logic state of the control signal resulting in the current of the current source flowing entirely through a first one of the differential pair.

Abstract: An integrated circuit allows for the correction of distortion at an input of a sampling network. The integrated circuit contains a first bootstrap circuit to drive a sampling network transistor and a second bootstrap circuit to separate the back-gate terminal of the transistor from a voltage input by a resistance inserted in series. The presence of the inserted resistance counteracts the effect of the nonlinear back-gate capacitance on the distortion at the input.

Abstract: An analog switch circuit that includes a first field-effect transistor, a source of which is coupled to a first switch terminal, and a drain of which is coupled to a second switch terminal; a first capacitance storing electric charge; a second capacitance storing electric charge; a first switch circuit that couples the first capacitance between a direct current voltage node and a reference potential node; a second switch circuit that couples the first capacitance and the second capacitance in parallel; and a third switch circuit that couples the second capacitance between a gate and the source of the first field-effect transistor.

Abstract: A ramp-up circuit for switched capacitor circuits with negative feedback to control the slew rate of in-rush current. Other embodiments are described and claimed.

Abstract: The invention relates to an apparatus and method for driving high-side switching devices in an H-Bridge circuit. The apparatus includes first and second N-Channel high-side switching devices. Each of the high-side switching devices is associated with, and is selectively driven by, a driver circuit. Each of the driver circuits is associated with, and is powered from, a bootstrap capacitor. The apparatus further includes a cross-couple circuit that is arranged to charge each of the bootstrap capacitors based, at least in part, on whether the low-side switching device that is associated with the other bootstrap capacitor is open or closed.

Abstract: The present invention relates to a circuit arrangement, which is used for controlling a high side CMOS transistor (M1) in a high voltage deep sub micron process. To provide a circuit arrangement for switching a high side CMOS transistor (M1) in a circuit having a very thin gate oxide, produced by a deep sub micron process, a circuit arrangement is proposed for controlling a high side CMOS transistor (M1), wherein the high side CMOS transistor (M1) is coupled between a high side voltage potential (Vbat) and a control output (OUT) for switching an external device, the high side CMOS transistor (M1) is controlled at its gate by a reference potential (Vbat-Vref), which is provided by a high side voltage reference (11) having a capacitor (C1), which is charged for switching on and discharged for switching off the high side CMOS transistor (M1).

Abstract: A switching circuit includes first and second transistors, and a driver circuit. The first transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode, and a control electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal, and a control electrode. The driver circuit has an input for receiving an input signal, and an output coupled to the control electrode of the first transistor. The driver circuit precharges the control electrode of the first transistor to a first predetermined voltage, and in response to the input signal transitioning from a first logic state to a second logic state, the driver circuit provides a second predetermined voltage to the control electrode of the first transistor to cause the first transistor to be conductive.

Abstract: An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.

Abstract: A high load driving device is disclosed. The driving device comprises an inverter receiving a digital voltage. The inverter reverses the digital voltage, and then sends out it. The output terminal of the inverter is coupled to a capacitor, a first P-type field-effect transistor (FET), a second P-type FET, a first N-type FET, and a third N-type FET. A push-up circuit is composed of these transistors and a second N-type FET and coupled to a P-type push-up FET. A load is coupled to a high voltage through the P-type push-up FET. When the digital voltage rises from a low level to a high level, the push-up circuit utilizes the original voltage drop of the capacitor to control the P-type push-up FET, whereby the gate voltage of the P-type push-up FET is at a low stabilization voltage that is lower than the ground potential. Then, the load is driven rapidly.

Abstract: A bootstrapped switch circuit can include a switch transistor, having a drain configured as an input terminal to receive an input signal, and a voltage-controlled voltage source, configured to provide predetermined constant voltages between a gate and a source of the switch transistor in response to a control signal received at a control terminal. The predetermined constant voltages can include a first predetermined constant voltage to turn on the switch transistor and pass the input signal to the source and a second predetermined constant voltage to turn off the switch transistor. The first and second predetermined constant voltages can be independent of the magnitude of a signal passed to the source of the switch transistor based on the input signal at the drain.

Abstract: This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit.

Abstract: Methods and apparatus for sampling an input voltage and apparatus incorporating the same are disclosed. An input voltage sampling apparatus includes a voltage sampling circuit coupled to the input voltage and configured to produce a sampled input voltage at an output terminal, and a voltage charging circuit coupled to the voltage sampling device and producing a first charged voltage on a first charged voltage output terminal and a second charged voltage on a second charged voltage output terminal. A voltage charging enabling circuit is coupled to the voltage charging circuit, the voltage sampling device via the first connection, and a power supply voltage. Further, the input voltage sampling apparatus includes a control circuit coupled to the voltage sampling circuit, the voltage charging circuit, and the power supply voltage, ground, third and fourth pulse signals. The first and third pulse signals are non-overlapping with the second and fourth pulse signals.

Abstract: The present invention relates to a switch driving circuit and a driving method thereof. The switch driving circuit according to the present invention is supplied with a first voltage and a second voltage, is driven by a voltage difference between the first and second voltages, controls a switching operation of a power switch according to a switch driving control signal, generates a sense voltage corresponding to the second voltage, compares a predetermined reference voltage with the sense voltage, and stops the switching operation of the power switch according to the comparison result.

Abstract: There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance (205) is provided between a gate and a source of a TFT (203) connected to an output node, and a circuit formed of TFTs (201) and (202) has a function to bring a node ? into a floating state. When the node ? is in the floating state, a potential of the node ? is caused higher than VDD by using gate-source capacitance coupling of the TFT (203) through the capacitance (205), thus an output signal having an amplitude of VDD-GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

Abstract: A track-and-hold circuit includes a bootstrapped clock generator and a track-and-hold unit. The bootstrapped clock generator receives an input voltage signal and generates a sampling control signal having a voltage level lower than or equal to a level of a power supply voltage by maintaining an initial level of a boost capacitor voltage at a level lower than the level of the power supply voltage. The boost capacitor voltage is a voltage that is charged across a boost capacitor included in the bootstrapped clock generator and the sampling control signal is generated based on a clock signal. The track-and-hold unit samples and holds the input voltage signal in response to the sampling control signal to generate a sampled signal.

Abstract: An image display system comprises a pixel driving circuit. A storage capacitor is coupled between the first and second nodes. The first switch is turned on in the first and second periods. The second switch, coupled to the first node, is turned on in the first and second periods. The third switch, coupled between the second node and the first switch, is turned on in the first, third and fourth periods. The fourth switch, coupled between the second switch and the first voltage, is turned on in the first, third and fourth periods. The fifth switch, coupled between the second node and the first voltage, is turned on in the first, second and third periods. The sixth switch, coupled between the first node and the reference voltage, is turned on in the fourth period. The first transistor is coupled between the first and second switches and is turned on in the fourth period. During the second period, the voltage between source and gate of the first transistor is a threshold voltage.

Abstract: In embodiments of the present invention a device, circuit, and method are described for sampling input signal voltages, which may include voltages below a negative supply voltage for the device or circuit, without requiring static current from the input. Various embodiments of the invention obviate the requirement of an external negative supply voltage or attenuation resistors to allow sampling between a positive and negative voltage range. These embodiments result in a lower power sampling solution as well as simplifying any driver circuitry required by the sampler. The embodiments of the invention may be applied to sampling processes within analog-to-digital converters and may also be applicable to various other types of circuits in which a sampling input having input voltages that are lower than its negative supply voltage.

Abstract: The present invention provides a semiconductor device having a buffer circuit formed on an insulating substrate using single-channel type thin film transistors, wherein the buffer circuit has an output stage which including first and second thin film transistors connected in series between first and second power sources, and the output terminal potential of the output stage is switched to the potential of the first or second power source in a complementary manner by the input timings of a set signal adapted to control the first thin film transistor and a reset signal adapted to control the second thin film transistor.

Abstract: One example of the invention relates to a circuit arrangement for actuating a high-side transistor which includes a control terminal and a load terminal. The circuit arrangement includes a driver circuit that is designed to generate, in response to a control signal, a driver signal for the control terminal of the high-side transistor. A supply circuit is capacitively coupled to a radio-frequency signal source and is designed to provide a supply voltage to the driver circuit, the supply voltage being referenced to a floating reference potential.

Abstract: An amplifier/buffer composed from circuit elements of a single threshold and single conductivity type, comprising an input stage for receiving one or more inputs for buffering/amplification and providing an intermediate to control output of the amplifier/buffer. The intermediate signal is provided to a boosting circuit configured to boosts said signal when said signal has exceeded a predetermined value. The amplifier/buffer further has an output stage for receiving at least said signal and providing an amplified/buffered output.

Abstract: The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because latching-up is reduced when the supply voltage is applied to the CMOS circuit or when the supply voltage is cut off, and subthreshold current is decreased during normal operation.

Abstract: A clock control circuit is provided. The clock control circuit includes a voltage supplier for supplying a first voltage in response to a first clock signal, a voltage booster for boosting the first voltage in response to the first clock signal input to the voltage booster, and a clock generator for generating a second clock signal having a voltage level equal to the boosted first voltage in response to the first clock signal.

Abstract: A driver circuit comprising an insulated gate bipolar transistor having a collector coupled to a voltage supply, an emitter coupled to a source of reference potential, and a gate configured to receive a control signal from a driver circuit, and a desaturation circuit conductively coupled between an insulated gate and a collector of the insulated gate bipolar transistor to desaturate the insulated gate. The desaturation circuit includes a series coupled bias voltage source, uni-directionally conducting element and switch.

Abstract: A clock generation circuit has two output ends to provide a first clock signal and a second clock signal, in response to first and second input signals, respectively. A charge storage component is used to transfer some charge from the first output end to the charge storage component when the first clock signal is high for a period of time, and to transfer the charge from the charge storage component to the second output end when the second clock signal is low. At a different period of time in the clock cycle, the charge storage component is used to transfer some charge from the second output end to the charge storage component when the second clock signal is high for a period of time, and to transfer the charge from the charge storage component to the first output end when the first clock signal is low.

Abstract: A switch circuit is described, where a switch to be controlled is formed of two NMOS transistors having their source terminals connected together and their gate terminals connected together. Their drain terminals are the input and output terminals of the switch. A driver circuit controls a bootstrap circuit that is formed of a latching circuit and a capacitor. When the switch is in an off state, the driver circuit connects the capacitor to a charging voltage source for charging the capacitor to a bootstrap voltage, and applies a non-zero voltage across the latching circuit. When the driver circuit is controlled to turn on the switch, the driver circuit disconnects the capacitor from the charging voltage source, and the latching circuit becomes conductive and effectively connects the capacitor across the gate and source terminals of the switch to turn it on with the bootstrap voltage. The bootstrap voltage across the capacitor maintains the latching circuit in a latched conductive state.

Abstract: The present invention discloses an output circuit that is able to adjust the output voltage slew rate and avoid short-circuit current, comprising: a control circuit for receiving an input data and generating a first set of control signals based on the input data; an output control device consisting of a first field effect transistor (FET) connected in series with a second field effect transistor (FET) and the point of connection is the output end for generating an output signal; a first capacitor having one end connected to a first working voltage and generates a first control voltage by charging/discharging on another end to control the gate of the first field effect transistor; a first switch for controlling charging/discharging of the first capacitor device based on the first set of control signals; a first current source for providing charging current for the first capacitor device; a second capacitor having one end connected to a second working voltage and generates a second control voltage by charging/d