Abstract: The signal transmission circuit comprises a first switch controls output according to a first control pulse, the first source follower outputting signals to the first output line based on signal input into the gate, a first capacitor connected between the gate and the source of the source follower, the first circuit, based on a level of the input signal, fixing the first output line to reference potential, the second switch controlling output according to a second control pulse, the second source follower, according to signals input into the gate, supplying output signals to the subsequent stage and also to a second output line, a second capacitor connected between the gate and the source of the source follower, and the second circuit, based on a level of input signals from the source, fixing the second output line to reference potential.

Abstract: According to some embodiments, provided are a static low-swing driver circuit to receive a full-swing input signal, to convert the full-swing input signal to a low-swing signal, and to transmit the low-swing signal, and a dynamic receiver circuit to receive the low-swing signal and to convert the low-swing signal to a full-swing signal. Also provided may be an interconnect coupled to the driver circuit and to the receiver circuit, the interconnect not comprising a repeater and to receive the low-swing signal from the driver circuit and to transmit the low-swing signal to the receiver circuit.

Abstract: The level shift circuit in the semiconductor circuit of the invention has a configuration comprising an input stage inverter circuit which inputs an input signal having a first voltage amplitude and outputs an inverted signal of this input signal, an output stage inverter circuit which inputs at least the output signal of the input stage inverter circuit and the output signal has a second voltage amplitude larger than the first voltage amplitude and a bootstrap circuit section which boosts a voltage value of input signal voltage of the output stage inverter circuit and the potential difference of the input signal and the output signal is held as a voltage component. The level shift circuit of each circuit is a Thin-Film Transistor at least using a semiconductor layer composed of amorphous silicon having single channel polarity as a switching element.

Abstract: A bootstrapping circuit capable of sampling inputs beyond a supply voltage which includes a bootstrapped switch coupled between an input node and an output node, a first transistor having a first end coupled to a control node of the bootstrapped switch, a first capacitor having a first end coupled to a second end of the first transistor, a second transistor coupled between the first end of the first transistor and a supply node, and having a control node coupled to a first clock signal node, a third transistor coupled between the second end of the first transistor and the supply node, a charge pump having an output coupled to a control node of the third transistor, a level shifter having an output coupled to a second end of the first capacitor, a fourth transistor cross-coupled with, the first transistor, a fifth transistor having a second end coupled to the first end of the fourth transistor, and having a control node coupled to the output of the level shifter, and a sixth transistor coupled between the firs

Abstract: Provided is concerned with a high voltage switch circuit for a semiconductor device, which rapidly discharges a gate voltage of a pass transistor through an additional discharge transistor during inactivation of itself in the circuit structure with a positive feedback loop for transferring an internal high voltage without a voltage drop by applying an enough voltage to the gate of the pass transistor. The high voltage switch circuit prevents the internal high voltage from decreasing.

Abstract: A boost circuit capable of boosting a reference voltage into an output voltage. The boost circuit includes a main transistor electrically connected to the output voltage, an auxiliary transistor electrically connected to the output voltage, a pre-charge circuit electrically connected to the main transistor and the auxiliary transistor for pre-charging the main transistor and the auxiliary transistor, and a voltage detector electrically connected to the auxiliary transistor and the reference voltage for controlling the auxiliary transistor according to the reference voltage.

Abstract: In one embodiment, a power MOSFET driver uses two different voltages for the operating voltage of the two output drivers of the power MOSFET driver.

Abstract: A circuit with a large load driving capability, which is structured by single polarity TFTs, is provided. With a capacitor (154) formed between a gate electrode and an output electrode of a TFT (152), the electric potential of the gate electrode of the TFT (152) is increased by a boot strap and normal output with respect to an input signal is obtained without amplitude attenuation of an output signal due to the TFT threshold value. In addition, a capacitor (155) formed between a gate electrode and an output electrode of a TFT (153) compensates for increasing the electric potential of the gate electrode of the TFT (152), and a larger load driving capability is obtained.

Abstract: A first bias voltage to be applied to a drain portion of a MOS transistor and a pulse voltage pulsating with a predetermined potential difference are being generated by an apparatus incorporating the MOS transistor. Voltage generation means generates a second bias voltage to be applied to a gate portion of the MOS transistor, based on a value of the predetermined potential difference of the pulse voltage generated in the apparatus incorporating the MOS transistor, a value of the first bias voltage generated in the apparatus incorporating the MOS transistor, and a channel potential of a channel portion provided beneath the gate portion of the MOS transistor. Superposition means generate a voltage to be applied to the gate portion of the MOS transistor by superposing the pulse voltage onto the second bias voltage generated by the voltage generation means.

Abstract: A signal transmission gate includes a switch such as a transistor. The switch includes a gate terminal adapted to receive a control voltage, and a source terminal and a drain terminal. One of the source and drain terminals is adapted to receive an input signal, and the output signal is provided on the other terminal. A constant-voltage boosting circuit generates the control voltage such that it has a substantially constant value above a voltage of the input signal. In one embodiment, the constant-voltage boosting circuit is coupled between the gate terminal and the terminal that receives the input voltage, and generates a substantially constant voltage difference. In one implementation, a component is employed that exhibits a characteristic voltage behavior, such as a diode, for generating the substantially constant voltage difference.

Abstract: The present invention discloses a high voltage switch circuit of a semiconductor device which can reduce a discharge time by supplying a higher voltage than a power voltage to a gate terminal of a discharge transistor in a discharge unit for discharging a high voltage.

Abstract: A power supply reset boosting element which boosts a level of the reset voltage to a level higher than the level of the power supply. The boosted voltage is isolated from both the power supply and from undesired switching by special transistors which can withstand the voltage power supply level.

Abstract: Switched level-shift circuit (SLSC) for a signal-switch (1) which is provided for switching an applied analog input signal (VAIN), wherein the switched level-shift circuit (5) comprises an input terminal (13) for the analog input signal applied to the signal-switch (1), a control input terminal (18) for a control signal (SW), an analog level-shift circuit (15) which adds a constant voltage to the analog input signal (VAIN) to generate a level-shifted analog output signal when the control signal (SW) is in a first logical state (high); and an output terminal (4) for the generated level-shifted analog output signal which is connected to a gate terminal (2) of said signal-switch (1).

Abstract: Circuit arrangement for voltage regulation having a differential amplifier having first and second inputs and first and second outputs, wherein a reference voltage is applied to the first input and a voltage to be regulated is applied to the second input. A charge pump is connected to the first output of the differential amplifier. A current mirror is connected to the second output of the differential amplifier. A transistor, which influences the voltage to be regulated, has its control input connected to the current mirror and the charge pump.

Abstract: The present invention discloses a high voltage switch circuit of a semiconductor device which can efficiently switch a high voltage over about 20V required in a flash memory even in a low voltage below about 1.4V by reducing increase of a threshold voltage by a back bias, facilitate development of a low voltage memory device, and reduce an area of a pumping capacitor.

Abstract: A device for driving a memory cell (601) of a memory module which can be operated with an external voltage (VEXT) and an operating frequency (fCLK), whereas the memory cell (601) has a capacitance (600) for storing charges and a transistor (602) for reading charges from the capacitance (600) and for writing charges to the capacitance (600), which transistor can be controlled with a control voltage (VPP), which has a charge store (614) for supplying a control voltage (VPP) which is greater than the external voltage (VEXT). The charge store (614) being able to be charged by the external voltage (VEXT), and the charging of the charge store (614) is able to be controlled by a charging control frequency (fCC) derived from the operating frequency (fCLK) of the memory module.

Abstract: An input circuit for an integrated circuit device may include a boosting circuit, a protection circuit, and a buffer circuit. The boosting circuit is configured to receive a supply voltage of the integrated circuit device and to generate a boosted voltage higher than the supply voltage. The protection circuit is configured to receive an input signal and the boosted voltage and to generate an output signal that changes responsive to changes in the input signal. The buffer circuit is configured to generate a buffered output signal responsive to the output signal generated by the protection circuit. Related methods are also discussed.

Abstract: Methods and apparatus provide for front-end processing of a first differential output current, whereby a first differential output current is received and a second differential output current having reduced spurious content is produced. Current steering is used to divide, and reassemble, the first differential output current so as to provide an output signal with reduced spurious content. Current steering is implemented by a return-to-zero circuit that is coupled to the terminals of a first differential current output stage. During a first phase, the return-to-zero circuit provides a differential output current equal to the first differential current output. During a second phase, the return-to-zero circuit provides a differential output current equal to zero. The current steering return-to-zero circuit is implemented with MOSFETs or any other suitable electrical circuit element that provides the ability to controllably pass or refrain from passing current.

Abstract: There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance (205) is provided between a gate and a source of a TFT (203) connected to an output node, and a circuit formed of TFTs (201) and (202) has a function to bring a node a into a floating state. When the node ? is in the floating state, a potential of the node a is caused higher than VDD by using gate-source capacitance coupling of the TFT (203) through the capacitance (205), thus an output signal having an amplitude of VDD-GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

Abstract: A low distortion, high frequency switch circuit for selectively coupling an input voltage terminal to an output voltage terminal includes a switching device coupled to the input voltage terminal and the output voltage terminal, a charge storage device, and a first, second and third switches. While the switch circuit is turned off, the charge storage device, typically a capacitor, is charged to a precharge voltage. Then, when the switch circuit is to be turned on, the charge storage device is coupled between the control terminal of the switching device and the input voltage terminal. As a result, the switching device receives a constant gate-to-source voltage approximately equals to the precharge voltage and becomes conductive with a minimum and constant RON for all values of input voltages. In another embodiment, the switch circuit includes a pedestal voltage compensation circuit for reducing charge injection induced pedestal errors.

Abstract: An isolation circuit for coupling a large programming voltage from an external terminal to a circuit ground node includes an NMOS isolation transistor through which the programming voltage is coupled, and a charge pump that applies a voltage having at least the magnitude of the programming voltage to the gate of the NMOS transistor. As a result, the NMOS transistor is able to pass the full magnitude of the programming voltage to the circuit ground node. The charge pump can generate a voltage having a sufficient magnitude with only a single charge pump stage because the charge pump uses the relatively large programming voltage as the starting point for the voltage boosting process.

Abstract: An integrated circuit driver is disclosed. The driver comprises a high side transistor and a low side transistor connected in series. The output of the driver is taken from the source of the high side transistor and the drain of the low side transistor. A bootstrap contact pad is connected to the output node. Connected to the bootstrap contact pad is a bootstrap capacitor that is also connected to a high side gate drive that selectively controls the high side transistor.

Abstract: An integrated circuit device is discussed that includes a data output driver having two modes of operation for driving a data bus. The output driver includes a circuit to produce a full drive output high signal, a partial drive output high signal, a full drive output low signal and a partial drive output low signal. The output driver is protected against negative voltages on the data bus. The output driver is selectable and adaptable to drive terminated loads and unterminated loads.

Abstract: A buffer circuit is used to convert signals of a first preselected voltage level to a second preselected voltage level. A pass gate transistor has a gate, source, and drain and is adapted to receive the signals of the first preselected voltage level, and deliver the signals of the second preselected voltage level. A capacitor is coupled across the source and drain of the pass gate transistor. A resistive element is coupled between the gate of the pass gate transistor and a voltage supply. The resistive element cooperates with a parasitic capacitance located between the gate and source of the pass gate transistor to form a pump that reacts to a low-to-high transition in the input signal to temporarily increase the voltage level applied to the gate of the pass gate transistor. This temporarily increased voltage level causes the voltage level output from the pass gate transition to track the transition in the input signal more closely.

Abstract: A level shifter includes first and second P type thin film transistors (TFTs) and first and second N type TFTs for latching levels of first and second output nodes, third and fourth N type TFTs for setting levels of the first and second output nodes, and first and second resistance elements and first and second capacitors for applying, between the gate-source of the third and fourth N type TFTs, a voltage higher than a voltage of an input signal, in response to rising and falling edges of the input signal respectively.

Abstract: A power switching circuit comprising a power semiconductor switching device, a charge pump circuit having a control input to control whether it is on or off and a charge pump output, the charge pump output being coupled to a control terminal of the power semiconductor switching device, a bootstrap power supply for supplying power to driver circuitry for the power semiconductor switching device, the bootstrap power supply comprising a bootstrap capacitor coupled to a charging current source, the bootstrap power supply providing power to the driver circuitry when the power semiconductor switching device is being switched by the driver circuitry in a pulsed mode, and the charge pump supplying a control voltage to turn on the power semiconductor switching device and maintain it on when the power switching semiconductor device is to be maintained on continuously.

Abstract: The amplitude expansion circuit as a main part of a drive circuit includes: a VM DC power supply line to which a voltage VM is applied; a VH DC power supply line to which a voltage VH roughly twice as high as the voltage VM is applied; an inverter circuit receiving a pulse signal oscillating between the ground voltage and the voltage VM; another inverter circuit receiving a pulse signal oscillating between the voltage VM and the voltage VH in correspondence with the oscillation of the voltage level of the above pulse signal; a p-channel MOSFET having a gate receiving an output from the inverter circuit; another p-channel MOSFET having a gate connected to the VM DC power supply line; an n-channel MOSFET having a gate connected to the VM DC power supply line; and another n-channel MOSFET having a gate receiving an output from the other inverter circuit. A common connection node of the p-channel MOSFET and the n-channel MOSFET works as the output terminal of the amplitude expansion circuit.

Abstract: In a circuit having two input stages multiplexed to a common output stage having an output, one of the two input stages including transistor having a base, a collector and an emitter; a method of protecting the transistor from ?-degradation when the one of the two input stages is disabled comprises: clamping the base to a substantially fixed voltage for a first range of voltages applied to the one of the two input stages; and bootstrapping the base to a voltage that follows the output for a second range of voltages applied to the one of the two input stages. Alternatively, a method of protecting a transistor having a base connected through a finite impedance to an input voltage, a collector and an emitter, may comprise bootstrapping the base to a voltage that follows the input voltage with an offset when the input voltage is within a second range of voltages.

Abstract: The high-side transistor driver according to the present invention includes a high-side transistor, a low-side transistor, a drive-buffer and an on/off transistor. When the low-side transistor is turned on, a charge-pump diode and a bootstrap capacitor produce a floating voltage. The drive-buffer will propagate the floating voltage to switch on the high-side transistor. The on/off transistor is used to switch the drive-buffer. The high-side transistor drive further includes a speed-up circuit. The speed-up circuit has a capacitive coupling for generating a differential signal. When the on/off transistor is turned off, the speed-up circuit accelerates the charge-up of the parasitic capacitor of the on/off transistor, thus accelerating high-side transistor switching.

Abstract: An isolation circuit for coupling a large programming voltage from an external terminal to a circuit ground node includes an NMOS isolation transistor through which the programming voltage is coupled, and a charge pump that applies a voltage having at least the magnitude of the programming voltage to the gate of the NMOS transistor. As a result, the NMOS transistor is able to pass the full magnitude of the programming voltage to the circuit ground node. The charge pump can generate a voltage having a sufficient magnitude with only a single charge pump stage because the charge pump uses the relatively large programming voltage as the starting point for the voltage boosting process.

Abstract: A multi-stage circuit has a first stage and a second stage that both share a bootstrap module. More specifically, the first stage has an output switch, and the second stage has an input switch in communication with the output switch. The multi-stage circuit thus includes the bootstrap module in communication with both the output switch and the input switch. The bootstrap module is capable of applying a voltage to both the input and output switches, while the applied voltage ensures that the first and second switches remain in an on state at specified times.

Abstract: A level translator circuit for use between a lower voltage potential circuit and a higher voltage potential circuit is disclosed. The translator circuit comprises a first transistor coupled to the lower voltage potential circuit and a bootstrap mechanism coupled to the first transistor. The circuit includes a second transistor coupled to the first transistor, a higher voltage potential and the higher voltage potential circuit, and a third transistor coupled to the higher voltage potential circuit, the higher voltage potential and the second transistor. Finally, the circuit includes a fourth transistor coupled to the higher voltage potential circuit, the third transistor and the lower voltage potential circuit. The bootstrap mechanism allows for the dynamic modulation of the first transistor to maximize translation speed and to minimize power consumption.

Abstract: Disclosed is a method of the present invention relates to a high voltage transfer circuit. The high voltage transfer circuit includes a first high voltage switch for transferring a high voltage generated within a chip to the outside of the chip according to a clock signal and a first control signal, and a second high voltage switch for transferring the high voltage generated outside the chip to the inside of the chip according to the clock signal and a second control signal. Therefore, it is possible to easily analyze fail of an initial product without manufacturing additional PMOS transistor that withstands a high voltage.

Abstract: A bootstrap circuit includes at least a chargeable semiconductor element region (D3, 6) and a drift region (Rn, 8) of a high-tension island, and junction between the chargeable semiconductor element region and the high-tension island drift region is isolated, and the high-tension island drift region has n+ layers (11, 12) provided at a high-tension side and at an opening portion in an n− semiconductor layer (106) of a high-tension island, and thus an ON operation of a parasitic transistor can be prevented to thereby reduce a current consumption of the circuits.

Abstract: Buffer that includes an input node, an output node, and a three-transistor charge pump circuit is coupled to the input node and the output node. The buffer generates an output signal that is a delayed version of a signal presented at the input node. The three-transistor charge pump includes a first transistor (e.g., a pass transistor) that includes a drain electrode that is coupled to the input node, a gate electrode and a source electrode; a second transistor that includes a drain electrode that is coupled to a first predetermined voltage, a gate electrode coupled to the drain electrode of the second transistor, and a source electrode coupled to the gate electrode of the first transistor; and a capacitive element that includes a first electrode that is coupled to the source electrode of the second transistor and the gate electrode of the first transistor and a second electrode that is coupled to the output node.

Abstract: The invention relates to a device for controlling the phases of a charge pump 20, which device includes a phase generator 9 and a charge pump that is provided with a plurality of stages 1, 2. The invention also relates to a driver circuit for driving a display device with a charge pump and a phase generator, and to a display device with a driver circuit and a charge pump and a phase generator. In order to enable optimum adjustment of the delays between the individual phases P1 to P4 for the control of a charge pump and also to enable a response to disturbances that are caused by changes of the load or the temperature, signals 14 to 17 are fed back from the charge pump to a phase generator 9 so that the phases are started only when the appropriate conditions or states of the other phases exist.

Abstract: A bootstrap circuit in DC/DC static converters is provided that includes a power transistor having a first non drivable terminal coupled with a first input voltage and driving means connected with a drivable terminal of the power transistor and adapted for determining the on time and the off time of the power transistor for each prefixed switching time period. The bootstrap circuit includes a capacitor coupled respectively with the second non drivable terminal of the power transistor and with a second input voltage and an input of the driving means so that the voltage between its terminals is substantially equal to the voltage between the second non drivable terminal and the drivable terminal during the off time of the power transistor. The bootstrap circuit includes an overcharge circuit arranged between the second non drivable terminal and ground; the overcharge circuit is able to allow overcharging the capacitor during the off time of the power transistor and for a time period lower than the off time.

Abstract: A circuit with a large load driving capability, which is structured by single polarity TFTs, is provided. With a capacitor (154) formed between a gate electrode and an output electrode of a TFT (152), the electric potential of the gate electrode of the TFT (152) is increased by a boot strap and normal output with respect to an input signal is obtained without amplitude attenuation of an output signal due to the TFT threshold value. In addition, a capacitor (155) formed between a gate electrode and an output electrode of a TFT (153) compensates for increasing the electric potential of the gate electrode of the TFT (152), and a larger load driving capability is obtained.

Abstract: A technique, for drawing power from the external signal circuit to power on-chip elements for an integrated circuit diode (ICD), utilizes an integrated diode and capacitor. The capacitor is charged by the external applied voltage during the time the ICD blocks the external current flow. The charged capacitor then acts as a battery to power the on-chip circuits to provide active control for the ICD function. This ICD could be provided as a two terminal discrete diode, or integrated onto a larger IC. This same technique can be utilized for a “self powered” MOSFET IC (ICM), utilizing a low power logic signal to trigger an internal circuit which would provide a much larger gate drive than the logic signal could provide. This could also be provided as discrete three terminal components, or integrated into a larger IC.

Abstract: Embodiments of the present invention relate to a voltage clamp circuit including a transistor and a switch. The switch is coupled between a gate of the transistor and a source or a drain of the transistor. Embodiments of the present invention can quickly raise and lower a voltage level supplied to a memory device.

Abstract: An analog switch circuit with superior breakdown voltage characteristics that can operate at a high speed at a low power supply voltage. The analog switch circuit includes a comparator circuit for inputting and comparing an analog input signal input to an analog switch section and a reference signal. If the input potential of the analog input signal is lower than the reference potential of the reference signal, a voltage boost circuit sets a potential of a gate of an n MOS transistor included in the analog switch section to a potential of positive power supply voltage. If the input potential of the analog input signal is higher than the reference potential of the reference signal, the voltage boost circuit boosts the potential of the gate to a potential higher than the potential of power supply voltage.

Abstract: A dual pump circuit including a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, each having a control terminal and a pair of current terminals coupled between a dual pump input and a dual pump output. The dual charge pump includes first and second pump circuits, where each pump circuit is coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors. Each pump circuit is operative to linearize operation of its corresponding transmission gate transistor by maintaining VGS—VT constant. The dual pump circuit is used in a track and hold circuit including at least one dual pump sampling circuit, at least one sampling capacitor, and a control circuit for controlling input signal sampling timing. Each dual pump sampling circuit includes the transmission gate and a dual charge pump.

Abstract: In a composite IC in which integrated are a power transistor, a bipolar analog circuit and a MOS logic circuit, a load-driving semiconductor device is provided which is capable of certainly placing the power transistor into an off-condition at power-on for stopping the driving of a load. In the semiconductor device, a high-side switch MOS transistor, a charge pump, a bipolar analog circuit, a charge pump driving CMOS logic circuit, a level conversion CMOS logic circuit and a forcibly stopping bipolar transistor 90 are made in the form of an IC, and the forcibly stopping bipolar transistor receives, through its base terminal, a signal which inverts when a drive voltage exceeds a predetermined value to turn to an on-condition. This operation places the bipolar analog circuit into a driving-stopped condition.

Abstract: A buffered bootstrapped input switch employs cancelled charge sharing for use in high performance sample and hold switched capacitor circuits especially useful for implementing, for example, an analog-to-digital converter (ADC) or amplifier circuit front end sampling network, among others. A scheme is employed for estimating the charge loss from the bootstrapping capacitor to the gate of the bootstrapped input switch, storing the estimated charge loss on a small capacitor, buffering the small capacitor, and then adding the estimated charge loss in series to the bootstrap capacitor, to provide an almost ideal bootstrap network.

Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.

Abstract: The invention utilizes a boost-strap method to improve switch operation in a design that is particularly advantageous for supplying high voltages within a low voltage design. A native NMOS transistor, a PMOS transistor, and a capacitor are connected in series between the high voltage source and the output, where the gate of the native NMOS is connect to the output. In an initialization phase, the plate of the capacitor connected to the output is precharged by receiving the input signal while the other plate of the capacitor is held near ground. In a subsequent enable phase, the native NMOS and PMOS transistors are turned on and the high voltage is supplied to the output.

Abstract: A voltage booster drives the gate of a bus-switch n-channel transistor to a theoretical maximum of triple the power-supply voltage Vcc. The gate node is first driven to Vcc. Then the back-side of a first capacitor is driven from ground to Vcc, coupling a first voltage boost to the gate node. After a Schmidt-trigger detects the back-side of the first capacitor near Vcc, the back-side of a second capacitor is driven from ground to Vcc. The front-side of the second capacitor is connected to the back-side of the first capacitor. A second voltage boost is coupled across the first and second capacitors to increase the voltage boost of the gate node to near triple Vcc rather than just double Vcc.

Abstract: Simple, inexpensive boost structures are realized with diode, switch and buffer circuits that operate in a charge mode and a boost mode to thereby generate a boost signal Sboost. The boost structures are especially suited for use in switched-capacitor systems.

Abstract: A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD.

Abstract: An amplifier system with on-demand power supply boost includes an amplifier circuit for receiving an input signal and a charge pump connected to positive and negative power supplies and having predetermined supply voltages and being responsive to the input signal for increasing beyond the predetermined supply voltages the supply voltage applied to the amplifier in response to an increase in the input signal and a tracking charge pump usable in the amplifier system which includes a charge storage device; a unidirectional isolation device interconnecting the charge storage device and one pole of a power supply; a driver circuit responsive to an input signal and interconnected between both poles of the power supply; the power supply having predetermined power supply voltages; and a bias circuit for biasing the driver circuit to charge the charge storage device in the charge mode and in the boost mode, for increasing beyond the predetermined power supply voltages, the supply voltage supplied by the storage device