Abstract: A series resonant circuit includes a series connected power source, inductor and capacitance. The resonant capacitance includes two separate capacitors, connected to form a voltage doubler. Two rectifiers clamp the resonant capacitors' voltage to the output voltage, so the voltage on the resonant capacitors is limited under overload conditions. Current control may be achieved by modulation of the power source frequency.

Abstract: In a level shift circuit, when a signal at a low voltage signal level applied at the signal input terminal changes from a LOW to a HIGH level, an inverter is boosted in input voltage level by a voltage booster on the basis of the voltage of a capacitor element charged through a diode element and on the basis of the input signal variation such that the inverter assumes an input voltage level above the aforesaid low voltage signal level. This enables the inverter to perform an inversion operation without fail and the signal output terminal provides a HIGH level signal at a high voltage. In addition, when the input signal changes from HIGH to LOW, an input of the inverter is pulled down directly by an N-channel transistor coupled to a ground power source to LOW. Accordingly, also in this case, the inverter performs an inversion operation without fail.

Abstract: A low-voltage constant-impedance analog switch based on a single MOSFET [328] as the main switching element. The constant-impedance on-state operation is obtained by connecting a charged capacitor [326] between the gate and source terminals of the MOSFET [328]. The switch can be compensated for the body effect, which may be necessary to obtain the required level of linearity. Low-voltage operation is made feasible by employing an internal feedback loop that locks in the switch's on-state. The switch can be implemented in a single-well CMOS bulk technology, and it can operate at supply-voltage differences that are only slightly higher than the technology's threshold voltage.

Abstract: The present invention relates to an output stage for an electronic memory device and for low supply-voltage applications and is the type comprising a final stage of the pull-up/pull-down type made up of a complementary pair of transistors inserted between a primary reference supply voltage and a secondary reference voltage and a voltage regulator for the control terminals of said transistors. The regulator is a voltage booster using at least one bootstrap capacitor to increase the current flowing in the final stage by boosting the voltage applied to said control terminals.

Abstract: A high performance driver circuit is described. The driver produces increased current flow at its output to decrease charging time. Increased current flow is achieved by providing an overdrive circuit that provides a voltage offset to increase the magnitude of the overdrive voltage.

Abstract: A logic circuit includes: a main switching means for changing conduction state between at least two terminals in accordance with a voltage supplied to a control terminal; and a voltage converting means for converting a voltage at an input terminal and outputting the converted voltage to the control terminal.

Abstract: A charge pump limits the voltages at nodes internal to the charge pump to reduce the risk of junction breakdown in the charge pump. The charge pump includes a first pump circuit, a second pump circuit, a first clamp and a second clamp. The first clamp limits the voltage level of a well by providing a current path from the well to the output lead when the voltage level of the well reaches a first predetermined limit. The voltage level at a node from which charge is redistributed to the well is limited by the second clamp, which is configured to provide a conductive path from the node to the output lead when the voltage level of the node reaches a second predetermined limit. The pump circuits can each include a logic circuit that is configured, depending on the level of an external supply voltage, to reduce the rate at which the capacitor node is boosted when the external supply voltage is relatively high.

Abstract: In this invention a booster circuit is driven with two complimentary boost signals. The two boost signals produce two complimentary boosted signals that are connected to a pump circuit output by means of two pass gate circuits. The transistors in each pass gate are controlled such that one pass gate circuit conducts in a first half of a clock cycle and the second pass gate circuit conducts in a second half of a clock period. Each pass gate is driven such that the full boosted signal is transferred to the output of the pump circuit and is not diminished by a threshold voltage of the pass gate circuit. The efficiency of this design keeps the output capacitor charged to a value close to the average value of boosted signal.

Abstract: A method, and related circuit, prevent the triggering of a parasitic transistor in an output stage of an electronic circuit. The stage includes a transistor pair with at least one transistor of the pull-up PMOS type having respective source, gate and drain terminals and a body terminal, and a parasitic bipolar transistor having a terminal connected to the body terminal. The method includes the steps of providing a capacitor connected between the body and source terminals of the PMOS transistor; and using a control circuit to suppress the body effect of the pull-up PMOS transistor.

Abstract: A high voltage NMOS switch is adjustable in order to optimize the switch for proper operation with different circuit configurations. A high voltage booster, included within the high voltage NMOS switch, enables the switch to reclaim the previously unused second half-cycle of a power source waveform signal, which thereby increases the speed of the NMOS switch by a factor of two. In addition, the high voltage NMOS switch provides added ramp rate flexibility by enabling a user to optimize the ramp rate of the high voltage NMOS switch for different circuit configurations.

Abstract: Output nodes (Noutn, Noutp) outputting a negative potential (VN) and a positive potential (VPS) respectively are supplied with fixed potentials by reset circuits respectively when unused. Switches (SW2, SW3) conduct when generating the negative potential, while switches (SW1, SW4) conduct when generating the positive potential. Reference potentials for the generated potentials are supplied to internal nodes (N10, N20) through the switches (SW1, SW3) respectively. Poly-diode elements are employed for a voltage generation part, whereby a charge pump circuit capable of generating positive and negative voltages can be implemented without remarkably changing a fabrication method.

Abstract: A voltage boosting circuit having an asymmetric MOS in DRAM. A gate of a first NMOS connects to a voltage source, and a source region of the first NMOS connects to a row decoder. A gate of the asymmetric NMOS connects to a drain region of the first NMOS. A drain region of the asymmetric NMOS connects to a column decoder, and a source region of the first asymmetric NMOS connects to a word line. A gate of a second NMOS connects to the column decoder, a source region of the second NMOS connects to a ground terminal and a drain region of the second NMOS connects to a source region of the first asymmetric NMOS.

Abstract: In the semiconductor circuit device of the present invention, the switching circuit 10 connects the power supply pin 4 to the capacitance 9 before the input signal 2 to the semiconductor circuit 1 is changed so that the electric charge of the semiconductor 1 is stored in the capacitance 9, and when the input signal 2 is changed, the semiconductor circuit 1 is charged with the electric charge stored in the capacitance 9. And, after the input signal 2 is changed, the switching circuit 10 connects the power supply pin 4 to a power supply to charge the semiconductor circuit 1.

Abstract: An H-bridge circuit having a boost capacitor coupled to the gate of the low-side driver. A driver, in the form of a switching transistor is connected between the load and ground, thus providing a low-side driver. A capacitor is coupled to the gate of the low-side driver to provide a boosted voltage for rapid turn on of the gate. The size of the capacitor selected to be similar to the size of the capacitance associated with the low-side driver transistor.

Abstract: A circuit that produces a gate drive voltage for a MOS transistor switch, that receives an input voltage "on" a source terminal, includes a first input that receives the input voltage, a second input that receives a bias voltage, and a voltage storage element. A first switch connects the voltage storage element to sample one of the input voltage and the bias voltage during a first of first and second non-overlapping time intervals. A second switch connects the voltage storage element to increase the sampled voltage by another of the input voltage and the bias voltage to the gate drive voltage during the second non-overlapping time interval, while maintaining the gate drive voltage less than a breakdown voltage of the MOS transistor switch. A third switch connects the voltage storage element to provide the gate drive voltage to the MOS transistor switch such that a gate-to-source voltage of the MOS transistor switch is maintained approximately constant.

Abstract: Integrated buffer circuits include an output driver powered at a first power supply voltage (EVC) and a voltage boosting circuit which drives an input (DOK) of the output driver and is powered at a second power supply voltage (VINTQ) having a magnitude less than a magnitude of the first power supply voltage. An internal power supply voltage generator is provided which generates the second power supply voltage at a level which varies inversely with increases in the first power supply voltage in order to minimize timing skew associated with the output driver. This is achieved by lowering the voltage of the signal applied to the input (DOK) of the output driver to compensate for the output driver being powered at an increased first power supply voltage.

Abstract: A ramping circuit gradually applies an erasing voltage to a memory cell. Within the ramping circuit an NMOS transistor is disclosed which gradually supplies the erasing voltage to the memory cell in response to an external ramping voltage. The NMOS transistor supplies the erasing voltage until the body effect loss voltage of the transistor limits a maximum erasing voltage that the NMOS transistor can supply. The specification then discloses a PMOS transistor which operates to supply the erasing voltage to the memory cell when the NMOS transistor can no longer do so. The PMOS transistor is connected to control circuitry which keeps the PMOS transistor inactive until the output voltage of the NMOS transistor is limited by its body effect voltage loss.

Abstract: A power MOSFET switch is connected in parallel to a capacitive actuator for the purpose of protecting the actuator against over-voltage. The protective power MOSFET switch is rendered conductive by a supplemental circuit when the actuator voltage exceeds a predetermined threshold limit voltage or when the control circuit emits a corresponding signal.

Abstract: A logic circuit includes: a main switching means for changing conduction state between at least two terminals in accordance with a voltage supplied to a control terminal; and a voltage converting means for converting a voltage at an input terminal and outputting the converted voltage to the control terminal.

Abstract: In a semiconductor device having a plurality of output circuits such as a semiconductor memory device, a drive signal having a boosted voltage level which is produced from a boosting circuit is applied to a gate of a low-level outputting MOS transistor in the output circuit. As a result, even when a potential at the ground wiring line is floated, a substantial decrease of a potential difference between the ground wiring line and the gate of the low-level outputting MOS transistor can be prevented. Also, a signal having a sufficiently high level can be supplied to a gate of a low-level outputting output MOS transistor. As a consequence, delays in the switching operation of the output MOS transistor can be suppressed, and the output circuit can be operated at high speed.

Abstract: A bootstrap sample and hold circuit accurately acquires and holds values of a high frequency analog input signal, to avoid harmonic distortion of a signal representing the analog input signal in, for example, a pipeline ADC, includes a first sampling MOSFET coupling the analog input signal to a sampling capacitor. A bootstrap circuit includes a bootstrap capacitor. First and second MOSFETs couple the bootstrap capacitor between a first reference voltage and ground in response to pulses of a first clock signal. Third and fourth MOSFETs then couple the bootstrap capacitor between the gate and source of the sampling MOSFET in response to non-overlapping pulses of a second clock signal to apply a constant gate-to-source voltage to the sampling MOSFET, the gate-to-source voltage having a magnitude equal to the difference between a first reference voltage and ground during the pulses of the second clock signal.

Abstract: Disclosed is a biasing circuit for bringing a power FET to a substantial full enhancement. The biasing circuit includes: (a) a rail power voltage that is coupled to a drain terminal of the power field effect transistor; (b) a load being coupled between an other potential and a source terminal of the power field effect transistor; and (c) a micromachined DC/DC converter that is coupled between a gate terminal of the power field effect transistor and the rail power voltage. The micromachined DC/DC converter is configured to produce an enhanced voltage that is greater than the rail power voltage to the gate terminal of the power field effect transistor to achieve a substantial enhancement of the power field effect transistor.

Abstract: A circuit for providing programmable voltage output levels in a logic device includes a pull-up device for driving an output pad with either a first voltage output level or a second voltage output level. A charge pump generates a pumped voltage. A first clamp regulator, coupled to the charge pump and the pull-up device, receives a first reference signal. The first clamp regulator, in response to the first reference signal, generates a first voltage from which the first voltage output level is derived. A second clamp regulator, coupled to the pull-up device, receives a second reference signal. In response to the second reference signal, the second clamp regulator generates a second voltage from which the second voltage output level is derived. A passgate multiplexer is coupled to the first and second clamp regulators. The passgate multiplexer receives at least one output voltage select signal.

Abstract: A circuit for charging a capacitance using an LDMOS integrated transistor functioning as a source follower stage and controlled, in a manner to emulate a high voltage charging diode of the capacitance via a bootstrap capacitor charged by a diode connected to the supply node of the circuit, and by an inverter driven by a logic control circuit as a function of a first Low Gate Drive Signal and of a second logic signal. The second logic signal is active during a phase where the supply voltage is lower than the minimum switch-on voltage of the integrated circuit. The circuit further includes a second inverter functionally referred to the charging node of the bootstrap capacitor and to the voltage of the output node of the inverter. The second inverter has an input coupled to the second logic signal and an output coupled to the gate node of the LDMOS transistor for preventing accidental undue switch-on of the LDMOS transistor.

Abstract: A circuit that produces a gate drive voltage for a MOS transistor switch, that receives an input voltage "on" a source terminal, includes a first input that receives the input voltage, a second input that receives a bias voltage, and a voltage storage element. A first switch connects the voltage storage element to sample one of the input voltage and the bias voltage during a first of first and second non-overlapping time intervals. A second switch connects the voltage storage element to increase the sampled voltage by another of the input voltage and the bias voltage to the gate drive voltage during the second non-overlapping time interval, while maintaining the gate drive voltage less than a breakdown voltage of the MOS transistor switch. A third switch connects the voltage storage element to provide the gate drive voltage to the MOS transistor switch such that a gate-to-source voltage of the MOS transistor switch is maintained approximately constant.

Abstract: A semiconductor integrated circuit includes a first charge pumping circuit connected to an input node. The first charge pump circuit includes a plurality of first driving transistors and charges an input voltage at the input node to a control voltage. A second charge pumping circuit includes a plurality of second driving transistors that each receive the control voltage from the first charge pump. The received control voltage controls the driving of the second transistors when charging an output node to an output voltage. To eliminate body effects, the semiconductor integrated circuit further includes a plurality of body transistors that connect the source and body terminals of the driving transistors.

Abstract: A charge pump includes a plurality of stages connected in series between a reference potential and an output terminal of the charge pump. The plurality of stages includes a first group of stages, proximate to the reference potential, and a second group of stages proximate to the output terminal of the charge pump. Each stage of the first group includes a pass-transistor with first and second terminals respectively connected to an input and an output of the stage, and a first capacitor with a first plate connected to the output of the stage and a second plate driven by a digital signal switching between the reference voltage and a positive voltage. Each stage of the second group includes a junction diode having a first electrode connected to an input of the stage and a second electrode connected to an output of the stage, and a second capacitor having a first plate connected to the output of the stage and a second plate driven by a digital signal switching between the reference voltage and the voltage supply.

Abstract: The well regions of pumping units of charge pump circuits are maintained electrically floating. By maintaining the wells electrically floating, reduced impact from the body effect may be obtained. More specifically, integrated circuit charge pump circuits boost a first voltage from a voltage source to a second voltage at an output terminal. The charge pump circuits include a plurality of pumping units in an integrated circuit substrate of first conductivity type, that are serially connected between the voltage source and the output terminal. Each of the pumping units includes a well region of second conductivity type in the integrated circuit substrate of first conductivity type. The well region of second conductivity type is electrically floating.

Abstract: This invention presents an all-N-logic true-single-phase CMOS dynamic logic circuit for high speed operation with a low supply voltage, in which a bootstrapped circuit containing a bootstrap capacitor, an inverter and a PMOS transistor is incorporated to a conventional non-inverting N1-block.

Abstract: An insulated-gate field effect transistor comprising a channel forming region, source/drain regions, a gate region, a bias supplying means, and a capacitive element, wherein a potential for controlling a gate threshold voltage of the insulated-gate field effect transistor in an off-state thereof is applied to the channel forming region through the bias supplying means, and a signal having approximately the same phase as a phase of a signal supplied to the gate region is supplied to the channel forming region through the capacitive element.

Abstract: A potential across an output terminal (OUT) is applied to a node N2 through a transistor (Tr66) even when a potential across a node N1 is higher than a power source voltage Vdd due to a bootstrap effect. Accordingly, the potentials between the drain and the source electrodes are not higher than the power source voltage Vdd for both a transistor (Tr62) and the transistor (Tr66). This allows circuit designing without setting the withstand voltage for the transistor over the power source voltage Vdd.

Abstract: A capacitor is connected between the gate of a transistor that is an object of threshold voltage compensation and an input terminal. A switching device is connected between a current source connected to one terminal of the transistor and the gate of the transistor. A second switching device is connected between the input terminal and a terminal to which a reference voltage is applied. The switching device is turned ON so that the transistor is diode-connected. The switching device is turned ON, thus applying the reference voltage to the input terminal. A reference voltage is applied to a current inflow terminal connected to another terminal of the transistor. After charge dependent on the threshold voltage of the transistor is accumulated in the capacitor, the switching device is turned OFF. With this control, a difference of a threshold voltage from another deriving from the fine structure of transistors as well as a difference in threshold voltage between adjoining transistors can be compensated for.

Abstract: A circuit that produces a gate drive voltage for a MOS transistor switch includes an input that receives a supply voltage, a regulated voltage generating circuit that produces a regulated voltage, and a voltage storage element. A first switch connects the voltage storage element to sample one of the supply voltage and the regulated voltage during a first of first and second non-overlapping time intervals. The second switch connects the voltage storage element to increase the sampled voltage by another of the supply voltage and the regulated voltage to the gate drive voltage during the second non-overlapping time interval. A third switch connects the voltage storage element to provide the gate drive voltage to the MOS transistor switch during the second non-overlapping time interval. The regulated voltage generating circuit produces the regulated voltage such that a high level of the gate drive voltage exceeds the supply voltage yet is maintained less than a breakdown voltage of the MOS transistor switch.

Abstract: In a high voltage pass gate suitable for use as a block decoder in a flash memory circuit, the boosting of the block decoder's internal nodes is performed using coupling capacitors and boost transistors which are decoupled from the high capacitance pass gate node. The block decoder uses three internal block decoder nodes. Each of the three nodes is held to ground by a corresponding discharge transistor when the block is unselected. Each of the three nodes of a selected block is discharged to a normal supply voltage by a corresponding diode-connected regulation transistor when the high voltage supply is turned off after a programming operation has finished. Each of the three nodes has a separate coupling capacitor associated with it. One of the nodes is connected to the gates of the high voltage pass transistors, this node has high capacitance. The remaining two nodes have relatively small coupling capacitors.

Abstract: A circuit for driving a power transistor in pulse mode, particularly adapted for use in a defibrillator. The gate of the power transistor is connected to the drain of a depletion mode transistor so no charge can build up at the gate of the power transistor when the depletion mode transistor is in its normal, conducting state. An electrical path is provided which allows current to flow, in response to a control signal, so that negative charge builds up at the gate of the depletion mode transistor, causing it to switch off (non-conducting), at which point the same current flow begins to charge the gate of the power transistor, switching it on. When the current flow is reversed, the gate of the depletion mode transistor is discharged and it switches back on, causing the gate of the power transistor to also discharge and turn the power transistor off. The various components are selected such that leakage current is less than 1 .mu.a with the resulting power pulse lasting about 25 ms.

Abstract: A discharge control circuit is connected between an output signal line of a boot-strap circuit having an allowable output signal voltage level range and a low voltage line. If an output signal voltage level of the output signal line is within the allowable output signal voltage level range, then the discharge control circuit provides no electrical connection between the output signal line and the low voltage line and if the output signal voltage level of the output signal line exceeds the allowable output signal voltage level range, then the discharge control circuit provides an electrical connection between the output signal line and the low voltage line.

Abstract: The present invention discloses a negative voltage drive circuit which does not takes an influence from the load capacitor or the power supply voltage drive circuit according to the present invention comprises a cross pumping circuit, a pumping unit block and circuit for supplying VCC or VSS power supply voltages for the pumping unit block.

Abstract: In a preferred embodiment of the present invention, a bidirectional buffer connects a first device, such as a CMOS chip having a first voltage, such as VCC, to a second device having a second voltage, such as VDD, through a terminal pad. The buffer includes a bootstrap capacitor to assist in driving up the terminal pad. In particular, the buffer comprises an output and an input portion. The output portion includes a first driver for driving the terminal pad up to VDD and a second driver for driving the terminal pad down to VSS. The first driver includes a pull-up PMOS transistor and a pull-up NMOS transistor connected in series and the second driver includes a pull-down NMOS transistor. Further, preferably one pair of push-pull bootstrap control transistors are connected in parallel to the gate of the pull-up NMOS transistor for quickly driving up the first driver to a voltage level based on the bootstrap capacitor having a predetermined capacitance.

Abstract: A charge pump circuit that is capable of generating a voltage that is greater in absolute magnitude than that of the substrate voltage Vsub in circuits where the substrate cannot be pumped to a voltage that is greater in absolute magnitude than Vsub is disclosed. Various innovative circuit techniques are used to implement a, for example, negative charge pump circuit in an N-well CMOS process with all PMOS transistors. The negative charge pump circuit according to the present invention can reliably drive on-chip transmission line termination switches.

Abstract: A bootstrap clock generator powered by a variable DC power supply voltage signal generates an approximate boost voltage signal depending on the DC power supply voltage signal level. The clock generator comprises a capacitor having a first and a second terminal and a first switching circuit coupled to the first terminal so as to couple the variable voltage supply signal to the first terminal. A second switching circuit is coupled to the second terminal so as to couple a variable reference voltage signal to the second terminal. A third switching circuit is coupled to the second terminal so as to connect a substantially fixed reference voltage signal to the second terminal. A first and a second control signal activates the switching circuits, such that the first control signal activates the first and second switching circuits, and the second control signal activates the third switching circuit.

Abstract: A circuit configuration for generating an output voltage which is boosted beyond a supply voltage includes a boosting capacitor that is connected through a p-channel MOS transistor to an output node. A control circuit ensures that first of all the boosting capacitor and the output node are precharged through the use of respective precharging transistors when the p-channel MOS transistor is turned on, and that subsequently, during a shifting phase, the gate terminal of the p-channel MOS transistor is held at a floating potential. This prevents the voltage present between the gate and the main current path terminals of the p-channel MOS transistor from becoming greater than the supply voltage.

Abstract: A voltage pump circuit for precharging/pumping a charge to/from a pumping capacitor separately employs a voltage generator for independently supplying a well-bias voltage to a PMOS transfer transistor which transfers a charge of a precharged capacitor to produce reference voltage. The voltage of the voltage generator is applied to a well of the PMOS transfer transistor to body bias the PMOS transfer transistor and, thus, ruggedize its threshold voltage transistor. Here, the well-bias voltage equals or exceeds the reference voltage while being approximately twice a power source voltage.

Abstract: This invention discloses a 1.5 V bootstrapped pass-transistor-based Manchester-carry-chain circuit suitable for CMOS VLSI using a low supply voltage, in which a bootstrapper circuit is incorporated to enhance the speed performance of the conventional Manchester-carry-chain circuit, which is composed. The bootstrapper circuit contains two P-type metal-oxide-semiconductor (PMOS) transistors, one N-type metal-oxide-semiconductor (NMOS) transistor; a capacitor device, and an inverter. The bootstrapper circuit provides an output having a voltage overshoot, as a carry propagation signal, to the gate of a pass transistor of the Manchester-carry-chain circuit.

Abstract: An augmentation circuit for use in connection with a self-bootstrap type output buffer having an n-channel pullup transistor is disclosed. The augmentation circuit includes a capacitor formed by a second n-channel transistor, connected as a capacitor, and disposed between first and second capacitor terminals. A non-overlapping signal generator is formed from a pair of NOR gates, and an inverter, to generate a pair of control signals CS1, and CS2 wherein when one of the control signals is active, the other control signal is inactive. Four n-channel transistors are provided in a switching matrix. One pair of the four n-channel transistors responds to control signal CS2 to connect the capacitor formed by the n-channel transistor across and between ground, and the output pad. In this switched configuration, a voltage level on the output pad is effectively impressed upon the capacitor, and is stored thereon.

Abstract: An improved charge transfer stage with an expanded output voltage range and high charge transfer efficiency is described. The charge transfer stage can be implemented as an output stage in a four phase clock negative charge pump system. The charge transfer stage comprises a PMOS pass transistor coupling the transfer stage input and output, a resistor between the transfer stage input and the pass transistor gate, a clock terminal, a capacitor configured PMOS transistor coupling the clock terminal to the gate of the pass transistor, and a diode from the transfer stage output to ground. When the transfer stage input goes low, charge is coupled through the resistor to pre-charge the gate of the pass transistor. The resistor has a higher junction breakdown voltage than a transistor which allows the gate of the pass transistor to be driven to a larger voltage.

Abstract: A charging circuit for a bootstrap capacitance employing an integrated LDMOS transistor and including a circuital device for preventing the turning on a parasitic transistors of the integrated LDMOS structure during transients that comprises a plurality of directly biased junctions (D1, D2, . . . , Dn) connected in series between a source and a body of the LDMOS transistor structure and at least a current generator, tied to ground potential, coupled between said body and ground, has at least one switch (INT1) between said source and a first junction (D1) of said plurality of junctions and a limiting resistance (R) connected between the body and the current generator (GEN). The switch (INT1) is kept open during a charging phase of the bootstrap capacitance (Cboot) and is closed when the charge voltage (Vboot) of the bootstrap capacitance reaches a preset threshold.

Abstract: A booster circuit uses a source voltage to generate a boosted voltage that is higher than the source voltage. The booster circuit has two capacitors. The two capacitors are alternately charged and discharged in response to a signal applied to an input terminal. The first capacitor is discharged to boost the voltage at the boosting node, whereas the second capacitor is discharged to boost the voltage at an output terminal. Further, the booster circuit includes a control circuit. When the voltage at the input terminal changes from an "H" level to an "L" level, the control circuit supplies a voltage for discharging the first capacitor to the first capacitor after the second capacitor has been brought into a charging state. Since the voltage at the output terminal is reduced by the charging of the second capacitor, a transistor is deactivated in response to the voltage at the output terminal. As a result, the boosting node and the source voltage can be prevented from being coupled by the transistor.

Abstract: A charge pump circuit for charging/pumping charge into/out of a charge pumping capacitor. Charge is pumped from the capacitor to turn on one of a pair of MOSFET transistors formed in an integrated circuit for driving a load. The MOSFET transistors are connected at a node in series with one another. The charging capacitor has one end connected at the node and the other connected through a diode to one side of a power supply which is also applied across both transistors. An input signal turns the MOSFETs on and off in a complementary fashion. Each MOSFET has a gate which is discharged to ground when the MOSFET is turned off. A zener diode prevents the capacitor from pumping excess charge to the gate of the MOSFET to which it is connected. Another zener diode prevents damage resulting from excessive voltage external to the integrated circuit.

Abstract: A sampling capacitor interface circuit for storing charge on a sampling capacitor related to a sample of an input signal voltage during a charging phase and to transfer the stored charge to an output during a charge transfer phase, such input signal having bipolar voltages within a range above and below an input signal common mode voltage. The interface circuit includes a transistor having: an input electrode fed by the input signal; an output electrode coupled to the sampling capacitor; and, a control electrode. A controller is provided for producing a control signal having a first voltage during the charging phase and a second voltage during the charge transfer phase, such voltages being a unipolar voltage referenced to the input signal common mode voltage.

Abstract: A decoupling capacitor for an integrated circuit is operatively coupled to a supply and to control circuitry for isolating the capacitor. The control circuitry automatically isolates the capacitor in response to a current through the capacitor exceeding a certain threshold, but tends to restore the capacitor to operation if the current is merely caused by momentary conditions, rather than substantial failure of the capacitor. The control circuitry includes a first control device for automatically switching to an off state to isolate the capacitor in response to a voltage produced by the current exceeding a certain threshold. A discharging device tends to discharge the voltage and automatically turn on the first device when the current is caused by momentary conditions. The discharging device may include a control device responsive to an external control signal for switching the first control device on and off.