Abstract: An apparatus includes a plurality of multiplication circuits for accurately performing small scale multiplication of analog signals with digital signals. The multiplication circuits (M0-M7) are arranged in parallel, receiving an analog signal (X) and bits of a digital signal B. Each circuit generates an output corresponding to a multiplication of the analog signal (X) with a digital bit (B0-B7), that output being based on a weight of the digital signal bit. The outputs generated by each respective multiplication circuit are capacitively coupled to produce an output indicative of multiplication between the digital signal and the analog signal. Each multiplication circuit includes a pair of transistors which receive a common digital signal, and which combine to have switching characteristics of a mutual toggle, alternatively opening and closing.