Abstract: Provided is a driver circuit that includes a first operational mode and a second operational mode and outputs an output signal according to an input signal, including a first driver section that, in the first operational mode, generates and outputs the output signal according to the input signal and, in the second operational mode, outputs a power supply power having a predetermined voltage and a second driver section that, in the first operational mode, receives the output signal output by the first driver section and outputs the received signal to the outside and, in the second operational mode, generates the output signal according to the input signal and outputs the thus generated signal to the outside.

Abstract: A half bridge is described with at least one transistor having a channel that is capable in a first mode of operation of blocking a substantial voltage in at least one direction, in a second mode of operation of conducting substantial current in one direction through the channel and in a third mode of operation of conducting substantial current in an opposite direction through the channel. The half bridge can have two circuits with such a transistor.

Abstract: A semiconductor device includes a first conductive type first transistor, a first conductive type second transistor, a first power supply pad arranged between the first transistor and the second transistor and supplying a first potential, a second conductive type third transistor, a second conductive type fourth transistor, a second power supply pad arranged between the third transistor and the fourth transistor and supplying a second potential, a first output pad arranged between the first transistor and the third transistor, and a second output pad arranged between the second transistor and the fourth transistor, in which a direction in which a line connecting the first power supply pad with the second power supply pad extends is perpendicular to a direction in which a line connecting the first output pad with the second output pad extends.

Abstract: A power module is adapted to be connected to a voltage source and to supply power to a load. The power module includes a power transistor; and a gate controller for driving the power transistor. The gate controller includes a gate transformer, and an impulse generator that extends a negative drive phase of a gate voltage to the power transistor relative to a positive drive phase of the gate voltage to the power transistor.

Abstract: This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.

Abstract: A method for rendering a half-bridge circuit containing normally on switches such as junction field effect transistors (JFETS) inherently safe from uncontrolled current flow is described. The switches can be made from silicon carbide or from silicon. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of the integrated power modules. As described herein, a power supply can be added to the gate driver circuitry. The power supply can be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch through the gate driver. The terminal characteristics of the normally on switch can then be coordinated to the input-to-output characteristics of the power supply.

Abstract: A semiconductor integrated circuit device according to the present invention includes: a sample circuit in which through current to be monitored flows during switching between transistors; a non-overlap circuit for outputting an output signal for the switching in the sample circuit; a current detector for detecting the through current flowing during the switching; and a current comparator in which a reference current value with respect to the through current has been set and which compares a current value detected by the current detector with the reference current value and outputs a result of the comparison to the non-overlap circuit.

Abstract: In a control circuit and method for a high efficiency and low EMI switching amplifier, an input signal is compared with a reference signal to generate a comparison signal, and a control signal is generated in response to the comparison signal for a driver to generate an output signal. The output signal is fed back to control the slope of the reference signal in association with an initial level set for the reference signal to provide a minimum on-time period for the output signal. Alternatively, a reference value is provided to compare with the reference signal for setting a minimum on-time period for the output signal.

Abstract: A gate driving circuit has a variable current carrying path that switches a current carrying path among a driving target device, a DC power source and a reactor to operate in plural operation modes including at least a hold mode, a preparation mode, and an execution mode. The variable current carrying path includes a backflow path for causing a reactor current flowing through the reactor to flow back to the DC power source when a gate voltage of the driving target device deviates from a preset allowable voltage range. A drive control part sets the operation mode of the variable current carrying path to the hold mode and holds the ON state or the OFF state of the driving target device, and further switches the operation mode in sequence of the preparation mode and the execution mode, and realizes turn-on or turn-off of the driving target device.

Abstract: A discharge protection circuit for discharging a full-bridge circuit in a brushless DC fan, wherein the brushless DC fan comprises a control circuit outputting at least one first control signal and at least one second control signal to the full-bridge circuit. The second control signal is a reverse signal of the first control signal; and the full-bridge circuit comprises a first impedance, a second impedance and a switch. The switch has a first terminal, a second terminal, and a third terminal that is grounded. The first terminal and the first impedance are in series connection for receiving the first control signal to control the status of the switch. The second terminal and the second impedance are in series connection and are connected to the input terminal of the second control signal of the full-bridge circuit, and the full-bridge circuit is discharged according to the status of the switch.

Abstract: The invention relates to a circuit configuration (1) for controlling the operation of a half-bridge (13) by pulse-width modulation, especially in a synchronous rectifier mode. Said circuit configuration comprises a first terminal connection (23, 25) for electrically connecting the circuit configuration (1) to an insulated gate terminal of a bridge valve (15, 17) of the half-bridge (13), a second terminal connection (20, 22) for electrically connecting the circuit configuration (1) to an additional terminal of the bridge valve (15, 17), a lead (16, 18) electrically connecting the first terminal connection (23, 25) to the second terminal connection (20, 22), and an electric valve (43, 45) that can be switched on and off by pulse-width modulated signals. Said electric valve (43, 45) is disposed in the lead (16, 18) so that a flow of current through the lead (16, 18) can be released and blocked.

Abstract: A driver for a switching device has a plurality of driver circuits for driving the switching device and a control circuit. The control circuit selectively operates the driver circuits in response to a plurality of predetermined drive modes. Alternatively, a driver for a switching device has a driver circuit and a control circuit. The driver circuit is connected to a plurality of power sources. Each of the power sources has a different voltage. The control circuit selects one of the power sources for operating the driver circuit in response to a plurality of predetermined drive modes.

Abstract: The invention is a method and apparatus for supplying both positive and negative gate drive power supply potentials to the top switch, in a typical half-bridge semiconductor power topology, from the bottom switch gate drive power supplies and without the use of transformer, capacitive or optical isolation. A known method of providing the positive top switch gate drive supply is enhanced and used in conjunction with a new and novel method for providing the negative top switch gate drive supply. The negative top switch gate drive supply is provided by an additional, lower power semiconductor switch, which is substantially synchronized with the bottom semiconductor switch, except for a slight turn-on delay. When this additional switch is gated “on” and conducting, the negative bottom switch gate drive power is connected to the negative top switch gate drive supply energy storage capacitors.

Abstract: A semiconductor integrated circuit device according to the present invention includes: a sample circuit in which through current to be monitored flows during switching between transistors; a non-overlap circuit for outputting an output signal for the switching in the sample circuit; a current detector for detecting the through current flowing during the switching; and a current comparator in which a reference current value with respect to the through current has been set and which compares a current value detected by the current detector with the reference current value and outputs a result of the comparison to the non-overlap circuit.

Abstract: This invention discloses a new MOSFET device. The MOSFET device has an improved operation characteristic achieved by connecting a shunt FET of low impedance to the MOSFET device. The shunt FET is to shunt a transient current therethrough. The shunt FET is employed for preventing an inadvertent turning on of the MOSFET device. The inadvertent turning on of the MOSFET may occur when a large voltage transient occurs at the drain of the MOSFET device. By connecting the gate of the shunt FET to the drain of the MOSFET device, a low impedance path is provided at the right point of time during the circuit operation to shunt the current without requiring any external circuitry.

Abstract: A driver circuit that has a plurality of output elements that are switched on and off in staggered fashion by signals generated by first and second drive chains of a drive chain configuration. The first drive chain comprises “N” delay elements, each of which produces a time delay equal to tDELAY such that the total time delay produced by the first drive chain is equal to (N×tDELAY). The second drive chain comprises N+1 delay elements, “N” of which produce a time delay equal to tDELAY and one of which produces a time delay equal to ½(tDELAY). Therefore, the total time delay produced by the second drive chain is equal to ((N×tDELAY)+(½tDELAY)). The use of the delay element in the second drive that produces the time delay equal to ½(tDELAY) results in smooth transitions in the transition regions where the driver circuit output signal transitions from high to low and from low to high.

Abstract: The present invention achieves technical advantages as an improved Parallel Damping scheme suitable for very-low-supply preamp operation. The improved Parallel Damping Scheme accurately generates a programmable Iw flowing through the write head while compensating for a leakage current path through a Parallel Damping resistor.

Abstract: A demagnetizer for an inductive load having a driver circuit including at least one transistor and a ramp-down voltage source switchably connected to the driver circuit, so that when the ramp-down voltage source is connected to the transistor, it drives the voltage of the transistor below its threshold voltage.

Abstract: A P-CHANNEL MOSFET is configured as a high side switch by arranging a capacitor between the P-CHANNEL MOSFET gate and a pair of push/pull transistors in a control circuit. A pull-up resistor is connected with the high side supply, one leg of the capacitor and with the gate of the P-CHANNEL MOSFET. In a two-phase electrical drive circuit, a pair of P-CHANNEL MOSFETS is connected with the high side supply and a pair of N-CHANNEL MOSFETS is connected with the low side supply.

Abstract: A motor bridge driver interface, implemented in an ASIC using cost-efficient CMOS technology, is designed to control four external MOS power transistors in a H-bridge configuration for DC-motor driving to achieve accurate and fast switching. Said driver interface is comprising a charge pump for generating the control voltage for the high-side N-channel MOS transistors, high-side (HSD) circuits, low-side (LSD) circuits and a complex digital interface for supplying the control signals in a programmable timing scheme. A “strong” charge pump is used to realize a simple CMOS switch to steer the output to the high-side transistors of said H-bridge. The motor bridge is connected to the battery supply by an additional N-channel MOS transistor to implement a reverse supply protection.

Abstract: A transconductance circuit (16) and method for protecting an H-bridge power circuit (10) that provides power to a load that includes an inductive component (14) connected between one side of the inductive component (14) and a gate (25) of a low side transistor (24) of the H-bridge (10). The transconductance circuit (16) operates to pull current from the inductive component (14) to ground (30) when the inductive load (14) sources current to a body diode of the high side transistor (20). The transconductance circuit (16) creates a regulated voltage to the gate (25) of the low side transistor (24) to cause the low side transistor (24) to conduct the current away in a regulated manner from the inductor (14) and the high side transistor (20) to ground (30).

Abstract: An H-bridge driver has a drive signal generating circuit for generating a square-wave signal as a drive signal. The H-bridge driver also has a waveform shaping circuit for blunting the waveform of the drive signal at the rising and trailing edges thereof. The waveform shaping circuit has a first circuit for generating, in a rising period of the square-wave signal fed thereto, a first current having a positive peak at the center of the rising period, a second circuit for generating, in a trailing period of the square-wave signal fed thereto, a second current having a negative peak at the center of the trailing period, and a capacitor to which the first and second currents are fed. The waveform shaping circuit outputs the voltage across the capacitor as its output voltage.

Abstract: An inductive load driving circuit includes a switching transistor and a guardring. The switching transistor is connected between an output terminal and a power supply potential point. The guardring is an N-type semiconductor region provided for the switching transistor and connected to the power supply potential point.

Abstract: In an integrated circuit, a data link relies on low swing differential signals. A push-pull driver circuit and a receiver circuit are both clocked from a common on-chip clock. A driver circuit includes an H-bridge of NMOS transistors and a line-to-line precharge circuit which reduces the power requirements of the circuit. A clocked repeater within the link may itself comprise a clocked receiver and an H-bridge driver with line-to-line precharge.

Abstract: A half-bridge circuit including a low-side drive module (110) and a high-side drive module (210) for driving respective lower (T1) and upper (T2) transistors. Each drive module (110, 210) is a charge trap circuit in that the low-side drive module (110) drives the low-side transistor (T1) with the charge on a capacitive load (C), and the high-side drive module (210) alternately recharges the capacitive load (C) as it is driven by a high-voltage supply. Each charge trap circuit (110, 210) also includes a diode (D1, D2) that prevents unintentional loss of charge on a gate of a driven transistor (T1, T2), and a zener diode (Z1, Z2) that clamps the gate voltage at a safe level. In this manner, the half-bridge circuit is efficiently driven without the need of an auxiliary power supply.

Abstract: An SCSI circuit which allows for the independent control of driver slew rate and amplitude with a linear shaped driver output voltage. The circuit comprises 1) a symmetrical H-Driver having at least four predrive controls; and 2) a predrive control circuit coupled to one of the predrive controls for independently varying the amplitude and rise time. The SCSI circuit is designed to utilize minimal space on the IO circuit pad, thereby conserving the amount of space allotted by the silicon area on the integrated circuit chip.

Abstract: A circuit to power multiple load elements is presented. Fewer discrete components and fewer output terminals are required to power multiple devices. A single high-power DC boost circuit powers multiple AC devices. An end-user can selectively power a subset of the AC devices electrically connected to the present invention. The circuit includes a first and second reference voltage terminal, and a first, second, and third switch. The circuit also includes a first control switch and a second control switch in electrical communication with the first switch and the second switch, respectively. The first control switch provides either a first control signal or a second control signal to a control terminal of the first switch. Similarly, the second control switch provides either the first control signal or the second control signal to a control terminal of the third switch.

Abstract: A method and apparatus are taught for driving a gate of a power device to turn on the power device utilizing a lossless gate driver circuit. The circuit comprises in parallel a power section, a rectifying section, a switching section, a capacitance, and an anti-spiking section. The circuit further comprises a transformer section coupled to the rectifying section, the switching section, and the anti-spiking section and a power device coupled to a portion of the anti-spiking section. The system is configured to regenerate substantially all energy utilized to power the power device via the coupling of the transformer section to the rectifying section, the switching section, the capacitance, and the anti-spike section.

Abstract: An inductive load driver circuit including a first switch that switches between a conductive state and a non-conductive state selectively applies a first power supply potential to a first side of the inductive load in response to a control signal. A second switch that switches between a non-conductive state and a conductive state selectively applies a second power supply potential to a second side of the inductive load in response to the control signal. The control signal places a control node of the second switch at a lower potential than the second side of the inductive load while the second switch is in the conductive state. In operation, a steady state current in a first direction is driven through the inductive load. The nodes of the inductive load are placed in a high impedance state, after which a steady state current is driven in a second direction through the inductive load.

Abstract: A half-bridge circuit including a low-side drive module (110) and a high-side drive module (210) for driving respective lower (T1) and upper (T2) transistors. Each drive module (110, 210) is a charge trap circuit in that the low-side drive module (110) drives the low-side transistor (T1) with the charge on a capacitive load (C), and the high-side drive module (210) alternately recharges the capacitive load (C) as it is driven by a high-voltage supply. Each charge trap circuit (110, 210) also includes a diode (D1, D2) that prevents unintentional loss of charge on a gate of a driven transistor (T1, T2), and a zener diode (Z1, Z2) that clamps the gate voltage at a safe level. In this manner, the half-bridge circuit is efficiently driven without the need of an auxiliary power supply.

Abstract: The circuit has a push-pull end stage which acts as an amplifier stage for digital signals. The push-pull end stage has two n-channel MOS transistors which function as source followers and two p-channel MOS transistors which also function as source followers. The gate terminals of the respective n-channel MOS transistors and p-channel MOS transistors are each controlled by an operational amplifier through drivers. A voltage that determines the setpoint value of the high level of the output of the push-pull end stage is present at the non-inverting input of one operational amplifier and a voltage that determines the low level of the output of the push-pull end stage is present at the inverting input of the other operational amplifier.

Abstract: An organic electroluminescence (OEL) matrix-type single-pixel driver, which comprises: an OEL device, a first transistor, and a second transistor. The first transistor and the second transistor form a complementary structure so that when the data line uses the first transistor to drive an organic light-emitting diode (OLED) device, the second transistor is in the OFF state, causing no power consumption. When the data line is in the LOW state, the first transistor is in the OFF state. The second transistor is in a sub-threshold state after getting rid of extra charges.

Abstract: A method and circuit are disclosed for controlling the write head of a magnetic disk storage device. The circuit includes a pull-up device coupled to a terminal of the write head, for selectively providing a current to the write head though the write head terminal. The circuit further includes parallel-connected current sink circuits, each of which is coupled to the write head terminal and selectively activated to draw current from the write head via the write head terminal. A first transistor is connected in series between the pull-up device and the write head terminal and biased to provide a voltage differential between the write head terminal and the pull-up device. A second transistor is connected in series between the write head terminal and the current sink circuits and biased to provide a voltage differential between the write head terminal and the current sink circuits.

Abstract: An inductive load driving circuit, formed in an integrated circuit device, includes first, second, third, and fourth switching transistors, and a guardring. The first switching transistor is connected between a first power supply potential point and a first output terminal. The second switching transistor is connected between the first power supply potential point and a second output terminal. The third switching transistor is connected between the first output terminal and a second power supply potential point. The fourth switching transistor is connected between the second output terminal and the second power supply potential point. One of the third switching transistor and the fourth switching transistor is turned on or off depending on a power supply direction in which power is supplied to an inductive load connected between the first output terminal and the second output terminal.

Abstract: A resonant gate driver circuit suitable for driving MOS-gated power switches in high-frequency applications recovers gate drive energy stored in the gate capacitance of the power switches, resulting in substantially lossless operation. The resonant gate driver circuit provides bi-polar gate control signals that are compatible with PWM operation.

Abstract: A circuit for synchronous rectification including two power MOSFET transistor switches in which the bottom switch is a P channel MOSFET, rather than an N channel MOSFET. The circuit of the present invention uses a single channel driver, rather than a dual driver and eliminates the deadtime associated with conventional circuits, thus minimizing reverse recovery losses. In an alternative arrangement, the position of the output filter is switched so that the N channel MOSFET conducts during the freewheeling time and the P channel MOSFET (with a larger RDSON) conducts during the conductor charge cycle.

Abstract: A switchable voltage follower and a bridge driver that utilizes the voltage follower. The voltage follower has an output transistor pair, three switching devices and an operational amplifier. Each of the switching devices is controlled by a polarity terminal for switching the circuit to be a pull-up voltage follower or a pull-down voltage follower. The bridge driver is formed by two switchable voltage followers to provide a bridge push-pull driving capability by driving the two switchable voltage followers alternately.

Abstract: The invention provides a load driver circuit including at least one FET such as MOSFET QX, QY, and QZ, controlled by a control circuit providing gate control voltage to the load driving FET by means of a feedback loop connecting the FET and the control circuit, without utilizing any resistor connected in series with the load to detect the load current. This is done by detecting, as a measure of the load current Io, the drain-source voltage drop of the load driving FET QX-QZ by means of detection means 13, 14, and 15. Because the control circuit utilizes no resistor, but utilizes a MOSFET instead, in detecting load current Io, the invention advantageously has a compact form, requiring only a minimum space for connection with external components, cuts down significant power loss that would be otherwise entailed by a current detection resistor, is capable of detecting the load current at high precision, thereby allowing precise control of the load current, and provides an improved wide output dynamic range.

Abstract: A balanced transformer-less (BTL) power drive circuit comprises a push-pull type output transistor section connected with a main power supply PowVcc, and an input control section connected with an auxiliary power supply for providing the output transistor section with a control signal. The potential of the auxiliary power supply is selectively set equal to or above the supply potential of the main power supply, depending on the requirements for the dynamic range of the power drive circuit. In accord with the potential of the auxiliary power supply thus set, the output reference potential Vref is set to the medium of the dynamic range, thereby ensuring the linearity of the input-output characteristic of the drive circuit, irrespective of the selected level of the auxiliary power supply.

Abstract: A full-bridge DC-to-DC converter having an unipolar gate drive is disclosed. The full-bridge DC-to-DC converter includes a primary-to-secondary transformer, multiple gate drive circuits, and multiple gate drive transformers. The primary-to-secondary transformer converts a first DC voltage to a second DC voltage under the control of the gate drive circuits. Each of the gate drive circuits includes a first transistor and a second transistor. The gate of the first transistor is connected to a pulse voltage source via a diode. The drain of the second transistor is connected to the source of the first transistor, and the source of the second transistor is connected to the gate of the first transistor via a resistor, for discharging a gate-to-source voltage of the first transistor during the time when a voltage of the pulse voltage source is below a gate-to-source threshold voltage of the first transistor.

Abstract: A technique for supplying drive voltage to the gate of a high-side depletion-mode N-channel MOS-device for phase-leg circuits, H-bridges, or any circuit with a depletion-mode N-channel MOS-device with its source at a voltage above local ground.

Abstract: The bridge circuit for switching high currents has n (n=a natural integer) lowside and highside switches (T1 to T4) in the form of vertically structured MOS transistors on two separate chips. The highside switch is formed using DMOS technology. The lowside switches are formed using common-source technology with the source arranged on the rear side of the chip and the drain arranged on the front side of the chip. The drain is connected to the source of the associated highside switch.

Abstract: A power switching circuit with reduced interference radiation includes at least one pair of low-side and high-side MOS power transistors, between which a load resistor is connected. One or at least one of the low-side MOS power transistors is connected to a drive circuit having a divider for dividing a difference between a maximum output voltage of the MOS power transistor and an instantaneous output voltage at the load resistor as a dividend, by a maximum output voltage of the MOS power transistor as a divisor, and a level converter for generating a drive voltage for the MOS power transistor. The drive voltage is proportional to the quotient.

Abstract: A circuit accurately detects an arm voltage pulse from an inverter that is used for on-delay compensation. Specifically, switching elements S1 to S6 are provided with detection circuits C1 to C6, respectively, for detecting an on or off state of a corresponding inverter arm in order to detect an arm voltage pulse from the inverter accurately and without delay. Since outputs from the detection circuits C1, C3, C5 on an upper arm have an excessively high voltage level before processing, level-down circuits Dw1, Dw3, Dw5 reduce these outputs down to an appropriate voltage level for signals used by a control circuit. The outputs are then provided to an on-delay compensator in the control circuit.

Abstract: An active damping circuit damps the ringing effect caused by a write circuit for a disk drive. The circuit includes upper switches and lower switched current sources. A capacitive feedback is connected between the output and the lower switched current sources.

Abstract: The invention relates to a circuit arrangement having a half-bridge arrangement comprising a first and a second switch (T1;T2), each switch (T1;T2) having, between its operating and reference electrodes, an internal diode (DB1;DB2), which is reverse-connected in parallel with the main current flow direction of the respective switch (T1;T2), and also an internal capacitance (COSS1;COSS2), a series diode (DS1;DS2) being arranged in series with the respective switch (T1;T2) in the main current flow direction in such a way that current can flow in the main current flow direction, and a freewheeling diode (DF1;DF2) being connected in parallel with the respective series circuit formed by the switch (T1;T2) and the series diode (DS1;DS2), and having a load circuit (L;RL), which has at least one inductive component (L) and is connected to the midpoint of the half-bridge arrangement.

Abstract: A driver circuit for a latching type valve is provided which utilizes an electronic switch assembly to provide the dual polarity necessary to actuate the latching type valve to both its open and closed states. The driver circuitry includes a microprocessor and a slope detector circuit for monitoring the coil current used to energize the valve solenoid to determine when the valve armature has moved to its fully actuated position. The driver circuit preferably utilizes power MOSFET devices in the switch assembly configured into an H-bridge to drive the solenoid coil. Advantageously, the user of power MOSFET devices eliminates the necessity for a current sense resistor in the control circuitry, thereby decreasing power dissipation and increasing efficiency of the drive circuit, thereby prolonging the battery life used to drive the valve.

Abstract: A circuit and method to drive an H-bridge circuit is disclosed. The H-bridge circuit uses NMOS transistors for both the upper and lower sets of transistors. An inductive head is coupled between the terminals of the transistors. When a logic signal is received, it is boosted with a circuit including a capacitor and is used to drive one of the upper transistors. The upper transistor selected to be driven is responsive to the logic signal. A corresponding lower transistor is also driven, forcing current through the inductive head in a first direction. When the logic signal is received that is the complement of the first logic signal, the other upper and lower transistors turn on, thereby driving current through the inductive head in the other direction. Since all of the transistors in the H-bridge circuit are NMOS transistors, boosted driving circuits are used to quickly change the direction of the flux through the inductive head.

Abstract: In a write driver circuit for switching the direction of a write current passing through a magnetic head or the like having an inductance component, an H-shaped bridge circuit is formed by using four NPN transistors in order to switch the write current at a high speed. Four switching means for controlling the base potentials of the four NPN transistors are provided and two switching means for rapidly decreasing the base potential of one of the two NPN transistors on the power source side, which is turned off when the write current passing through the magnetic head is switched are provided, thereby widening a voltage difference occurring between both terminals of the magnetic head.

Abstract: A method and circuit is disclosed for controlling the write head of a magnetic disk storage device. The circuit includes a pull-up device coupled to a terminal of the write head, for selectively providing a current to the write head through the terminal. The circuit further includes parallel-connected first and second current sink circuits, each of which is coupled to the write head terminal and selectively activated to draw current from the write head via the write head terminal. The circuit further includes a control circuit for individually activating the pull-up device and the first and second current sink circuits. In particular, when reversing the direction of current flow through the write head from a first direction in which current is provided to the write head via the write head terminal to a second direction in which current is drawn from the write head from the write head terminal, both the first and second current sink circuits are activated by the control circuit.