Abstract: A power system including a gate driver configured with test circuitry to detect faults is disclosed. The power system may be configured to test the fault detection circuitry in order to confirm its ability to detect faults. Various methods and circuit implementations are disclosed to determine the ability of the system to detect faults. The testing may include different configurations and protocols in order to make conclusions about which components are likely responsible for a failure. These components may include components included in the gate driver or externally coupled to the gate driver. The disclose approach does not significantly add complexity because a test input to initiate a test may be communicated from a low voltage side to a high voltage side over a shared communication channel.

Abstract: A DC/DC converter includes a high-voltage side, a low-voltage side, a high-voltage side capacitor and a power conversion circuit. The high-voltage side includes a high-voltage positive terminal and a high-voltage negative terminal. The low-voltage side includes a low-voltage positive terminal and a low-voltage negative terminal. The low-voltage negative terminal is electrically connected with the high-voltage negative terminal A first terminal of the high-voltage side capacitor is electrically connected with the high-voltage positive terminal. A second terminal of the high-voltage side capacitor is electrically connected with the low-voltage positive terminal. The power conversion circuit is electrically connected between the high-voltage side and the low-voltage side. The power conversion circuit includes at least one switch and at least one magnetic assembly.

Abstract: A method for operating a multi-level bridge power converter of an electrical power system connected to a power grid includes providing a plurality of switching devices of the power converter in an active neutral point clamped topology. The method also includes operating the plurality of switching devices in a plurality of operating states such that current simultaneously flows through at least two parallel recovery paths of the plurality of switching devices during operation of the power converter to minimize a commutation path of the current when at least one diode of the plurality of switching devices recovers, thereby reducing parasitic inductance affecting the recovering antiparallel diode or the switch.

Abstract: A light-emitting diode (LED) backlight modulation method based on duty cycle reference point setting is provided, and the LED backlight modulation method is applied to an LED backlight control circuit with row and column scan lines. Different duty cycle reference points are set for the LED string channels in the LED backlight control circuit in row-column scanning mode, whereby the LED string channels can be turned on or off at different time points during a turn-on duration of the row scan line to achieve lighting in the duty cycle, so as to realize the staggered setting of the turn-on time point and turn-off time point of each channel and avoid the need for large current jump at a power drive terminal.

Abstract: A synchronous rectifier driver circuit is configured to drive a synchronous rectifier FET and includes a first terminal configured to be connected to a source terminal of the synchronous rectifier FET. A second terminal is configured to be connected to a drain terminal of the synchronous rectifier FET, and a third terminal is configured to be connected to a gate terminal of the synchronous rectifier FET. The synchronous rectifier driver circuit is configured to measure the voltage between the second terminal and the first terminal, and detect a switch-on instant in which the measured voltage reaches a first threshold value and a switch-off instant in which the measured voltage reaches a second threshold value. The synchronous rectifier driver circuit generates a drive signal between the third terminal and the first terminal as a function of the measured voltage.

Abstract: A circuit includes a first transconductance stage having an output. The circuit further includes an output transconductance stage, and a first source-degenerated transistor having a first control input and first and second current terminals. The first control input is coupled to the output of the first transconductance stage. The circuit also includes a second transistor having a second control input and third and fourth current terminals. The third current terminal is coupled to the second current terminal and to the output transconductance stage.

Abstract: A half-bridge power supply comprises: a first switch electrically connected to an energy source and to a load; a second switch electrically connected to the energy source and to the load; and circuitry electrically connected to the first and second switches and configured to provide a dynamic dead time for the half-bridge power supply based on one of the first and second switches being turned off having forward current.

Abstract: An apparatus includes a first high-side driver of a buck-boost converter, the first high-side driver powered between a first bootstrap voltage (VBST1) and a first output voltage of a first high-side switch driven by the first high-side driver. A second high-side driver is powered between a second bootstrap voltage (VBST2) and a second output voltage of a second high-side switch driven by the second high-side driver. A comparator is to detect VBST1 drop below a threshold value with respect to the first output voltage when the buck-boost converter is in boost mode. A leakage control circuit is to boost, using VBST2 as a voltage source, VBST1 each cycle of boost mode in which an output of the comparator is enabled.

Abstract: An apparatus includes a first switch and a second switch connected in series between a first voltage bus and a second voltage bus, wherein a common node of the first switch and the second switch is connected to a first terminal of a first coil magnetically coupled to a second coil, and a third switch and a fourth switch connected in series between the first voltage bus and the second voltage bus, wherein a common node of the third switch and the fourth switch is coupled to a second terminal of the first coil, and wherein a gate of the first switch is controlled by a first signal derived from a signal on the common node of the third switch and the fourth switch, and a gate of the third switch is controlled by a second signal derived from a signal on the common node of the first switch and the second switch.

Abstract: A power converter can include first, second, third, and fourth power switches, and a driver for operating the drive switches to modify an input voltage. An AC coupling capacitor can be coupled between the first and fourth power switches. Bootstrap capacitors can be used for driving the first and second power switches, which can be high-side switches. In some embodiments, a current sensing circuit can be used to measure current through the third and/or fourth power switches and for determining the current through the power converter. In some embodiments, the power converter can monitor the voltage across the AC coupling capacitor and can determine the current through the power converter based on the monitored voltages. In some embodiments, the AC coupling capacitor can be pre-charged before the power converter begins normal operation.

Abstract: Each of a P-side IGBT and an N-side IGBT connected in series to implement an arm includes a first gate and a second gate. In each of a drive circuit unit configured to control a voltage of the first gate with respect to a collector of the P-side IGBT, a drive circuit unit configured to control a voltage of the second gate with respect to an emitter of the P-side IGBT, and a drive circuit unit configured to control a voltage of the second gate with respect to a collector of the N-side IGBT, a signal processing circuit and an output circuit are electrically isolated from each other by an isolation structure.

Abstract: Circuits comprising: a first capacitor(C1); a first switch(S1) having a first side coupled to a VIN and a second side coupled to a first side of C1; a second switch(S2) having a first side coupled to the second side of S1; a third switch(S3) having a first side coupled to a second side of S2 and a second side coupled to a second side of C1; a fourth switch(S4) having a first side coupled to a second side of S3 and a second side coupled to a VSUPPLY, wherein: in a first state, S1 and S3 are off, and S2 and S4 are on; in a second state, S1 and S3 are on, and S2 and S4 are off; and at least one of a control of S1, a control of S2, a control of S3, and a control of S4 is coupled to a time-varying-slew-rate signal.

Abstract: An overcurrent protection circuit includes an amplifier configured to amplify an inter-terminal voltage of a shunt resistor, an offset application circuit configured to allow the amplifier to provide an output with a predetermined offset voltage additionally applied thereto, a first comparator that compares an output voltage from the amplifier with a predetermined first reference voltage higher than the offset voltage to output a through-current sensing signal when the output voltage from the amplifier is higher than a first reference voltage, and an amplifier failure determination circuit that compares the output voltage from the amplifier with a predetermined second reference voltage that is higher than zero and lower than the offset voltage to output an amplification circuit failure determination signal corresponding to a result of the comparison.

Abstract: In some examples, a power converter includes a first bridge circuit, a second bridge circuit, and a transformer, where a first side of the transformer is coupled to the first bridge circuit. The power converter further includes a first LC tank circuit coupled to a second side of the transformer and a second LC tank circuit coupled to the first LC tank circuit and coupled to the second bridge circuit.

Abstract: A voltage-to-current converter includes a first differential pair of transistors, a second differential pair of transistors, and a first resistor. The first differential pair of transistors includes a first transistor and a second transistor. An emitter of the first transistor is directly connected to an emitter of the second transistor. The second differential pair of transistors includes a third transistor and a fourth transistor. An emitter of the third transistor is directly connected to an emitter of the fourth transistor. The first resistor is connected to the emitter of the first transistor, the emitter of the second transistor, the emitter of the third transistor, and the emitter of the fourth transistor.

Abstract: An AC line filter module includes AC-to-DC rectification circuitry. The rectification circuitry includes four low forward voltage rectifiers coupled together as two high-side rectifiers and two low-side rectifiers, where each low forward voltage rectifier includes an NPN bipolar transistor and a parallel-connected diode. A current splitting pair of inductors splits a return current so that a portion of the current is supplied to the collector of an NPN bipolar transistor that is on, and so that the remainder of the current is supplied to the base of the transistor that is on. Both low-side rectifiers are driven by these current splitting inductors. A pair of base current return diodes provides base current return paths. Due to the use of NPN bipolar transistors and no PNP bipolar transistors, manufacturing cost is reduced and efficiency is improved as compared to an implementation that uses low forward voltage rectifiers having PNP transistors.

Abstract: Systems related to controlling a DC/AC converter. A control system uses a nonlinear adaptive observer to estimate the state variables inverter current and converter voltage using a sensed grid current and a bus voltage as inputs. For non-observable points (such as when the duty cycle=0.5), the required information can be found from the DC bus voltage.

Abstract: An inverter device for a solar module. The inverter device comprises a slave circuit device that includes an input comprising a DC input from a solar cell group and a preliminary boost circuit. A DC boost circuit is coupled to the preliminary boost circuit and configured to boost the intermediary voltage to an AC RMS peak voltage. A rectifier circuit is coupled to the DC boost circuit. An energy recovery circuit comprises a storage device coupled to the rectifier output. The energy recovery circuit is configured to temporarily store a reverse recovery charge and transfers the reverse recovery charge to an output of a DC bus structure to reduce a diode recovery loss in the rectifier circuit.

Abstract: Embodiments of the present invention relate to methods and circuits for brightness regulation for at least one light-emitting diode in the field of general lighting, more particularly, for incandescent lamp replacement by means of a supply voltage comprising a brightness level signal, wherein the brightness level signal contained in the supply voltage is decoded and converted into a modulation signal with a duty cycle corresponding to the brightness level signal for the purpose of driving a driver circuit for the at least one light-emitting diode.

Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

Abstract: The invention relates to a method and to an apparatus for protecting transistors (S1, S3; S2, S4) arranged in at least one path, wherein transistors (S1, S3; S2, S4) connected in series to which an input voltage (Ue) is applied are arranged in a path (2), and the transistors (S1, S3; S2, S4) of a path are alternately switched between a conductive state and a blocking state in order to generate an output voltage (Ua) at the center of the path. In order to prevent both transistors (S1, S3; S2, S4) of a path from triggering, the blocking state of the second transistor (S3; S4) of the path is checked before switching a transistor (S1; S2) into the conductive state, and the switching is released by way of a signal generated during the check.

Abstract: A semiconductor device includes a control section, a first arm, and a second arm; and has an H-bridge circuit to supply an input current supplied from a power source to an output terminal as a reversible electric current on the basis of a control signal outputted from the control section and a reverse-connection-time backflow prevention circuit to prevent an electric current in a direction opposite to the direction of the input current from being supplied to the H-bridge circuit. The first arm is formed over a first island. The second arm is formed over a second island. The control section and the reverse-connection-time backflow prevention circuit are formed over a third island.

Abstract: A half bridge is described with at least one transistor having a channel that is capable in a first mode of operation of blocking a substantial voltage in at least one direction, in a second mode of operation of conducting substantial current in one direction through the channel and in a third mode of operation of conducting substantial current in an opposite direction through the channel. The half bridge can have two circuits with such a transistor.

Abstract: A method for rendering a half-bridge circuit containing normally on switches such as junction field effect transistors (JFETs) inherently safe from uncontrolled current flow is described. The switches can be made from silicon carbide or from silicon. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of the integrated power modules. As described herein, a power supply can be added to the gate driver circuitry. The power supply can be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch through the gate driver. The terminal characteristics of the normally on switch can then be coordinated to the input-to-output characteristics of the power supply.

Abstract: A gate drive circuit includes an insulated gate semiconductor switch. A controlled current source is connected to the semiconductor switch gate terminal to provide a gate drive circuit that is responsive to recycled gate charge corresponding to an internal gate capacitance of the insulated gate semiconductor switch.

Abstract: A method of operating a bridge switch control circuit is disclosed for controlling at least one pair of complementary switches. First, a first driving signal, a second driving signal, a first latching signal, and a second latching signal are provided. The first driving signal and the second driving signal drive the complementary switches. Afterward, it is to judge whether the first driving signal triggers one of the complementary switches by a rising-edge manner. If YES, the first latching signal is controlled at a high-level status and the second latching signal is simultaneously controlled at a low-level status. Afterward, it is to judge whether the second driving signal triggers the other of the complementary switches by a rising-edge manner. If YES, the second latching signal is controlled at a high-level status and the first latching signal is simultaneously controlled at a low-level status.

Abstract: Power switching circuits including an inductive load and a switching device are described. The switches devices can be either low-side or high-side switches. Some of the switches are transistors that are able to block voltages or prevent substantial current from flowing through the transistor when voltage is applied across the transistor.

Abstract: A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

Abstract: A regulating system for an insulated gate bipolar transistor (IGBT) includes a clamping circuit coupled to the IGBT. The IGBT is coupled to a gate driver circuit. The regulating system also includes a feedback channel coupled to the clamping circuit. The feedback channel is configured to transmit signals representative of a conduction state of said clamping circuit. The regulating system further includes at least one gate driver controller coupled to the feedback channel and the gate driver circuit. The gate drive controller is configured to regulate temporal periodicities of the IGBT in an on-condition and an off-condition.

Abstract: A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

Abstract: A circuit for simulating an electrical load at a terminal of a test circuit having at least one first switch and at least one second switch includes a third switch connected to the first switch of the test circuit via a first external connection point. A fourth switch is connected to the second switch of the test circuit via a second external connection point. The first switch and the second switch are connected via a shared, first internal connection point to the terminal of the test circuit and the third switch and the fourth switch are connected via a shared, second internal connection point such that that the first switch, the second switch, the third switch and the fourth switch form an H-bridge circuit. A voltage source is configured to provide the first and second external connection points with a supply voltage. A controllable voltage source is connected in a transverse bridge branch between the terminal and the second internal connection point. An inductance is active in the transverse bridge branch.

Abstract: The drive circuit is for turning on and off a switching element having an open/close control terminal, an input terminal and an output terminal by moving electrical charge in the open/close control terminal in accordance with an on-manipulation command and an off-manipulation command received from outside. The drive circuit includes an active gate control means for changing a moving speed of the electrical charge midway between when movement of the electrical charge is started and when the movement is completed, and a determination means for making at least one of a determination on a change timing to change the moving speed and a determination on whether or not a change of the moving speed by the active gate control means should be made.

Abstract: A semiconductor device includes a variable resistor that sets a resistance value as a first resistance value in an emphasis mode, and as a second resistance value smaller than the first resistance value in a de-emphasis mode, a first driver that sets an output impedance as a third resistance value in the emphasis mode, and as a fourth resistance value larger than the third resistance value in the de-emphasis mode, a second driver that sets the output impedance as a fifth resistance value in the emphasis mode, and as a sixth resistance value larger than the fifth resistance value in the de-emphasis mode, and a controller that controls conductive states of the first and second drivers according to an input signal, and switches the output impedances of the first and second drivers and the resistance value of the variable resistor between the emphasis mode and the de-emphasis mode.

Abstract: A signal transmitting apparatus that may suppress generation of a noise voltage attributable to a common mode voltage is provided. A transistor P1 is connected between a first terminal of a sending coil and a power supply voltage. A transistor N1 is connected between the first terminal and a ground voltage. A transistor P2 is connected between a second terminal of the sending coil and the power supply voltage. A transistor N2 is connected between the second terminal and the ground voltage. In a period-PE1 a coil current flowing in a positive direction is generated by turning on the transistors P1 and N2 and turning off the transistors P2 and N1, and then the transistor N1 is turned on in response to turning off the transistor P1. In a period PE2, a coil current flowing in a negative direction is generated by turning off the transistors P1 and N2 and turning on the transistors P2 and N1, and then the transistor N2 is turned on in response to turning off the transistor P2.

Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

Abstract: A switch circuit and an electronic device using the same include a power switch transistor, a controlling circuit, a regulated capacitor, and a capacitor. The power switch transistor is connected between an input and an output of the switch circuit. An output of the controlling circuit is connected to a controlling electrode of the power switch transistor and outputs pulse width modulation (PWM) signals to turn the power switch transistor on and off. The regulated capacitor is connected between an output of the switch circuit and ground. The capacitor is connected between an output of the controlling circuit and ground for increasing an inclination of a rising edge and a falling edge of PWM signals to slow down the speed of switching the power switch transistor on and off, thereby making the regulated capacitor charge slowly and the output voltage of the switch circuit stable.

Abstract: The present invention relates to a driver circuit wherein upper and lower legs of a first driver comprise first and second sets of parellelly coupled semiconductor switches, respectively. A control circuit is configured to generate respective control signals for the first and second sets of parellelly coupled semiconductor switches to create a current path through the upper and lower legs during an overlap time period between state transitions of a driver output.

Abstract: Power switching circuits including an inductive load and a switching device are described. The switches devices can be either low-side or high-side switches. Some of the switches are transistors that are able to block voltages or prevent substantial current from flowing through the transistor when voltage is applied across the transistor.

Abstract: Four energization switching devices and positive/negative switching devices are controlled to form a path charging a positive capacitor; a path connecting a power supply with the positive capacitor in series and energizing an inductor to charge a control terminal of a target switching device; a path charging the control terminal using electromagnetism in the inductor; a path supplying circulating current to the power supply when potential of the control terminal becomes higher than voltage of the power supply; a path charging a negative capacitor; a path connecting the power supply with the negative capacitor in series and energizing the inductor to discharge the control terminal; a path discharging the control terminal using electromagnetism in the inductor; and a path supplying circulating current to the power supply when potential of the control terminal becomes lower than potential of a negative terminal of the power supply.

Abstract: A half bridge is described with at least one transistor having a channel that is capable in a first mode of operation of blocking a substantial voltage in at least one direction, in a second mode of operation of conducting substantial current in one direction through the channel and in a third mode of operation of conducting substantial current in an opposite direction through the channel. The half bridge can have two circuits with such a transistor.

Abstract: Power switching circuits including an inductive load and a switching device are described. The switches devices can be either low-side or high-side switches. Some of the switches are transistors that are able to block voltages or prevent substantial current from flowing through the transistor when voltage is applied across the transistor.

Abstract: A gate drive circuit includes an insulated gate semiconductor switch. A controlled current source is connected to the semiconductor switch gate terminal to provide a gate drive circuit that is responsive to recycled gate charge corresponding to an internal gate capacitance of the insulated gate semiconductor switch.

Abstract: A motor load control apparatus capable of suppressing heat generation of an electronic switch and suppressing occurrence of noise associated with rotation of a fan and vibration of the fan is provided. A switch section (17) in which a first electronic switch (T1) and a second electronic switch (T2) are connected in parallel is provided, and the first electronic switch (T1) is driven by a PWM signal with a predetermined duty ratio and a predetermined frequency and the second electronic switch (T2) is driven in a state of delaying the PWM signal by which the first electronic switch (T1) is driven by a predetermined time. Consequently, as compared with the case of one electronic switch, a heating value of each of the electronic switches can be reduced and radiation measures of the whole apparatus can be reduced. Further, noise or vibration occurring by PWM control can be reduced by changing delay time at random.

Abstract: A method for rendering a half-bridge circuit containing normally on switches such as junction field effect transistors (JFETs) inherently safe from uncontrolled current flow is described. The switches can be made from silicon carbide or from silicon. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of the integrated power modules. As described herein, a power supply can be added to the gate driver circuitry. The power supply can be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch through the gate driver. The terminal characteristics of the normally on switch can then be coordinated to the input-to-output characteristics of the power supply.

Abstract: A PWM mode for turning on and off two output transistors by an output of a high impedance circuit and a constant voltage mode for controlling voltages at two output terminals by an output of an op amp are provided. Then, the two modes are switched by a switching signal.

Abstract: Techniques to generate boosted multi-level switched output voltages from a boosted multi-level Class D amplifier. The amplifier may include a multi-level H-bridge, which may include pairs of transistor switches coupled to a first, second, and third supply potential. The second supply potential may be a boosted representation of the first supply potential. The amplifier may receive an input signal, and from the input signal may generate pulse-modulated control signals to control the switching for the transistor switches of the multi-level H-bridge. The amplifier may generate the boosted multi-level switched output voltages from output nodes of the multi-level H-bridge.

Abstract: A method and an arrangement are provided for balancing the switching transient behavior of parallel connected power semiconductor components. The method includes providing a switch signal to the parallel connected power semiconductor components for changing the state of the components, forming control signals for each of the parallel connected components from the switch signal, and determining, during the change of state of the power semiconductor component, the voltage induced to an inductance in the main current path of the component in each of the parallel connected components. The method also includes comparing each of the induced voltages with a predetermined threshold voltage, measuring time differences between the time instants at which the induced voltages crosses the threshold voltage, and modifying one or more of the control signals on the basis of the measured time differences in the respective following state change for balancing the switching transient behavior.

Abstract: A half bridge converter includes a transformer with a high side switch coupled between a first input terminal and a primary winding of the transformer. A low side switch is coupled between a second input terminal and the primary winding. A first control circuit is coupled to the first input terminal and the primary winding to control the high side switch in response to a rate of voltage change with respect to time across the high side switch while the high side switch is off. A second control circuit coupled to the primary winding and the second input terminal to control the low side switch in response to a rate of voltage change with respect to time across the low side switch while the low side switch is off.

Abstract: The invention relates to a driver circuit used to transmit a digital signal from a source device to a destination device. The driver circuit provides a controlled switching time to improve digital signal quality, while reducing electromagnetic interference. In the circuit, a pair of first switches of a first plurality are coupled in parallel between a first current node and respective ones of first and second output terminals. A plurality of pairs of second switches of a second plurality are coupled in parallel between a respective second current node and the first and second output terminals. Timing circuitry applies input signals to the pair of first switches and successive input signals to the pairs of second switches so as to develop a staggered voltage across a load coupled between the first and second output terminals.

Abstract: A semiconductor chip includes a power transistor circuit with a plurality of active transistor cells. A first load electrode and a control electrode are arranged on a first face of the semiconductor chip, wherein the first load electrode includes a first metal layer. A second load electrode is arranged on a second face of the semiconductor chip. A second metal layer is arranged over the first metal layer, wherein the second metal layer is electrically insulated from the power transistor circuit and the second metal layer is arranged over an area of the power transistor circuit that comprises at least one of the plurality of active transistor cells.