Abstract: A CMOS device fabricated in a silicon-on-insulator structure and including circuitry and methods in a first embodiment dynamically shifts the threshold voltage of the CMOS device in a receiver to provide improved noise margin and in a second embodiment dynamically matches the threshold voltages in a differential amplifier to correct for manufacturing offset. To dynamically shift the threshold voltage for noise immunity, the back gate or bulk nodes of the devices is shifted through two similar circuits comprised of npn inverters with clamping devices. The back gate of the n device is biased at 0 volts for the maximum Vth and is biased at +1 threshold for the minimum Vth of the device. Only the back gate of the p device is biased at Vdd for the maximum Vth of the device and is biased at 1 Vth below Vdd for the minimum Vth of the device. The Vth of the n device and the p device should be less than the forward bias of the respective source volt junctions to prevent unwanted bipolar currents.

Abstract: A charge pump generator system and method is provided which more precisely maintains the level of an internally generated voltage supply by operating some or all of the available charge pumps depending upon the voltage level reached by the voltage supply. When the voltage supply is far from its target level, a first group and a second group of charge pumps are operated. The first group may preferably have a faster pumping rate or a greater number of charge pumps than the second group. When the voltage supply exceeds a first predetermined level, the first group of charge pumps is switched off while the second group remains on, such that the rate of charge transfer slows. The second group continues operating until a second, e.g. target, voltage level is exceeded. The slower rate of charge transfer then effective reduces overshoot, ringing and noise coupled onto the voltage supply line. Preferably, at least one charge pump operates in both standby and active modes, thereby reducing chip area.

Abstract: The disclosed semiconductor integrated circuit device can control the threshold thereof without adding any other supply voltages except a drive supply voltage and a ground supply voltage. The semiconductor integrated circuit device comprises: a substrate potential generating circuit operative on the basis of a control signal, for deepening a substrate bias by pumping out charges from a semiconductor substrate when activated, but for setting an output thereof to a high impedance when deactivated; and a switch circuit operative on the basis of the control signal and turned on when the substrate potential generating circuit is deactivated, to set potential of the semiconductor substrate to a supply potential, but turned off when the substrate potential generating circuit is activated.

Abstract: In some embodiments, the invention includes a die having a driver circuit. The driver circuit includes a driver input node and a driver output node. An nFET pull-up transistor is connected to the driver output node, and wherein the nFET pull-up transistor is at times forward body biased and the forward body bias is substantially greatest when a signal at the driver input node begins to switch high and substantially least when the switching has already essentially occurred. In some embodiments, the driver includes a first inverter to receive an input signal from the driver input node and provide an inverted input signal at a first inverter output node. The driver includes second inverter to receive the inverted input signal from the first inverter output node and provide a driver output signal at the driver output node. The driver includes an nFET pull-up transistor connected between the driver output node and a power supply node, the nFET pull-up transistor having a gate tied to the driver input node.

Abstract: The invention relates to a voltage reference source used to control an overvoltage tolerant input/output buffer for a mixed voltage bus system. The voltage source comprises a voltage tracking circuit having a first input receiving a variable voltage. and a second input receiving a reference voltage. the voltage tracking circuit being adapted to generate an output voltage in response to the difference between the variable voltage and the reference voltage. wherein where the variable voltage is less than the reference voltage. the output voltage is held at substantially zero volts. When the variable voltage exceeds the reference voltage. the output tracks the voltage at the variable voltage input.

Abstract: A high voltage input circuit includes a triple-well NMOS for reducing the voltage stress across its drain junction for preventing it from breakdown. The triple-well NMOS is fabricated in a P-well formed in a deep N-well on a P-substrate. The P-well is coupled to a power supply voltage by a P-well voltage control device to reduce the voltage difference across the drain junction. A low voltage signal input circuit portion is also added to the high voltage input circuit to allow a high voltage input pin to receive other signal and reduce the total pin count of an integrated circuit. A dual-input buffer such as NAND gate instead of an inverter is used in the low voltage signal input circuit for reducing the voltage stress to the devices in the low voltage signal input circuit.

Abstract: A select circuit switches a connection from a gate terminal of an NMOS transistor or a substrate voltage terminal to a semiconductor substrate or well by a Select signal. At this time, a voltage of the substrate voltage terminal is set to be lower than a gate voltage in an OFF state. Consequently, when the semiconductor substrate or well is connected to the gate terminal in an active state, the off-current can be reduced to 10−10 A/&mgr;m. When the substrate voltage terminal is connected to the semiconductor substrate or well in a standby state, the off-current can be further reduced to 10−12 A/&mgr;m. Thus, leakage currents in the standby state and leakage currents flowing from the power supply voltage terminal to the ground voltage terminal in an active state can be suppressed.

Abstract: A buffer circuit for mixed voltage applications. The circuit is built from field effect transistors and is used to interface with multiple voltage levels. The circuit uses a protection transistor in which the gate is controlled by a logic circuit having the mixed voltages as inputs. It is particularly useful on CMOS semiconductor chips that interface with multiple voltage levels which are required to conform to a specification allowing voltage levels to be powered down.

Abstract: An integrated circuit is provided for use with a supply voltage and which includes an input/output (I/O) circuit with an output driver with a pull-up transistor and a pull-down transistor and which includes an I/O pin connected to receive output signals from the output driver and connected to provide input signals to the integrated circuit, the protection circuit comprising: bias circuitry that imparts a bias voltage to the pull-up transistor so as to substantially prevent leakage current when a voltage applied externally to the I/O pin rises above the supply voltage; a switch connected to conduct current from the I/O pin to the supply voltage when the switch is turned on and to block current flow from the I/O pin to the supply voltage when the switch is turned off; and voltage clamp circuitry connected to clamp voltage on the I/O pin to the supply voltage when the switch is turned on; and programming circuitry which is programmable to turn the switch on and off.

Abstract: Circuit for discharging to ground, supplied by a supply voltage, comprising a reference voltage, a negative potential node, first circuitry adapted to couple the negative potential node to the reference voltage in response to a control signal. Second circuitry is provided adapted to determine in the first circuitry the passage of a controlled current for the discharge of the negative potential node.

Abstract: A plurality of substrate bias circuits (14, 16, and 18) are designed to provide a stable substrate reference potential for a variety of operating modes. Only one of the bias circuits is enabled by a control circuit (12) at any time for any operational mode. An on-demand boost bias circuit (16) is enabled whenever a level detector (20) indicates substrate bias has exceeded a predetermined limit during special operating modes such as burn-in or parallel test.

Abstract: Circuits with SOI devices are coupled to a body bias voltage via a switch for selectively connecting the body bias voltage signals to the SOI device body. NMOS or PMOS SOI devices are used for the switched body SOI device and a FET is used for the switch and the gate terminal of the SOI device is connected to the FET device. The gate of the SOI device controls the FET switch connection of the body bias voltage signals to the SOI device to adjust the threshold value of the SOI device. Logic circuits incorporating the SOI devices are also disclosed, and the fabrication process for the SOI devices as well.

Abstract: A bus switch for transferring logic signals between nodes without the problems associated with undershoot conduction. The bus switch is an FET switch including a single primary transfer transistor. The bulk of the transfer transistor is coupled to a differential logic sense circuit that is designed to establish a pseudo low-potential power rail. The logic sense circuit is coupled to the two transfer nodes and a standard low-potential power rail. It compares the potentials associated with the transfer node signals and the low-potential rail and selects the one with the lowest potential to establish the potential of the pseudo low-potential rail. The logic sense circuit provides for active selection of the lowest potential element, including under very small undershoot conditions.

Abstract: An arrangement of enhanced drivability transistors is disclosed herein which includes a plurality of conductor patterns, wherein the conductor patterns include ring-shaped portions which enclose device diffusion contacts and the ring-shaped portions form the gate conductors of insulated gate field effect transistors (IGFETs).

Abstract: An integrated circuit includes a substrate pump circuit developing an internal back-bias voltage on an output, and an external terminal adapted to receive an external back-bias voltage. A semiconductor substrate is coupled to the external terminal and to the output of the substrate pump circuit. The semiconductor substrate includes at least one transistor formed in the semiconductor substrate which has a first threshold voltage when the internal back-bias voltage is applied to the substrate. The at least one transistor has a second threshold voltage greater than the first threshold voltage when the external back-bias voltage is received on the external terminal.

Abstract: A semiconductor circuit or a MOS-DRAM wherein converting means is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converting means includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.

Abstract: In one embodiment, a semiconductor circuit includes a first group of field effect transistors having a body and parameters including a net channel doping level DL1. The circuit also includes a conductor to provide a first voltage to the body to forward body bias the first group of transistors, the first group of transistors having a forward body bias threshold voltage (VtFBB) when forward body biased, wherein DL1 is at least 25% higher than a net channel doping level in the first group of transistors that would result in a zero body bias threshold voltage equal to VtFBB, with the parameters other than the net channel doping level being unchanged. In another embodiment, the semiconductor circuit includes a first circuit including a first group of field effect transistors having a body.

Abstract: A differential receiver for sensing small input voltage swings by using a built in reference voltage obtained by a difference in threshold voltage between a differential pair of closely spaced transistors. The difference in threshold voltage can be produced by different values of ion implantation of the gates of the transistor pair with the same material, or by dosages using different materials. The difference in threshold voltage can also be obtained by using different transistor channel lengths. The threshold voltages can also be modulated by the control of the transistor substrate voltages using a voltage control substrate means.

Abstract: An output buffer switching circuit for producing digital output signals comprises a buffer amplifier section (12) for driving a load, a low-impedance transmission line (9) and a power supply section (11) for delivering power to the buffer amplifier section (12). The power supply section (11) comprises a pair of input connections (1, 2) for connection to a voltage source and a pair of output connections (3, 4) connected to the amplifier section (12), reactance devices for temporary energy storage and switching devices adapted to provide a charge phase in which energy from the voltage source is stored in the reactance devices and a discharge phase in which at least some of the energy stored in the reactance devices is discharged to the output connections (3, 4).

Abstract: An integrated circuit (100) includes a first input (108) to receive a first operating voltage Vcc and a second input (110) to receive a second operating voltage Vss. Operating circuitry (102) of the integrated circuit is coupled to the first input to power the operating circuitry. A transistor (104) is coupled between the second input and the operating circuitry to selectively provide the second operating voltage to the operating circuitry of the integrated circuit. The well containing the transistor is biased to provide a reverse body effect and reduce the threshold voltage of the transistor to allow operation at very low Vcc.

Abstract: A body voltage controlled semiconductor integrated circuit which can solve a problem of a conventional CMOS inverter in that it cannot operate at a supply voltage beyond the built-in voltage of the CMOS transistors if their body electrodes are each connected to their own gate electrodes rather than to their source electrodes to quicken the operation of the CMOS inverter. A voltage divider circuit is provided which conducts during the operation of the CMOS transistors of the inverter so that the body voltages of the PMOS transistor or the NMOS transistor of the inverter is varied in the direction of reducing their threshold voltages. By controlling the size of electrodes and the voltages applied to the body electrodes of transistors constituting the voltage divider circuit, it becomes possible to operate the CMOS inverter at the supply voltage beyond the built-in voltage.

Abstract: A differential receiver for sensing small input voltage swings by using a built in reference voltage obtained by a difference in threshold voltage between a differential pair of closely spaced transistors. The difference in threshold voltage can be produced by different values of ion implantation of the gates of the transistor pair with the same material, or by dosages using different materials. The difference in threshold voltage can also be obtained by using different transistor channel lengths. The threshold voltages can also be modulated by the control of the transistor substrate voltages using a voltage control substrate means.

Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

Abstract: Low power CMOS circuit provided with CMOS devices, is disclosed, for minimizing a power consumption in a standby mode, including PMOS transistors having drains connected to a power supply voltage and NMOS transistors having sources connected to a ground voltage, both of the PMOS transistors and the NMOS transistors being adapted to be applied of a back bias voltage in a standby mode, wherein the PMOS transistors and the NMOS transistors are formed to have high gamma factors.

Abstract: A level shift circuit capable of performing a low voltage operation without increasing the power consumption is described. A charge pump type level shift circuit incorporates NMOS transistors having well-in-well structures, where the potential of these wells are designed to rise along with the rise of the output voltage. The level shift circuit is capable of eliminating a back-bias effect and can lower the power source voltage to as low as 2V.

Abstract: A switching circuit includes a switch having first and second terminals coupled between a voltage supply and ground potential and having a control terminal coupled to receive a control signal indicative of the output voltage of an associated semiconductor circuit. The switch also includes an output terminal coupled to the well region within which is formed the associated semiconductor circuit. In preferred embodiments, the control signal transitions from a first state to a second state when the output voltage exceeds a predetermined potential. In response thereto, the switching circuit changes the well potential of the associated semiconductor circuit from a first voltage to ground potential, wherein the first voltage is greater than ground potential.

Abstract: An improved off-chip driver circuit is disclosed which will properly transition from an active mode to a high impedance mode. The circuit includes first and second input nodes for receiving a first and second input signal respectively. An input composite transmission gate including a p-channel transistor in parallel with an n-channel transistor to receive the first input signal is provided in the circuit. A push-pull circuit is also included which includes the pull-up transistor disposed between a voltage supply and an output node and a first pull-down transistor disposed between ground and the output node. The pull-up transistor has a gate electrode for receiving the first input signal provided by the input composite transmission gate. The first pull-down transistor has a gate electrode for receiving the second input signal. A control transistor is included and is coupled between the gate electrode of the pull-up transistor and the output node.

Abstract: In a charge pump circuit, the issues of increase in loss due to the backgating effect, increase in cost, risks of latch-up and charge leak and the like, which would be involved in achieving voltage reduction, are resolved with a simple circuit structure. A pump cell 31 has nMOS transistors M1-M3 and capacitors C1, C2. An auxiliary capacitor C is connected to an input node IN, and further p-well portions of the nMOS transistors M1-M3 are connected to this auxiliary capacitor C, the nMOS transistor M3 is interposed between each p-well portion and output node OUT, and the input node IN is connected to the gate of the nMOS transistor M3. Thus, with a simple circuit structure which involves only the use of the auxiliary capacitor C, voltage difference of the push-down of the p-well voltage is increased so that the deterioration of pump efficiency due to the backgating effect in the voltage reduction of power supply voltage is eliminated and that latch-up and charge leak are prevented.

Abstract: A method, and related circuit, prevent the triggering of a parasitic transistor in an output stage of an electronic circuit. The stage includes a transistor pair with at least one transistor of the pull-up PMOS type having respective source, gate and drain terminals and a body terminal, and a parasitic bipolar transistor having a terminal connected to the body terminal. The method includes the steps of providing a capacitor connected between the body and source terminals of the PMOS transistor; and using a control circuit to suppress the body effect of the pull-up PMOS transistor.

Abstract: To provide a semiconductor integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which one transistor Tp for constituting the CMOS circuit is set, with a first power-supply-voltage line Vdd through a switching transistor Tps, and electrically connecting a p-type well 3 in which the other transistor Tn for constituting the CMOS circuit is set with a second power-supply-voltage line Vss through a switching transistor Tns. Moreover, the semiconductor integrated circuit is constituted so that thermal runaway due to leakage current can be controlled by turning off the switching transistors Tps and Tns and supplying a potential suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the semiconductor integrated circuit is being tested.

Abstract: When a power supply terminal (10) is grounded, a circuit (101) is in the OFF state, and a high potential is transferred from a circuit (3) to a bus line (BL), the high potential is transferred to a node (100) via the source of a transistor (P1), back gate (Nw), and transistor (P2). A NAND circuit (NA1) always outputs a control signal (VGP) of a level equal to the node (100) to the gate of the transistor (P1) to turn non-conductive the transistor (P1). Hence, a current path from a terminal (B) to a terminal (A) or from the terminal (B) to the back gate (Nw) is cut off to prevent wasteful current consumption.

Abstract: A logic circuit which is driven at low voltage and operates at high speed and low power consumption is provided. Substrate potentials of P and N type transistors MP11 and MN11 constituting an inverter are controlled correspondingly to a stable state of the inverter. In a stable state of the inverter in which the P type transistor MP11 is ON, the substrate potential of the N type transistor MN11 which is OFF is lowered to ground potential or lower and, in a stable state of the inverter in which the N type transistor MN11 is ON, the substrate potential of the P type transistor MP11 which is OFF is raised to a power source potential or higher.

Abstract: A high voltage tolerant CMOS input/output interface circuit. In this circuit, a process feature called “dual-gate” or “thick-oxide” process is used on any devices that will be exposed to high voltage. The thick-oxide devices have a larger capacitance and lower bandwidth, and therefore, preferably, they are only used where exposure to high voltage can cause damage. The remaining devices on the interface circuit may all use a standard process with the thinner oxide, allowing the I/O and the core IC to run at maximum speed. The circuit design topology also limits the number of devices that are exposed to high voltage. Preferably, the protection scheme is broken down into two parts: the driver and receiver.

Abstract: A Silicon-On-Insulator (SOI) CMOS circuit comprises a plurality of PMOS transistors connected in series to each other, each of the plurality of PMOS transistors having its body and gate connected to each other, and at least an NMOS transistor connected to one of the plurality of PMOS transistors, the NMOS transistor having its body connected to a low reference potential having a value of ground. The SOI CMOS circuit can further comprise a plurality of potential limiting circuits each connected between the body and gate of each of the plurality of PMOS transistors, for setting a lower limit of the potential of the body of each of the plurality of PMOS transistors to a voltage between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a MOS transistor formed on the semiconductor substrate and having a first gate, wherein a first signal supplied to the first gate and a second signal supplied to a substrate region corresponding to the semiconductor substrate are combined with each other so that one logical signal is transmitted.

Abstract: A boosting stage of a charge pump circuit has a boosting capacitor connected to a boosted node and an n-channel enhancement type field effect transistor connected between the boosted node and other node and fabricated on a p-type well connected to the other node, and the n-channel enhancement type field effect transistor turns on for discharging current from the other node to the boosted node through the conductive channel and the p-n junction between the p-type well and the n-type source node thereof so that the potential level at the p-type well restricts the back-gate biasing effect, thereby widely swinging the potential level at the other node.

Abstract: A back bias generator for a semiconductor device improves refresh characteristics, reduces leakage current, and increases back bias supply capacity in a DRAM having a triple well structure by applying a well bias voltage to the bulk of an NMOS transfer transistor. The back bias generator includes a well bias generator that generates the well bias voltage before the pumping voltage is applied to the transfer transistor. The well bias provides a back bias to a parasitic NPN transistor formed in the triple well of the NMOS transfer transistor, thereby preventing leakage through the NPN into the substrate. The well bias is also applied to the bulk of a clamp transistor that initializes a pumping capacitor.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor (N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.

Abstract: A DC/DC converter including a switching transistor, an inductor, a smoothing capacitor, and a switching element which are connected so as to convert an input voltage U.sub.E to an output voltage U.sub.A greater or less than the input voltage U.sub.E. The current through the inductor can be measured by providing a comparator having a first input connected to the switching transistor, and a second input connected to a reference transistor and a reference current source so as to fix the switching threshold of the comparator at the second input.

Abstract: A semiconductor integrated circuit comprises a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltage of the p-channel and n-channel MIS transistors, and a second oscillation circuit which produces multiple reference clock signals of different frequencies depending on the operation mode. The control circuit receives a reference clock signal and controls the first oscillation circuit with the control signal so that the oscillation frequency of the first oscillation circuit is correspondent to the frequency of the reference clock signal.

Abstract: The present invention includes a semiconductor circuit including one or more transistors each having a body and one or more a variable voltage source to selectively provide a forward bias to the bodies at certain times and to provide a non-forward bias to the body at other times. The semiconductor circuit includes voltage control circuitry to control whether the variable voltage source provides the forward bias or the non-forward bias. In some embodiments of the invention, the voltage control circuit controls the variable voltage source such that the forward bias is provided during an active mode of the transistors and the non-forward bias is provided during a standby mode of the transistors. In some embodiments of the invention, the voltage control circuitry derives a priori knowledge of the mode of the transistor.

Abstract: A silicon-on-insulator digital circuit combination having a body voltage control stage and a voltage clamp stage. The body voltage control stage is responsive to an input control signal to provide an output driver signal. The body voltage control stage has a first transistor with a terminal for electrically-coupling to a combinational logic circuit, and a body contact electrically-coupled to the input control signal such that a threshold voltage of the transistor is reduced when the transistor is placed in an active state. It can be readily appreciated that the reduced threshold voltage of the transistor increases the transition rate for the first transistor to an inactive state in response to the input control signal. The voltage clamp stage has a second transistor responsive to the input control signal such that the terminal is electrically-coupled to a reference voltage when the first transistor is in the inactive state.

Abstract: An efficient charge pump circuit. Increased efficiency compared to previous pump circuits is achieved through use of a novel charge transfer switch and associated clocking scheme which reduces the supply current required to operate the charge pump. Instead of repeatedly charging and discharging a stray capacitance of each pump stage capacitor, some of the charge stored in the stray capacitor on the clock driver side is transferred to the next pump stage. This serves to pre-charge the stray capacitor of the next stage, reducing the supply current required to operate the charge pump. The apparatus and method described can also be used to reduce the power consumed by a system or circuit which has internal signals or nodes which are in opposite phase to each other. This is accomplished by reducing the power used to charge and discharge a stray capacitance associated with the signals or nodes.

Abstract: Methods and apparatus are provided for body control in silicon-on-insulator (SOI) domino circuits. The silicon-on-insulator (SOI) domino circuit includes a clock input and an input transistor stack including a plurality of input transistors. Each of the plurality of input transistors receives a data input. An intermediate precharge node is connected to the input transistor stack. An output inverter is connected to the intermediate precharge node. The output inverter includes a pair of silicon-on-insulator (SOI) transistors. A clocked transistor is connected to a body of at least one of the pair of silicon-on-insulator (SOI) transistors. The clocked transistor predischarges the body of the SOI transistor. Another clocked transistor is connected between ground and a body of an evaluate transistor connected to the input transistor stack. The body of the evaluate transistor is predischarged by the clocked transistor.

Abstract: An integrated device for a switching system is disclosed. The device includes control circuitry for generating at least one switching control signal, reference circuitry for generating at least one reference quantity, a using circuit for using the reference quantity, a circuit for storing the reference quantity, and a switch which, in a first operative condition, connects the reference circuit to the using circuit and to the storage circuit in order to apply the reference quantity thereto. In a second operative condition, the switch disconnects the reference circuit from the using circuit and connects the storage circuit to the using circuit in order to apply the stored reference quantity thereto. Finally, the device includes filtering circuitry for keeping the switch in the second operative condition for a filtering period in accordance with the switching of the control signal.

Abstract: An apparatus and method for controlling the power consumption of a logic device are implemented. The power dissipation, and consequently, the speed of a complementary metal oxide semiconductor (CMOS) logic device is substantially proportional to the speed of the device. The temperature of the logic device is controlled by controlling the device speed by adjusting the threshold voltage of the metal oxide semiconductor (MOS) devices forming the logic device under control. The threshold voltage of the devices is controlled by applying a back bias voltage between the bulk material in which each device under control is fabricated, and the most positive electrode of the device. The back bias voltage value is regulated in response to the logic device temperature, thereby closing a feedback loop.

Abstract: A driver circuit has an input terminal at which a first signal having a first voltage swing is applied, and an output terminal at which: (i) a second signal having a second voltage swing is provided to external circuitry, and (ii) a third signal having a third voltage swing is received from the external circuitry. A level shifter circuit is coupled to the input terminal and translates the first signal to the second signal. The level shifter circuit includes circuitry which regulates the switching rate of the driver circuit. An output circuit is coupled between the level shifter circuit and the output terminal which drives the external circuitry with the second signal received from the level shifter circuit. The output circuit has a floating well, and a bias circuit is coupled between the output terminal and the well of the output circuit. The bias circuit biases the well proportional to the third voltage swing when the third signal is received at the output terminal.

Abstract: A charge pump circuit operable with at least first to fourth phase clock signals. The charge pump circuit includes charge transfer devices connected in series through nodes. The charge transfer devices are connected to first side capacitors which are applied with second and fourth phase clock signals alternately so as to control charge transfer operations of the charge transfer devices with the second and fourth phase clock signals. The nodes are connected to second side capacitors which are applied with first and third clock signals. Each of the charge transfer devices includes a charge transfer field effect transistor connected in series between adjacent two of the nodes on opposite sides of the each charge transfer device and a boosting field effect transistor connected in series between a gate of the charge transfer field effect transistor and an input side one of the adjacent two nodes.

Abstract: An integrated circuit substrate bias pumping arrangement includes a charge pump circuit arranged as a circuit path from an oscillator input to a substrate. The charge pump circuit operates to supply charge to the substrate in response to a level of the oscillator signal. In the charge pump circuit, a pumping transistor transfers stored charge from a pumping capacitor to the substrate without imparting all of a threshold voltage of the pumping transistor as a voltage loss. The pumping transistor has its conduction path connected in a series circuit between the pumping capacitor and the substrate. A control gate electrode of the pumping transistor is bootstrapped to turn on the pumping transistor by a delayed version of the input signal used for pumping stored charge from the pumping capacitor to the substrate. Two of the charge pump circuits can be operated in a push-pull configuration, substrate bias pump.