Abstract: The present disclosure provides a memory circuit. The memory circuit includes: a plurality of word lines, a word line driver, and a first conductive line. The word line driver is electrically connected to the word lines. The word line driver includes: a plurality of first electronic components and a plurality of second electronic components. The plurality of first electronic components each electrically connected to the corresponding word line. The plurality of second electronic components each having a first terminal and a second terminal. The first terminal is electrically connected to the corresponding word line and the corresponding first electronic component. The first conductive line is electrically connected to the second terminal of the second electronic components. The first conductive line has a length proportional to the number of the word lines.

Abstract: Disclosed herein are related to memory device including an adaptive word line control circuit. In one aspect, the memory device includes a memory cell and a word line driver coupled to the memory cell through a word line. In one aspect, the memory device includes an adaptive word line control circuit including two or more diodes connected in series, where one of the two or more diodes is coupled to the word line.

Abstract: A power conversion module can include: an i-th level structure comprising 2i-1 basic units, a second terminal of each basic unit in each level structure respectively connected to first terminals of two basic units in a next level structure, where a first terminal of a first basic unit in a first-level structure is used as a first terminal of the power conversion module; an N-th level structure comprising 2N-1 balance units, where second terminals of each balance unit are connected as a second terminal of the power conversion module, and second terminals of each basic unit in an (N?1)th level structure are respectively connected to first terminals of two balance units in the N-th level structure; and where each basic unit comprises a switched capacitor circuit, N is a positive integer greater than or equal to 2, i is a positive integer, and 1?i?N?1.

Abstract: A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.

Abstract: Radio-frequency (RF) switching devices having improved voltage handling capability. In some embodiments, a switching device can include a first terminal and a second terminal, and a plurality of switching elements connected in series to form a stack between the first terminal and the second terminal. The switching elements can have a non-uniform distribution of a parameter that results in the stack having a first voltage handling capacity that is greater than a second voltage handling capacity corresponding to a similar stack having a substantially uniform distribution of the parameter.

Abstract: A power voltage supply device, including a reference bias voltage generating circuit, a temperature compensation bias voltage generating circuit, a compensation voltage generator, and a voltage buffer, is provided. The reference bias voltage generating circuit generates a reference bias voltage. The temperature compensation bias voltage generating circuit generates a temperature compensation bias voltage that changes as temperature rises. The compensation voltage generator generates a first power voltage based on the reference bias voltage, and selectively boosts the first power voltage based on the temperature compensation bias voltage. An input terminal of the voltage buffer receives the first power voltage. The voltage buffer generates a second power voltage corresponding to the first power voltage to a load circuit.

Abstract: A non-volatile memory device is provided. The non-volatile memory device may include a memory cell array, a first pumping circuit configured to output a first pumping voltage, a second pumping circuit configured to pump the first pumping voltage of the first pumping circuit to output a second pumping voltage, and a pumping circuit control unit which is connected to the first pumping circuit and the second pumping circuit and configured to output at least one of the first pumping voltage and the second pumping voltage to the memory cell array. The first pumping circuit may be enabled in a first mode and a second mode different from the first mode, and the second pumping circuit may be disabled or not enabled in the first mode and enabled in the second mode.

Abstract: An output stage circuit including a current source circuit, a bias circuit, and an output circuit is provided. The bias circuit is coupled between the current source circuit and a ground terminal voltage. The output circuit includes a first transistor, a second transistor, a third transistor, and a load circuit. A control terminal of the first transistor is coupled to the bias circuit. The load circuit is coupled to a second terminal of the first transistor. A second terminal of the second transistor is coupled to a first terminal of the first transistor. A first terminal of the third transistor is coupled to the second terminal of the first transistor.

Abstract: A voltage generator and a voltage generating method are provided. The voltage generator includes at least one first charge pump circuit, at least one second charge pump circuit, an oscillator, a passing circuit, and a voltage detector. The first charge pump circuit is configured to receive a clock signal to generate a first pump voltage. The second charge pump circuit is configured to receive the clock signal to generate a first pump voltage. The oscillator is configured to provide the clock signal. The passing circuit is configured to receive the clock signal, a power-on detection signal and an external command. The voltage detector is configured to receive an operation voltage, and generate the power-on detection signal by detecting the operation voltage. The passing circuit determines whether to transmit the clock signal to the second charge pump circuit or not to activate or deactivate the second charge pump circuit.

Abstract: Methods related to radio-frequency (RF) switching devices having improved voltage handling capability. In some embodiments, a method for fabricating an RF switching device can include: providing a semiconductor substrate; forming a plurality of field-effect transistors (FETs) on the semiconductor substrate such that the FETs have a non-uniform distribution of a parameter; and connecting the FETs to form a stack, such that the non-uniform distribution results in the stack having a first voltage handling capacity that is greater than a second voltage handling capacity corresponding to a similar stack having a substantially uniform distribution of the parameter.

Abstract: A power supply circuit and a field emission electron source are provided. The power supply circuit includes: field effect transistors Si coupled in series via drains and sources in sequence, 1?i?n, i and n are natural numbers, n?2, and a source of S1 is coupled to a negative electrode of a voltage source, and a drain of Sn is used as an output terminal of the power supply circuit to couple to a load; a first group of diodes D1i coupled in series; a first group of resistors R1j, 2?j?n, and i and j are natural numbers; and a voltage control module configured to adjust an output voltage of the voltage source to cause a current passing through the load to be constant; the field effect transistors Si, 1?i?n, operate in a resistive region.

Abstract: A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes and a second pair of output nodes, and two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes and a second bipolar output voltage at the second pair of bipolar output nodes.

Abstract: An image sensor including: a pixel array including first and second pixels connected to a column line; a row driver to provide the first pixel with a first selection signal based on a clamp voltage, and to provide the second pixel with a second selection signal based on a selection voltage, wherein the first pixel outputs a first output voltage in response to the first selection signal, and the second pixel outputs a second output voltage in response to the second selection signal, wherein the first and second output voltages are output as a pixel signal through the column line, wherein a voltage of the pixel signal corresponds to a voltage obtained by clamping the second output voltage with the first output voltage, and wherein a change in a voltage level of the first output voltage due to a temperature is compensated for by the clamp voltage.

Abstract: The disclosure provides a voltage regulator with a soft-start effect. The voltage regulator includes an amplifier, a first voltage setting circuit, a voltage selector and a power transistor. The amplifier has two input terminals to receive respectively a reference voltage and a feedback voltage. The amplifier has a current source to provide a current to an output terminal. In a voltage bypass mode, the first voltage setting circuit increases a driving voltage on the output terminal according to the current based on a selection voltage. In the voltage bypass mode, the voltage selector sequentially reduces the selection voltage respectively in multiple time intervals in a startup time interval. The power transistor receives the driving voltage, and generates an output voltage according to the driving voltage based on an operating power supply.

Abstract: A voltage generating circuit includes a first transistor and a second transistor. Voltage of a substrate of the first transistor varies with a first parameter. The first parameter is any one of a supply voltage, an operating temperature, as well as a manufacturing process of the voltage generating circuit. A gate of the first transistor is connected to a drain of the first transistor. The substrate of the first transistor serves as an output of the voltage generating circuit. A gate of the second transistor is connected to a drain of the second transistor.

Abstract: An example apparatus for writing a bit to a memory cell includes wordline driver circuitry configured to generate a first voltage in response to a row access enable signal. The apparatus also includes boost driver circuitry coupled to the wordline driver circuitry. The boost driver circuitry is configured to charge a capacitor using the first voltage and to generate a second voltage using the first voltage and a voltage at the capacitor in response to a boost enable signal. The apparatus also includes a wordline coupled to the memory cell and the wordline driver circuitry. The wordline is configured to output the first voltage or the second voltage to the memory cell.

Abstract: A charge pump circuit is provided. The charge pump circuit includes a dual-phase charge pump, a first load switch, a second load switch, and a control circuit. The dual-phase charge pump performs a voltage pumping operation on a power source in response to a first clock and a second clock to generate a first pumping voltage at a first node and a second pumping voltage at a second node. The control circuit controls the first load switch in response to a third clock and controls the second load switch in response to a fourth clock. In a period during which the first load switch is turned off, the second load switch transfers the first pumping voltage to an output terminal of the charge pump circuit. In a period during which the second load switch is turned off, the first load switch transfers the second pumping voltage to the output terminal.

Abstract: A diode voltage from a diode circuit can be combined with a proportional to absolute temperature (PTAT) voltage generated by a PTAT circuit to determine a temperature sensor voltage. This temperature sensor voltage may correspond to a temperature of a circuit or a localized temperature. By determining the temperature sensor voltage using a combination of a PTAT voltage and diode voltage, it is possible to remove or a PTAT circuit used to generate a bandgap voltage, which may shrink the temperature sensor and increase the accuracy of the temperature sensor circuit.

Abstract: A semiconductor storing apparatus and a flash memory operation method, for shortening a recovery time from a deep power-down (DPD) mode without a dedicated command for the DPD are provided. A flash memory includes: a standard command interface circuit and a DPD controller, operating through an external power voltage; a voltage supply node, for supplying power from the external power voltage via a first current path; a voltage supply node, for supplying power from the external power voltage via a second current path; an internal circuit group, connected to the voltage supply node; and a charge pump circuit, connected to the voltage supply node. When the DPD mode is released, the internal circuit group is enabled after the charge pump circuit is enabled.

Abstract: An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gate or routing lines that extend across the face of the display and that are formed in a low resistance source-drain metal routing layer. Forming routing/gate lines using the low resistance source-drain metal routing layer dramatically reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.

Abstract: Methods and apparatus for a signal isolator having reduced parasitics. An example embodiment, a signal isolator and include a first metal region electrically connected to a first die portion, a second die portion isolated from the first die portion, and a second metal region electrically connected to the second die portion. A third metal region can be electrically isolated from the first and second metal regions and a third die portion can be electrically isolated from the first, second and third metal regions. In embodiments, the first metal region, the second metal region, and the third metal region provide a first isolated signal path from the first die portion to the second die portion.

Abstract: Aspects of the invention include a first voltage sensitive circuit including first transistors, the first transistors being coupled together so as to be operatively coupled to a first current source. A second voltage sensitive circuit includes second transistors, the second transistors being coupled together so as to be operatively coupled to a second current source, the first voltage sensitive circuit being coupled to the second voltage sensitive circuit to form a delay chain, the first and second current sources being responsive to changes in voltage of a power supply according to a voltage reference. A voltage sensitive current reference module is coupled to the first and second current sources and configured to supply the voltage reference to the first and second current sources, the voltage sensitive current reference module being responsive to changes in the voltage of the power supply.

Abstract: Disclosed herein is a driver integrated circuit (IC), which can be miniaturized and includes a plurality of circuits, including a first substrate, a first circuit driven at a first level voltage and mounted on the first substrate, a second substrate bonded to the first substrate, and a second circuit including one or more sub-circuits driven at a second level voltage that is higher than the first level voltage, wherein at least one among the one or more sub-circuits is mounted on the second substrate.

Abstract: In an embodiment, a circuit provided by the present invention includes a transistor connected to allow current to flow from a voltage supply to an output port. The circuit further includes a resistance ladder digital-to-analog converter (RDAC) configured to receive a digital input that indicates a voltage scaling factor. The RDAC is further configured to receive an input voltage (VB) at a voltage input port and produce an output voltage (VA). The circuit further includes an amplifier having an output port connected to a gate of the first transistor, an inverting input port receiving the output voltage (VA), and a non-inverting input connected to the output port of the first transistor.

Abstract: The present technology includes a voltage generator and a memory device including the voltage generator. The voltage generator includes an operation code determiner configured to output a clock control code including the number of planes in response to an operation code, a clock group configured to simultaneously generate clocks having different periods according to the clock control code, and a pump group configured to perform a pumping operation according to the clocks and output operation voltages.

Abstract: A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

Abstract: A high voltage generating circuitry includes a charge-pump and control loop; the control loop includes a voltage divider which receives a high voltage and provides a divided high voltage output. A first circuit element provides a first voltage difference signal. A controller generates a feedback signal based on the first voltage difference signal. An oscillator generates clock signals for operating the charge-pump circuitry, with the frequency of the clock signals being controlled with a control signal. A feedforward path with a second circuit element combines a second reference voltage and a second voltage generated by inverting the supply voltage for obtaining a second voltage difference signal. A third circuit element generates a feedforward compensation signal inversely proportional to a voltage difference between the supply voltage and the second reference voltage. A fourth circuit element generates the control signal by summing the feedback signal and the feedforward compensation signal.

Abstract: A memory device may include one or more memory banks that store data and one or more input buffers. The input buffers may receive command address signals to access the one or more memory banks. The memory device may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers may operate under a first bias current when the memory device is in the first mode of operation or a second bias current when the memory device is in the second mode of operation, and the first bias current may be greater than the second bias current.

Abstract: A voltage-to-time-to-digital converter (VTDC) and conversion method are provided using a coarse analog-to-digital converter (ADC). A voltage-to-time converter (VTC) receives an analog input voltage-differential signal with a first time duration and supplies an analog first time-differential signal. An ADC receives the input voltage-differential signal and supplies a first digital code representing m bit values. A time-to-digital converter (TDC) receives a second time-differential signal with a second time duration derived from the first time duration. The TDC supplies an output digital code representing p bit values, where p>m. In one aspect the first digital code programs an initial set of TDC residue generators. In another aspect, a dither circuit controls the second time duration in response to a pseudo random signal combined with the first digital code.

Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.

Abstract: A voltage converting circuit and a control circuit thereof are provided. The control circuit includes a comparator, a clock generator, and a boost circuit. The comparator compares an input voltage with an output voltage to generate a comparison signal. The clock generator generates a clock signal according to the comparison signal to enable the clock signal to have a first frequency in a first time interval and to have a second frequency in a second time interval. The first frequency is higher than the second frequency. The first time interval occurs before the second time interval. The boost circuit receives the clock signal, pulls up a control signal of a driving switch in the first time interval according to a first driving capability, and generates the control signal in the second time interval according to a second driving capability. The first driving capability is greater than the second driving capability.

Abstract: Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.

Abstract: A charge pump circuit includes a voltage output terminal, a flying capacitor, and a current source. The flying capacitor includes a first terminal coupled to the voltage output terminal, and a second terminal coupled to an output terminal of a drive circuit. The current source includes a first terminal coupled to the voltage output terminal, and a second terminal coupled to a power supply rail.

Abstract: A charge pump drive circuit is disclosed. The charge pump drive circuit provides a switch signal to a charge pump which provides a memory with a read voltage and a read current. The charge pump drive circuit includes a read drive circuit and a standby drive circuit. The read drive circuit is powered by a first power supply and provides the charge pump with a switch signal when the memory is in an active reading state. The standby drive circuit is powered by a second power supply and provides the charge pump with a switch signal when the memory is in a read standby state. The first power supply provides a voltage level ranging from 1.6 V to 3.8 V, and the second power supply provides a voltage level of 1.5 V.

Abstract: A processor-implemented method to detect a battery fault includes obtaining first states of detection targets in a battery, generating a representative state based on the first states, generating second states by applying the representative state to each of the first states, generating one or more third states by amplifying at least a portion of the second states, and detecting for a fault of the battery based on the one or more third states.

Abstract: Power amplifiers, amplifier systems, and related methods are disclosed herein. In one example embodiment, the amplifier system includes a bias controller that enables fast switching between an on state bias voltage and an off state bias voltage for the power amplifier. The bias controller can transition a low impedance switch to an on state to electrically couple a first electrode of a charge holding capacitor to an input of the power amplifier. The charge holding capacitor can be pre charged with the on state bias voltage to quickly provide the on state bias voltage to the power amplifier. The bias controller can also transition the low impedance switch to an off state to couple the input of the power amplifier to the off state bias voltage.

Abstract: A comparator circuit includes a first transistor have a control electrode coupled to a first input voltage, a first current electrode coupled to a second input voltage, and a second current electrode coupled to a first circuit node. The circuit also includes a first inverter coupled to a first voltage supply terminal and having a first input coupled to the first circuit node and an output, a second transistor having a control electrode coupled to the output of the first inverter, and an active resistive element coupled in series between the first circuit node and a first current electrode of the second transistor.

Abstract: Methods and systems described herein perform a secure transaction. A display presents images that are difficult for malware to recognize but a person can recognize. In at least one embodiment, a person communicates transaction information using visual images received from the service provider system. In at least one embodiment, a universal identifier is represented by images recognizable by a person, but difficult for malware to recognize. In some embodiments, methods and systems are provided for determining whether to grant access, by generating and displaying visual images on a screen that the user can recognize. In an embodiment, a person presses ones finger(s) on the screen to select images as a method for authenticating and protecting communication from malware. In at least one embodiment, quantum randomness helps unpredictably vary the image location, generate noise in the image, or change the shape or texture of the image.

Abstract: A multi-mode charge pump generates a regulated voltage at an output node from a battery input voltage. The multi-mode charge pump has a plurality of flying capacitors and a plurality of switches coupled to the flying capacitors in order to selectively couple the flying capacitors to the battery, the output node or a reference potential. The regulated voltage is provided across a storage capacitor coupled to the flying capacitors, and the regulated voltage is input to a comparator. The comparator also receives a reference voltage and compares the regulated voltage to the reference voltage to generates an asynchronous regulation signal. A controller in the multi-mode charge pump can automatically transition between operation modes such as a buck mode, a doubler mode and a tripler mode by controlling actuation of the switches in response to the asynchronous regulation signal and clock signals.

Abstract: A charge leveler coupled between an external power supply and a data storage device includes a current limiter to receive an input current from the external power supply and to provide a limited input current at no more than a pre-determined level. A charge reservoir couplable in parallel with an output of the current limiter supplements the limited input current when the pre-determined level is exceeded. The charge reservoir is replenished with surplus limited current when the data storage device draws less than the pre-determined level. A boost assist regulator monitors a requested current from the data storage device, and initiates operation of the charge reservoir to supplement the limited input current when the requested current exceeds the limited input current.

Abstract: An internal voltage generation circuit includes a counting operation control signal generation circuit and a drive control signal generation circuit. The counting operation control signal generation circuit compares a test internal voltage with a test reference voltage to generate a counting operation control signal in a test mode. The drive control signal generation circuit generates a drive adjustment signal whose logic level combination is adjusted according to the counting operation control signal in the test mode. In addition, the drive control signal generation circuit compares the test internal voltage with the test reference voltage in the test mode to generate a drive control signal for driving the test internal voltage.

Abstract: The present disclosure discloses a battery device including a battery, a charging and discharging switch unit configured to control charging and discharging of the battery, a pre-charging unit configured to be charged during discharging of the battery, and a discharging unit configured to discharge the charge charged in the pre-charging unit.

Abstract: The present invention is provided with; subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKK1 or VKK2 to the subword drivers SWD, and memory cells MC that are selected in the case when the subword line SWL is set to an active potential VPP and are not selected in the case when the subword line SWL is either a negative potential VKK1 or VKK2.

Abstract: Provided is an electronic device which can easily measure a standby current of an internal circuit of an electronic device after burn-in. The electronic device includes: a power source terminal; a regulator that generates a predetermined voltage from a voltage of the power source terminal; an internal circuit that is operated by an output voltage of the regulator; and a standby terminal through which the regulator and the internal circuit are set to a low power consumption state.

Abstract: Disclosed is a voltage generator that includes a first voltage generation circuit and a second voltage generation circuit. The first voltage generation circuit is selectively operable in a single trimming mode enabling positive trimming only or in a dual trimming mode that shifts the voltage range downward enabling a somewhat smaller amount of positive trimming and also some negative trimming. The second voltage generation circuit is selectively operable in a single trimming mode enabling negative trimming only or in a dual trimming mode that shifts the voltage range upward enabling a somewhat smaller amount of negative trimming and also some positive trimming. Also disclosed is an integrated circuit (IC) chip that incorporates one or more such voltage generators for back-biasing the field effect transistors in one or more circuit blocks, respectively.

Abstract: A single integrated circuit DC-to-DC conversion solution that can be used in conjunction with product designs requiring at least two different DC-to-DC conversion ratios, and in particular both divide-by-2 and divide-by-3 DC-to-DC buck conversion ratios or both multiply-by-2 and multiply-by-3 DC-to-DC boost conversion ratios. Embodiments are reconfigurable between a first Dickson converter configuration that includes at least two non-parallel capacitors (any of which may be off-chip) and associated controlled multi-phase switching to achieve a first conversion ratio, and a second Dickson converter configuration that includes a lesser equivalent number of capacitors than the first circuit configuration (which may be accomplished by parallelizing at least two non-parallel capacitors of the first configuration) and associated controlled multi-phase switching to achieve a second conversion ratio different from the first conversion ratio.

Abstract: A single stage voltage quadrupler circuit includes a first capacitive voltage boosting circuit responsive to a first clock signal and operable to boost a voltage at a first node in response to the first clock signal from a first voltage level to a second voltage level that is substantially two times the first voltage level. A pass transistor selectively passes the boosted voltage at the first node to a second node in response to a control signal generated by a bootstrapping capacitor circuit in response to the level shifted first clock signal. A second capacitive boosting circuit is operable to boost the voltage at the second node in response to a level shifted second clock signal that is the logical invert of the level shifted first clock signal to third voltage level that is substantially four times the first voltage level.

Abstract: An apparatus includes a voltage regulation module configured to provide an output voltage signal (Vout) and an auto-calibration module configured to provide a calibration current signal (Isink) corresponding to a voltage difference between a target voltage signal (Vtarget) and the output voltage signal (Vout). The voltage regulation module may adjust the output voltage in response to changes in the calibration current signal. In one embodiment, the voltage regulation module comprises an output voltage resistor pair of resistance R1 and R2, respectively, and the output voltage signal conforms to the equation Vout=Isink·R1+Vref·(1+R1/R2).