With Field-effect Transistor Patents (Class 327/537)
  • Patent number: 10727831
    Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Lei Pan, Zhen Tang, Miranda Ma
  • Patent number: 10644701
    Abstract: An input output circuit and a self-biased circuit are provided. The self-biased circuit includes a tracking circuit, a biasing control circuit and first to fourth transistors. The tracking circuit receives a first power voltage, and generates a bias voltage according to variation of the first power voltage. The biasing control circuit generates a first control signal, a second control signal and a third control signal according to the first power voltage and a voltage on a pad. The first transistor is coupled to the pad and controlled by the first control signal. The second transistor is controlled by the second control signal to provide a bias voltage. The third transistor is coupled to the pad and controlled by the third control signal and generates a fourth control signal according to the voltage on the pad. The fourth transistor is controlled by the fourth control signal to generate the bias voltage.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 5, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Huang-Shiang Su, Chi-Sheng Liao, Jeng-Huang Wu
  • Patent number: 10536143
    Abstract: A system is disclosed. The system includes a first stage configured to receive VIN and VREF, the first stage including an input transistor pair, wherein the input voltage is coupled to the input transistor pair, the input transistor pair is coupled to ground, and the input transistor pair includes at a common drain a high-gain node having a voltage VHGN. The system further include a second stage coupled to the high-gain node and configured to generate VOUT based on a difference between VIN and VREF, the second stage comprising a resistor and an inverter transistor pair, wherein the gates of the inverter transistor pair are coupled to the high-gain node of the first stage and the resistor couples the high-gain node of first stage to a common drain of the inverter transistor pair and is configured to provide and/or draw current to and/or from the high-gain node of first stage.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: January 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Burt Lee Price, Dhaval Shah
  • Patent number: 10475407
    Abstract: A GOA circuit and a display device are provided. The GOA unit includes multiple GOA units, and each GOA unit includes a pull-up circuit for outputting a scanning driving signal of a current stage, a pull-down circuit including a first pull-down switch for pulling down the scanning driving signal of the current stage to a low voltage level, and a pull-down holding circuit including a first pull-down holding switch for holding the scanning driving signal of the current stage at a low voltage level. Each of the first pull-down switch and the first pull-down holding switch is a dual-gate TFT switch, a top gate electrode of each of the first pull-down switch and the first pull-down holding switch receives the first direct-current voltage. Accordingly, the present invention can reduce the current leakage, and increase the reliability of the entire GOA circuit.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: November 12, 2019
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd
    Inventor: Mian Zeng
  • Patent number: 10439599
    Abstract: Embodiments include circuits, apparatuses, and systems for non-boolean associative processors. In embodiments, an electronic associative processor circuit may include first and second ring oscillators, each having an odd number of inverters, an input terminal, and an output terminal. A first capacitor may have a first terminal coupled with the output terminal of the first ring oscillator and a second capacitor may have a first terminal coupled with the output terminal of the second ring oscillator. Second terminals of the first and second capacitors may be coupled at an oscillator stage output terminal. The inverters of the first and second ring oscillators may be implemented with metal oxide semiconductor transistors. Other embodiments may be described and claimed.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Dmitri E. Nikonov, Ian A. Young
  • Patent number: 10381489
    Abstract: The tunnel field effect transistor according to the present invention has: a channel; a source electrode connected directly or indirectly to one end of the channel; a drain electrode connected directly or indirectly to the other end of the channel; and a gate electrode for causing an electric field to act on the channel, generating a tunnel phenomenon at the source electrode-side joint part of the channel, and simultaneously generating a two-dimensional electron gas in the channel.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: August 13, 2019
    Assignees: National University Corporation Hokkaido University, Japan Science and Technology Agency
    Inventors: Takashi Fukui, Katsuhiro Tomioka
  • Patent number: 10326439
    Abstract: In some method and apparatus embodiments, an RF circuit comprises a switch transistor having a source, a drain, a gate, and a body. A gate control voltage is applied to the gate of the switch transistor. A body control voltage is applied to the body of the switch transistor. The body control voltage is a positive bias voltage when the switch transistor is in an on state. In some embodiments, an RF circuit comprises a control voltage applied to the gate of the switch transistor through a first resistance and applied to the body of the switch transistor through a second resistance. The first resistance is different from the second resistance.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Max Aubain, Clint Kemerling
  • Patent number: 10146238
    Abstract: A resistorless CMOS low power voltage reference circuit is provided. The start-up circuit is used to prevent the circuit to stay in the zero state and stop working when the circuit gets out of the zero state. The self-biased VPTAT generating circuit generate the voltage VPTAT which has positive temperature coefficient. The square-law current generating circuit generates a square-law current which is proportional to ?T2 through the VPTAT. Finally, the reference voltage VREF is obtained by introducing the square-law current into the reference voltage output circuit. The reference voltage VREF of this application can realize approximative zero temperature coefficient in the temperature range of ?40° C.˜100° C. This application improves temperature characteristic which may be poorer due to temperature nonlinearity of carrier mobility based on the traditional subthreshold reference. This application can reduce the power consumption from ?W level to nW level and realize low power consumption.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: December 4, 2018
    Assignee: University of Electronic Science and Technology of China
    Inventors: Zekun Zhou, Yao Wang, Jianwen Cao, Hongming Yu, Yunkun Wang, Anqi Wang, Zhuo Wang, Bo Zhang
  • Patent number: 10120967
    Abstract: A method for implementing a Semiconductor Integrated Circuit device using Near/Sub-threshold technology with SW programmable adaptive and dynamic forward and reverse bias voltage control using different sensors inside the chip in order to improve speed, reduce leakage and ensure high yield of the final product that operates at an ultra-low power consumption. This method allows achieving ultra-low power solution with reasonable higher speed and insure high yield.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: November 6, 2018
    Assignee: PLSense Ltd.
    Inventors: Uzi Zangi, Neil Feldman
  • Patent number: 10056898
    Abstract: An input stage of a chip includes a source driver and a sensing and clamping circuit. The source follower is arranged for receiving an AC-coupled signal to generate an output signal at an output terminal. The sensing and clamping circuit is coupled to the source follower, and is arranged for clamping the output terminal of the source follower at a fixed DC voltage.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: August 21, 2018
    Assignee: MEDIATEK INC.
    Inventor: Mu-Chen Huang
  • Patent number: 9779837
    Abstract: A command generation circuit, test control circuit, semiconductor device, semiconductor system, and or a test method may be provided. The semiconductor device may be configured to enter test modes and to generate internal commands during a clock cycle.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: October 3, 2017
    Assignee: Sk hynix Inc.
    Inventors: Myung Kyun Kwak, Tae Yong Lee, Geun Ho Choi
  • Patent number: 9705481
    Abstract: An integrated circuit device having a p-well plane, a plurality of substantially parallel n-well rows, and a logic cell. The p-well plane is comprised of p-type semiconductor material. Each n-well row comprises an n-type layer disposed on the surface of the p-well plane. The plurality of n-well rows includes a first n-well row and a second n-well row. The logic cell is arranged on the p-well plane and the footprint of the logic cell encompasses both the first and second n-well rows.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: July 11, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sudesh Chandra Srivastava, Vivek Singhal
  • Patent number: 9696747
    Abstract: An example a voltage regulator includes: a bias circuit coupled to an output node; a first operational amplifier having a first input coupled to the output node, a second input coupled to a reference voltage node, and an output coupled to a first node; a second operational amplifier having a first input coupled to the output node, a second input coupled to the reference voltage node, and an output coupled to a second node; an output transistor coupled between the output node and a ground node, the output transistor including a gate; first, second, and third stacked transistor pairs each serially coupled between the output node and the ground node, each transistor of the first, second, and third stacked transistor pairs including a gate; and switch circuits configured to selectively couple: the gates of the first and second stacked transistor pairs to the second node; and the gate of the output transistor to the first node.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: July 4, 2017
    Assignee: XILINX, INC.
    Inventors: Sing-Keng Tan, Wenyi Song
  • Patent number: 9531371
    Abstract: A method for at least partially compensating for a change in threshold voltage level of a FET transistor induced by OFF-state stress degradation includes determining a signal indicative of a change in threshold voltage level of the FET with respect to a reference threshold voltage level, and applying a restoration signal to the FET. This restoration signal is adapted for shifting the threshold voltage level of the FET in a direction having opposite sign with respect to the change in threshold voltage level. Applying the restoration signal further includes taking into account the signal indicative of the change in threshold voltage level.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: December 27, 2016
    Assignee: IMEC VZW
    Inventors: Alessio Spessot, Moon Ju Cho
  • Patent number: 9444660
    Abstract: A method for offset cancellation in a receiver loss of signal (RxLOS) circuit of a serializer/deserializer (SerDes) receiver device includes receiving a differential input signal via the first stage of a peak detector cell of the RxLOS circuit and shorting the differential output of the first stage via a control switch of the second stage of the RxLOS circuit. The control switch may further transition the RxLOS circuit from normal operating mode to an offset cancellation mode wherein the control switch may manually or automatically short the differential output of the first stage.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: September 13, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Shu Dong Cheng, Ming Chen, Yan Xu, Dong Hui Wang, Jun Tian
  • Patent number: 9419021
    Abstract: If the threshold of a thin film transistor is depleted, a leak-induced voltage drop takes place and the desired voltage cannot be obtained. Depending on the severity of the phenomenon, the thin film transistor may fail to function. This disclosure offers a thin film transistor circuit having a first transistor connected to a low voltage, and a second transistor connected to the gate of the first transistor. When the gate voltage of the second transistor is changed from the high level to the low level, the gate voltage of the first transistor is brought to a voltage level lower than the low voltage.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: August 16, 2016
    Assignee: Japan Display Inc.
    Inventors: Toshio Miyazawa, Takahide Kuranaga
  • Patent number: 9343959
    Abstract: Embodiments relate to circuits, systems and methods for providing interruption protection for sensors and other devices. One example embodiment includes an interruption protection circuit comprising at least one charge pump and at least one buffer capacitor configured to maintain and/or provide sufficient voltage for output signals of sensors or other devices during micro-breaks or other interruptions.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: May 17, 2016
    Assignee: Infineon Technologies AG
    Inventor: Dirk Hammerschmidt
  • Patent number: 9312755
    Abstract: Exemplary embodiments are directed to systems, devices, methods, and computer-readable media for reducing static and dynamic power consumption of a charge pump. In one embodiment, a device may include a plurality of switches, each switch of the plurality having a gate coupled to a dedicated driver of a plurality of drivers. The device may further include at least one clamp switch coupled to at least one driver of the plurality of drivers and configured to adjust a rail voltage of the at least one driver if an input voltage is greater than a threshold voltage. In another embodiment, the device may include a plurality of multiplexers, each multiplexer of the plurality of multiplexers coupled to a portion of an associated switch of the plurality of switches and configured to disable the portion of the associated switch if a clock frequency of the charge pump is below a threshold frequency.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: April 12, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Le Wang, Vijayakumar Dhanasekaran
  • Patent number: 9276561
    Abstract: An integrated circuit device can include at least one oscillator stage having a current mirror circuit comprising first and second mirror transistors of a first conductivity type, and configured to mirror current on two mirror paths, at least one reference transistor of a second conductivity type having a source-drain path coupled to a first of the mirror paths, and a switching circuit coupled to a second of the mirror paths and configured to generate a transition in a stage output signal in response to a stage input signal received from another oscillator stage, wherein the channel lengths of the first and second mirror transistors are larger than that of the at least one reference transistor.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: March 1, 2016
    Assignee: MIE Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, David A. Kidd, Chao-Wu Chen
  • Patent number: 9171121
    Abstract: A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Hanyi Ding, Alvin J. Joseph, Wayne H. Woods, Jr.
  • Patent number: 9158324
    Abstract: An integrated circuit includes a process voltage temperature (PVT) effect transducer responsive to a PVT effect, a PVT effect quantifier coupled to the PVT effect transducer and configured to quantify the PVT effect to provide an output, and a bias controller configured to receive the output of the PVT effect quantifier and provide a bias voltage for a substrate of an NMOS or a PMOS transistor. The bias controller is configured to compare the output received from the PVT effect quantifier to a threshold value, and decrease or increase the bias voltage depending on whether the output is higher or lower than the threshold value.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: October 13, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shyh-An Chi, Shiue Tsong Shen, Jyy Anne Lee, Yun-Han Lee
  • Patent number: 9143132
    Abstract: Apparatuses including termination for complementary signals are described, along with methods for terminating complementary signals. One such apparatus includes a termination transistor including a first node configured to receive a first complementary signal and a second node configured to receive a second complementary signal. A regulation circuit can generate a regulated voltage to render the termination transistor conductive with a substantially constant resistance. In one such method, a first complementary signal is received at a drain of a termination transistor and a second complementary signal is received at a source of the termination transistor. Energy of the complimentary signals can be absorbed when the termination transistor is rendered conductive. Additional embodiments are also described.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: September 22, 2015
    Assignee: Micron Technology, Inc.
    Inventors: William Kammerer, Kalyan Kavalipurapu
  • Patent number: 9088280
    Abstract: A body bias control circuit including an output coupled to provide a bias voltage to a body terminal. The body bias control circuit is configured to change the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time. For voltages between the first and second bias voltages closer to a source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: July 21, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Anis M. Jarrar, Stefano Pietri, Steven K. Watkins
  • Publication number: 20150145592
    Abstract: A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.
    Type: Application
    Filed: March 26, 2014
    Publication date: May 28, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Xia Li, Daeik Daniel Kim, Bin Yang, Jonghae Kim, Daniel Wayne Perry
  • Publication number: 20150137877
    Abstract: Provided is a bias circuit. The bias circuit includes: a first resistor connected between a ground terminal and a first node; a first bias transistor having a drain connected to the first node and a source connected to a second node; a second bias transistor having a drain connected to the second node and a source connected to a negative voltage terminal; a third bias transistor having a drain connected to the ground terminal and a source connected to a third node; and a second resistor connected between the third node and the negative voltage terminal, wherein a gate of the first bias transistor is connected to the second node; a gate of the second bias transistor is connected to the negative voltage terminal; a gate of the third bias transistor is connected to the first node; and a gate bias voltage signal is outputted through the third node.
    Type: Application
    Filed: June 19, 2014
    Publication date: May 21, 2015
    Inventors: Yun Ho CHOI, Youn Sub NOH, Hong Gu JI, Jin Cheol JEONG, In Bok YOM
  • Patent number: 9036443
    Abstract: A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: May 19, 2015
    Assignee: THE UNIVERSITY OF TOKYO
    Inventors: Ken Takeuchi, Teruyoshi Hatanaka, Koichi Ishida, Tadashi Yasufuku, Makoto Takamiya, Takayasu Sakurai
  • Patent number: 9024678
    Abstract: A circuit arrangement including a first transistor, a second transistor and a third transistor. The first transistor and the second transistor are configured so that the current flowing through the first transistor is proportional to the current flowing through the second transistor and the third transistor. The first transistor, the second transistor and the third transistor are configured to operate in an ohmic mode. The second transistor and the third transistor are coupled in series to each other. The first transistor, the second transistor and the third transistor match each other in at least one characteristic.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: May 5, 2015
    Assignee: Infineon Technologies AG
    Inventors: Daniele Vacca Cavalotto, Enrico Orietti
  • Publication number: 20150116030
    Abstract: A body bias control circuit including an output coupled to provide a bias voltage to a body terminal. The body bias control circuit is configured to change the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time. For voltages between the first and second bias voltages closer to a source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.
    Type: Application
    Filed: October 30, 2013
    Publication date: April 30, 2015
    Inventors: ANIS M. JARRAR, Stefano Pietri, Steven K. Watkins
  • Patent number: 9000751
    Abstract: In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate width and gate length of the transistor and gate width and gate length of the transistor are adjusted so that source-drain current flowing between the source and the drain of the transistor becomes equal to source-drain current flowing between the source and the drain of the transistor when the voltage applied to the input terminal is set to be preset trigger voltage. This configuration accomplishes detecting that the input voltage exceeds the trigger voltage with simple configuration.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Po-Hung Chen, Makoto Takamiya, Takayasu Sakurai
  • Patent number: 8988153
    Abstract: A low voltage ring oscillator circuit can have a frequency variation that depends on process variations of insulated gate field effect transistors (IGFETs) of a first conductivity type without substantially being affected by process variations to IGFETs of a second conductivity type. A ring oscillator stage may include an inverter including only IGFETs of the first conductivity type. The inverter may be coupled to a boot circuit that boosts the gate potential of a first IGFET of the first conductivity type with a timing such that IGFETs of the second conductivity type in the boot circuit do not affect the frequency variations of the ring oscillator circuit.
    Type: Grant
    Filed: March 9, 2013
    Date of Patent: March 24, 2015
    Assignee: SuVolta, Inc.
    Inventor: Richard S. Roy
  • Publication number: 20150070084
    Abstract: A semiconductor device includes an input-part receiving a first voltage and an output-part outputing a second voltage. A current mirror part receives the first voltage. A reference voltage is supplied to a gate of a reference transistor. The reference transistor is electrically connected between the current-mirror part and a ground voltage. A monitor transistor includes a gate electrically connected to the second power-supply voltage, and is electrically connected between the current-mirror part and the ground voltage. A voltage-generation transistor includes a gate electrically connected to both the current-mirror part and the reference transistor. The voltage-generation transistor is electrically connected between the input-part and the output-part. A first capacitor including one end electrically connected to the output-part, and the other end electrically connected to both the current-mirror part and the reference transistor.
    Type: Application
    Filed: March 10, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noriyasu Kumazaki, Yasufumi Kajiyama, Masaru Koyanagi
  • Patent number: 8975952
    Abstract: This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: March 10, 2015
    Assignee: Honeywell International Inc.
    Inventors: Paul S. Fechner, Weston Roper, James D. Seefeldt
  • Patent number: 8976606
    Abstract: A voltage generating circuit includes first and second step-up circuits, each having first and second input terminals and an output terminal and configured to increase a voltage level of an input signal supplied through the first input terminal and output the signal with the increased voltage level through the output terminal. The second input terminal of the first step-up circuit is connected to the output terminal of the second step-up circuit and the second input terminal of the second step-up circuit is connected to the output terminal of the first step-up circuit. The voltage generating circuit may also include third and fourth step-up circuits and fifth and sixth step-up circuits having similar configurations.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: March 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noriyasu Kumazaki, Masafumi Uemura, Tatsuro Midorikawa
  • Patent number: 8964489
    Abstract: When writing into an antifuse memory element finishes, a value of resistance of the memory element rapidly decreases; accordingly, an output voltage of a boosting circuit which produces a writing voltage rapidly decreases. By detecting a change in the output voltage of the boosting circuit to control a writing command, the writing operation can be stopped immediately after the memory element is shorted. Thus, unnecessary current consumption caused by continuing a writing operation on the shorted memory element can be suppressed.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Toshihiko Saito
  • Patent number: 8963624
    Abstract: A boosting circuit, includes an output circuit including a first transmission circuit, transmitting charges of a first boosting node to a first output node according to a first transmission control signal, a detection circuit, detecting the voltage level of the first output node, and a pre-charge circuit pre-charging the first boosting node according a detection signal of the detection circuit; a first pump circuit includes a second transmission circuit, transmitting charges to a second output node according to a second transmission control signal, and a first capacitance unit, coupled to the first boosting node, boosting the voltage level of the first boosting node according to charges transmitted in the second output node; and a control circuit, coupled to the output circuit and the first pump circuit, controls the second transmission control signal according to the voltage level of the first output node.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: February 24, 2015
    Assignee: Windbond Electronics Corp.
    Inventor: Hiroki Murakami
  • Publication number: 20150042399
    Abstract: Techniques for improving the linearity of radio-frequency (RF) front-end switches. In an aspect, open-loop techniques are disclosed for superimposing the output voltage of one or more negative rectifiers on a negative substrate bias voltage to reduce the non-linearities associated with voltage-dependent substrate leakage current. In another aspect, closed-loop techniques are further disclosed for maintaining the substrate bias voltage close to a reference voltage. Exemplary embodiments of the circuit blocks are further described.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 12, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: James Francis Imbornone, Xinwei Wang, Zhenying Luo, Xiangdong Zhang
  • Patent number: 8947156
    Abstract: This application discusses, among other things, apparatus and methods for driving the bulk of a high-voltage transistor using transistors having gates with low-voltage ratings. In an example, a bulk driver can include an output configured to couple to bulk of a high-voltage transistor, a pick circuit configured to couple the output to an input voltage at an input terminal of the high-voltage transistor or an output voltage at the output terminal of the high-voltage transistor when the high-voltage transistor is in a high impedance state, and a bypass circuit configured to couple the output of the bulk driver to the output voltage when the high-voltage transistor is in a low impedance state.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: February 3, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Julie Lynn Stultz, Tyler Daigle
  • Publication number: 20150028939
    Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.
    Type: Application
    Filed: October 13, 2014
    Publication date: January 29, 2015
    Inventors: Peter Vlasenko, Huy Tuong Mai
  • Patent number: 8937489
    Abstract: An inverter is capable of improving the reliability of driving. The inverter includes a first transistor and a second transistor. The first transistor is coupled between a first power source and an output terminal of the inverter, and has a first gate electrode coupled to a first input terminal of the inverter and a second gate electrode coupled to a third power source. The second transistor is coupled between the output terminal and a second power source, and has a first gate electrode coupled to a second input terminal of the inverter and a second gate electrode coupled to the third power source.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: January 20, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yong-Sung Park, Dong-Yong Shin
  • Publication number: 20150015326
    Abstract: A bulk-modulated current source includes: an output terminal configured to supply an output current; a first transistor comprising: a first electrode coupled to the output terminal, a second electrode, a bulk electrode, and a gate electrode configured to receive a bias voltage; and an amplifier comprising: an input terminal electrically coupled to the first electrode of the first transistor, and an output terminal electrically coupled to the bulk electrode of the first transistor.
    Type: Application
    Filed: April 22, 2014
    Publication date: January 15, 2015
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventor: Nasrin Jaffari
  • Patent number: 8928396
    Abstract: An electronic circuit includes: first circuits each including a first FET having a source supplied with at least one of a first voltage and a second voltage; and a second circuits each of which is associated with a respective one of the first circuits, and generates a back bias voltage applied to the first FET so as to change in accordance with a change of at least one of the first and second voltages.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: January 6, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Jun Nagayama, Tomoharu Awaya
  • Patent number: 8928043
    Abstract: A high voltage FET device provides drain voltage information with less overall silicon area consumption by forming a spiral resistance poly structure over a drift region of the high voltage FET device. The spiral resistance poly structure has an inner most end coupled to a drain region, and an outer most end coupled to a reference ground.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: January 6, 2015
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Joseph Urienza
  • Publication number: 20150002215
    Abstract: An integrated circuit includes a device of a first conductivity type formed in a first well; a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator; and a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage range, wherein each of the upper limit and lower limit is provided using a second band gap reference generator, separate from the first band gap reference generator, wherein, in response to determining that the voltage of the first well is outside of the first voltage range, providing a first out of range indicator.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Stefano Pietri, Chris C. Dao, Anis M. Jarrar, Juxiang Ren
  • Publication number: 20140375379
    Abstract: A semiconductor integrated circuit device has, as a current monitor circuit, a circuit in which n-channel type MISFETs are connected in series with each other. Based on a delay time of a speed monitor circuit in a state where a substrate bias is being applied to the p-channel type MISFETs, a first voltage value of a first substrate bias to be applied to the p-channel type MISFETs is determined. Next, based on a current flowing through an n-channel type MISFET in a state where the first substrate bias is being applied to the p-channel type MISFETs of the current monitor circuit and a second substrate bias is being applied to the n-channel type MISFETs of the current monitor circuit, a second voltage value of the second substrate bias to be applied to the n-channel type MISFETs is determined.
    Type: Application
    Filed: June 20, 2014
    Publication date: December 25, 2014
    Inventors: Hideki MAKIYAMA, Toshiaki IWAMATSU
  • Publication number: 20140369152
    Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.
    Type: Application
    Filed: August 29, 2014
    Publication date: December 18, 2014
    Inventors: Esin Terzioglu, Gregory Ameriada Uvieghara, Sei Seung Yoon, Balachander Ganesan, Anil Chowdary Kota
  • Publication number: 20140347131
    Abstract: A circuit, comprising a semiconductor device with one or more field gate terminals for controlling the electric field in a drift region of the semiconductor device; and a feedback circuit configured to dynamically control a bias voltage or voltages applied to the field gate terminal or terminals, with different control voltages used for different semiconductor device characteristics in real-time in response to a time-varying signal at a further node in the circuit.
    Type: Application
    Filed: May 23, 2014
    Publication date: November 27, 2014
    Applicant: NXP B.V.
    Inventors: Viet Thanh Dinh, Godefridus Antonius Maria Hurxk, Tony Vanhoucke, Jan Willem Slotboom, Anco Heringa, Ivan Zahariev, Evelyne Gridelet
  • Publication number: 20140347121
    Abstract: Self-biasing transistor switching circuitry includes a main transistor, a biasing transistor, a first capacitor, and a second capacitor. The body of the main transistor is isolated from the gate, the drain, and the source of the main transistor by an insulating layer. The first capacitor is coupled between the source and the gate of the main transistor. The second capacitor is coupled between the source and the body of the main transistor. The body and the drain of the main transistor are coupled together. The gate and the drain of the biasing transistor are coupled to the gate of the main transistor. The drain of the biasing transistor is coupled to the drain of the main transistor. The self-biasing transistor switching circuitry is adapted to receive an oscillating signal at the drain of the main transistor, and use the oscillating signal to appropriately bias the main transistor.
    Type: Application
    Filed: August 8, 2014
    Publication date: November 27, 2014
    Inventors: Nathaniel Peachey, Ralph Christopher Nieri
  • Patent number: 8896369
    Abstract: The present invention provides a switching device capable of further minimizing the ON resistance of a switching element. Switching element has hole injecting unit that includes injecting electrode which is directly connected to semiconductor substrate. Injection driving unit of driving unit is connected to injecting electrode and source electrode of switching element, and applies an injection voltage Vin between injecting electrode and source electrode. Injection driving unit injects holes from hole injecting unit to a hetero-junction interface of semiconductor substrate, by applying the injection voltage Vin exceeding a threshold value to switching element. Because the injected holes pull the equivalent amount of electrons to the hetero-junction interface, concentration of the 2-dimensional electron gas as the channel region becomes high, and the ON resistance of switching element 10 becomes small.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 25, 2014
    Assignee: Panasonic Coporation
    Inventors: Yosiaki Honda, Yuichi Inaba
  • Patent number: 8878599
    Abstract: A semiconductor integrated circuit device includes a power-supply terminal to which a power-supply voltage is input; and multiple MOS transistors including an Nch deplete mode MOS transistor functioning as a current source and at least one Pch enhancement mode MOS transistor formed on a silicon-on-insulator substrate including a silicon substrate, a buried-oxide film, and a silicon activate layer, each of the multiple MOS transistors dimensioned so that a bottom of a source diffusion layer and a bottom of a drain diffusion layer reach the buried-oxide film, the at least one Pch enhancement mode MOS transistor being connected to the supply terminal through the Nch depletion mode MOS transistor. The Nch depletion mode MOS transistor has electrical characteristics such that a source voltage thereof is higher than a silicon substrate voltage thereof and a saturation current of the Nch depletion mode MOS transistor is decreased.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: November 4, 2014
    Assignee: Ricoh Company, Ltd.
    Inventor: Takaaki Negoro
  • Patent number: 8867243
    Abstract: A DC-DC converter of a liquid crystal display (LCD) apparatus is provided comprising a first capacitor connected between a first node and a second node, a second capacitor connected between a third node and a fourth node, and a first diode connected between the input terminal and the first node.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: October 21, 2014
    Assignee: LG Display Co., Ltd.
    Inventor: Sungwoo Shin