Abstract: A semiconductor device drive circuit includes: a first transistor and a second transistor operating complementarily between a first voltage and a second voltage lower than the first voltage; an internal power supply circuit operating between the first voltage and the second voltage, and including: a constant voltage generation unit outputting an internal power supply voltage steadily being a constant voltage; and a feedback unit receiving a node voltage of a connection node between the first transistor and the second transistor, and changing the internal power supply voltage output from the constant voltage generation unit in response to a change of the node voltage; and a pre-driver operating between the first voltage and the internal power supply voltage, and driving the first transistor or the second transistor, wherein the node voltage is output as a gate voltage of the power switching device.

Abstract: A semiconductor device in which temperature dependence is reduced is provided. A switched capacitor is formed using a second transistor, a third transistor, and a second capacitor. Semiconductor layers of the second transistor and the third transistor that include an oxide can reduce temperature dependence. An AC signal supplied to the gates of the second transistor and the third transistor is converted into a DC voltage through the switched capacitor. Note that the level of the DC voltage is adjusted by the levels of the voltages supplied to the back gates of the second transistor and the third transistor.

Abstract: An integrated circuit is provided which can sense the drain voltage of an active heterojunction transistor under different conditions and can adjust a driving signal of a gate terminal of the active heterojunction transistor in order to limit conduction losses and/or switching losses.

Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

Abstract: A voltage selector circuit includes a voltage comparator, a multiplexer, and an adaptive current bias generator. The voltage comparator receives first and second input voltages, and outputs a comparator signal based on the first and second input voltages. The multiplexer selects a larger of the first and second input voltages in time based on first comparator signal. The adaptive current bias generator generates a bias current for the voltage comparator during a transition from a first state to a second state. The first input voltage is continuously larger than the second input voltage during the first state, and the second input voltage is continuously larger than the first input voltage in the second state. The bias current during the transition has a time-varying current level that is proportional to a time-varying difference between the first input voltage and the second input voltage during the transition.

Abstract: Disclosed are embodiments of a low-leakage row decoder and a memory circuit incorporating the row decoder. The row decoder includes wordline driver circuitry including first devices (pre-drivers) and second devices (wordline drivers). Each second device is connected in series between a first device and a wordline for a row in a memory array. The first devices can be directly connected to a positive supply voltage rail and connected to a ground rail through a footer. The second devices can be connected to the positive supply voltage rail through a header and directly connected to the ground rail. The on/off states of the header and footer are controlled by clock signal-dependent control signals so that they are either concurrently on or off. With this configuration, leakage power consumption of the wordline driver circuitry is minimized while the memory structures as idle and also while it operates in a normal active mode.

Abstract: A relay circuit, including a solid state relay switch, connected to a first relay line and to a charging capacitor, and connected to a second relay line. The relay circuit may also include a solid state relay control circuit, coupled between the charging capacitor and the solid state relay switch. The solid state relay control circuit may include a voltage detection circuit, having an input coupled to an output of the charging capacitor, and having an output arranged to generate a LOW voltage signal when a voltage level of the charging capacitor is below a low threshold value. The solid state relay control circuit may also include a zero crossing circuit, coupled to the first relay line and the second relay line, and having an output to generate a clock signal when a zero crossing event takes place between the first relay line and the second relay line.

Abstract: A voltage regulator circuit included in a computer system may include a switch device coupled between an input power supply node and a regulated power supply node. The switch device may change a value of a supply current flowing from the input power supply node and the regulated power supply node to regulate a voltage level of the regulated power supply node. A noise cancelation current may be feed forward onto a control terminal of the switch device to cancel noise on the regulated power supply node resulting from noise present on the input power supply node.

Abstract: Delay circuit includes: first to fourth transistors; capacitor; constant current source; and resistor. The first transistor has a gate connected to an input terminal, a source connected to the first power supply terminal, and a drain. The second transistor has a gate connected to an input terminal and the gate of the first transistor, a drain connected to the drain of the first transistor and the second terminal of the capacitor, and a source. The third transistor has a gate connected to a node between the drain of the first transistor, the drain of the second transistor, and the second terminal of the capacitor, a source connected to the second power supply terminal, and a drain. The fourth transistor has a gate connected to the node and the gate of the third transistor, a drain connected to the drain of the third transistor and an output terminal, and a source.

Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.

Abstract: A display substrate is provided. The display substrate includes a substrate (1), a first transistor (2) and a second transistor (3) on the substrate (1), directions of intrinsic threshold voltage shifts of the first transistor (2) and the second transistor (3) being opposite; and a shift adjustment structure (4) on the substrate (1). The shift adjustment structure (4) may be configured to input adjustment signals to the first transistor (2) and the second transistor (3) respectively to make threshold voltages of the first transistor (2) and the second transistor (3) shift in directions opposite to the directions of their intrinsic threshold voltage shifts respectively.

Abstract: A charge pump circuit includes a voltage output terminal, a flying capacitor, and a current source. The flying capacitor includes a first terminal coupled to the voltage output terminal, and a second terminal coupled to an output terminal of a drive circuit. The current source includes a first terminal coupled to the voltage output terminal, and a second terminal coupled to a power supply rail.

Abstract: An auxiliary power supply circuit is configured to receive electric power from an auxiliary power supply having a positive electrode connected to a switch node and supply electric power to a capacitor having a positive electrode connected to a reference potential node. The auxiliary power supply circuit includes; a switch element connected between the reference potential node and the switch node; and a diode having an anode connected to a negative electrode of the capacitor and a cathode connected to a negative electrode of the auxiliary power supply, a voltage of the switch node being alternately switched between (i) a first voltage substantially equal to a voltage of the reference potential node and (ii) a second voltage higher than the first voltage.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, an N-type well region over the semiconductor substrate, a FDSOI transistor formed over the N-type well region, a first shallow trench isolation (STI) region over the N-type well region, a first N-type doped region over the N-type well region, a second STI region over the semiconductor substrate, a first P-type doped region over the semiconductor substrate, and a first interconnection element over the first P-type doped region. The first P-type doped region is separated from the first N-type doped region by the second STI region. The first interconnection element is configured to connect the first P-type doped region to a ground. No interconnection element is formed over the first N-type doped region so that the first N-type doped region and the N-type well region are floating.

Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.

Abstract: A system is disclosed. The system includes a substrate, and a first chip on the substrate, where a load circuit is integrated on the first chip. The system also includes a second chip on the substrate, where a power delivery circuit is configured to deliver current to the load circuit according to a regulated voltage at a node. The power delivery circuit includes a first circuit configured to generate an error signal based at least in part on the regulated voltage, and a voltage generator including power switches configured to modify the regulated voltage according to the error signal, where the first circuit of the power delivery circuit is integrated on the first chip, and where at least a portion of the power switches of the power delivery circuit are integrated on the second chip.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.

Abstract: A watch is provided that includes a constant current circuit including: a plurality of transistors coupled in series between a first power supply and a second power supply, the first power supply being a power supply of a high potential side power supply, the second power supply being a power supply of a low potential side power supply; a plurality of connection wiring lines each provided for each of the plurality of transistors, and configured to couple the first power supply and a terminal on the first power supply side of each of the plurality of transistors; a non-disconnected fuse provided in a non-disconnected state to one connection wiring line of the plurality of connection wiring lines, and a disconnected fuse provided in a disconnected state to a connection wiring line other than the one connection wiring line of the plurality of connection wiring lines.

Abstract: An electronic device including a low dropout regulator having an output coupled to a first conduction terminal of a transistor, with a second conduction terminal of the transistor being coupled to an output node of the electronic device. A method for operating the device to switch into a power on mode includes: turning on the low dropout regulator, removing a DC bias from the second conduction terminal of the transistor, and turning on the transistor. A method for operating the device to switch into a power down mode includes: turning off the transistor, forming the DC bias at the second conduction terminal of the transistor, and turning off the low dropout regulator.

Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.

Abstract: An input output circuit and a self-biased circuit are provided. The self-biased circuit includes a tracking circuit, a biasing control circuit and first to fourth transistors. The tracking circuit receives a first power voltage, and generates a bias voltage according to variation of the first power voltage. The biasing control circuit generates a first control signal, a second control signal and a third control signal according to the first power voltage and a voltage on a pad. The first transistor is coupled to the pad and controlled by the first control signal. The second transistor is controlled by the second control signal to provide a bias voltage. The third transistor is coupled to the pad and controlled by the third control signal and generates a fourth control signal according to the voltage on the pad. The fourth transistor is controlled by the fourth control signal to generate the bias voltage.

Abstract: A system is disclosed. The system includes a first stage configured to receive VIN and VREF, the first stage including an input transistor pair, wherein the input voltage is coupled to the input transistor pair, the input transistor pair is coupled to ground, and the input transistor pair includes at a common drain a high-gain node having a voltage VHGN. The system further include a second stage coupled to the high-gain node and configured to generate VOUT based on a difference between VIN and VREF, the second stage comprising a resistor and an inverter transistor pair, wherein the gates of the inverter transistor pair are coupled to the high-gain node of the first stage and the resistor couples the high-gain node of first stage to a common drain of the inverter transistor pair and is configured to provide and/or draw current to and/or from the high-gain node of first stage.

Abstract: A GOA circuit and a display device are provided. The GOA unit includes multiple GOA units, and each GOA unit includes a pull-up circuit for outputting a scanning driving signal of a current stage, a pull-down circuit including a first pull-down switch for pulling down the scanning driving signal of the current stage to a low voltage level, and a pull-down holding circuit including a first pull-down holding switch for holding the scanning driving signal of the current stage at a low voltage level. Each of the first pull-down switch and the first pull-down holding switch is a dual-gate TFT switch, a top gate electrode of each of the first pull-down switch and the first pull-down holding switch receives the first direct-current voltage. Accordingly, the present invention can reduce the current leakage, and increase the reliability of the entire GOA circuit.

Abstract: Embodiments include circuits, apparatuses, and systems for non-boolean associative processors. In embodiments, an electronic associative processor circuit may include first and second ring oscillators, each having an odd number of inverters, an input terminal, and an output terminal. A first capacitor may have a first terminal coupled with the output terminal of the first ring oscillator and a second capacitor may have a first terminal coupled with the output terminal of the second ring oscillator. Second terminals of the first and second capacitors may be coupled at an oscillator stage output terminal. The inverters of the first and second ring oscillators may be implemented with metal oxide semiconductor transistors. Other embodiments may be described and claimed.

Abstract: The tunnel field effect transistor according to the present invention has: a channel; a source electrode connected directly or indirectly to one end of the channel; a drain electrode connected directly or indirectly to the other end of the channel; and a gate electrode for causing an electric field to act on the channel, generating a tunnel phenomenon at the source electrode-side joint part of the channel, and simultaneously generating a two-dimensional electron gas in the channel.

Abstract: In some method and apparatus embodiments, an RF circuit comprises a switch transistor having a source, a drain, a gate, and a body. A gate control voltage is applied to the gate of the switch transistor. A body control voltage is applied to the body of the switch transistor. The body control voltage is a positive bias voltage when the switch transistor is in an on state. In some embodiments, an RF circuit comprises a control voltage applied to the gate of the switch transistor through a first resistance and applied to the body of the switch transistor through a second resistance. The first resistance is different from the second resistance.

Abstract: A resistorless CMOS low power voltage reference circuit is provided. The start-up circuit is used to prevent the circuit to stay in the zero state and stop working when the circuit gets out of the zero state. The self-biased VPTAT generating circuit generate the voltage VPTAT which has positive temperature coefficient. The square-law current generating circuit generates a square-law current which is proportional to ?T2 through the VPTAT. Finally, the reference voltage VREF is obtained by introducing the square-law current into the reference voltage output circuit. The reference voltage VREF of this application can realize approximative zero temperature coefficient in the temperature range of ?40° C.˜100° C. This application improves temperature characteristic which may be poorer due to temperature nonlinearity of carrier mobility based on the traditional subthreshold reference. This application can reduce the power consumption from ?W level to nW level and realize low power consumption.

Abstract: A method for implementing a Semiconductor Integrated Circuit device using Near/Sub-threshold technology with SW programmable adaptive and dynamic forward and reverse bias voltage control using different sensors inside the chip in order to improve speed, reduce leakage and ensure high yield of the final product that operates at an ultra-low power consumption. This method allows achieving ultra-low power solution with reasonable higher speed and insure high yield.

Abstract: An input stage of a chip includes a source driver and a sensing and clamping circuit. The source follower is arranged for receiving an AC-coupled signal to generate an output signal at an output terminal. The sensing and clamping circuit is coupled to the source follower, and is arranged for clamping the output terminal of the source follower at a fixed DC voltage.

Abstract: A command generation circuit, test control circuit, semiconductor device, semiconductor system, and or a test method may be provided. The semiconductor device may be configured to enter test modes and to generate internal commands during a clock cycle.

Abstract: An integrated circuit device having a p-well plane, a plurality of substantially parallel n-well rows, and a logic cell. The p-well plane is comprised of p-type semiconductor material. Each n-well row comprises an n-type layer disposed on the surface of the p-well plane. The plurality of n-well rows includes a first n-well row and a second n-well row. The logic cell is arranged on the p-well plane and the footprint of the logic cell encompasses both the first and second n-well rows.

Abstract: An example a voltage regulator includes: a bias circuit coupled to an output node; a first operational amplifier having a first input coupled to the output node, a second input coupled to a reference voltage node, and an output coupled to a first node; a second operational amplifier having a first input coupled to the output node, a second input coupled to the reference voltage node, and an output coupled to a second node; an output transistor coupled between the output node and a ground node, the output transistor including a gate; first, second, and third stacked transistor pairs each serially coupled between the output node and the ground node, each transistor of the first, second, and third stacked transistor pairs including a gate; and switch circuits configured to selectively couple: the gates of the first and second stacked transistor pairs to the second node; and the gate of the output transistor to the first node.

Abstract: A method for at least partially compensating for a change in threshold voltage level of a FET transistor induced by OFF-state stress degradation includes determining a signal indicative of a change in threshold voltage level of the FET with respect to a reference threshold voltage level, and applying a restoration signal to the FET. This restoration signal is adapted for shifting the threshold voltage level of the FET in a direction having opposite sign with respect to the change in threshold voltage level. Applying the restoration signal further includes taking into account the signal indicative of the change in threshold voltage level.

Abstract: A method for offset cancellation in a receiver loss of signal (RxLOS) circuit of a serializer/deserializer (SerDes) receiver device includes receiving a differential input signal via the first stage of a peak detector cell of the RxLOS circuit and shorting the differential output of the first stage via a control switch of the second stage of the RxLOS circuit. The control switch may further transition the RxLOS circuit from normal operating mode to an offset cancellation mode wherein the control switch may manually or automatically short the differential output of the first stage.

Abstract: If the threshold of a thin film transistor is depleted, a leak-induced voltage drop takes place and the desired voltage cannot be obtained. Depending on the severity of the phenomenon, the thin film transistor may fail to function. This disclosure offers a thin film transistor circuit having a first transistor connected to a low voltage, and a second transistor connected to the gate of the first transistor. When the gate voltage of the second transistor is changed from the high level to the low level, the gate voltage of the first transistor is brought to a voltage level lower than the low voltage.

Abstract: Embodiments relate to circuits, systems and methods for providing interruption protection for sensors and other devices. One example embodiment includes an interruption protection circuit comprising at least one charge pump and at least one buffer capacitor configured to maintain and/or provide sufficient voltage for output signals of sensors or other devices during micro-breaks or other interruptions.

Abstract: Exemplary embodiments are directed to systems, devices, methods, and computer-readable media for reducing static and dynamic power consumption of a charge pump. In one embodiment, a device may include a plurality of switches, each switch of the plurality having a gate coupled to a dedicated driver of a plurality of drivers. The device may further include at least one clamp switch coupled to at least one driver of the plurality of drivers and configured to adjust a rail voltage of the at least one driver if an input voltage is greater than a threshold voltage. In another embodiment, the device may include a plurality of multiplexers, each multiplexer of the plurality of multiplexers coupled to a portion of an associated switch of the plurality of switches and configured to disable the portion of the associated switch if a clock frequency of the charge pump is below a threshold frequency.

Abstract: An integrated circuit device can include at least one oscillator stage having a current mirror circuit comprising first and second mirror transistors of a first conductivity type, and configured to mirror current on two mirror paths, at least one reference transistor of a second conductivity type having a source-drain path coupled to a first of the mirror paths, and a switching circuit coupled to a second of the mirror paths and configured to generate a transition in a stage output signal in response to a stage input signal received from another oscillator stage, wherein the channel lengths of the first and second mirror transistors are larger than that of the at least one reference transistor.

Abstract: A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output.

Abstract: An integrated circuit includes a process voltage temperature (PVT) effect transducer responsive to a PVT effect, a PVT effect quantifier coupled to the PVT effect transducer and configured to quantify the PVT effect to provide an output, and a bias controller configured to receive the output of the PVT effect quantifier and provide a bias voltage for a substrate of an NMOS or a PMOS transistor. The bias controller is configured to compare the output received from the PVT effect quantifier to a threshold value, and decrease or increase the bias voltage depending on whether the output is higher or lower than the threshold value.

Abstract: Apparatuses including termination for complementary signals are described, along with methods for terminating complementary signals. One such apparatus includes a termination transistor including a first node configured to receive a first complementary signal and a second node configured to receive a second complementary signal. A regulation circuit can generate a regulated voltage to render the termination transistor conductive with a substantially constant resistance. In one such method, a first complementary signal is received at a drain of a termination transistor and a second complementary signal is received at a source of the termination transistor. Energy of the complimentary signals can be absorbed when the termination transistor is rendered conductive. Additional embodiments are also described.

Abstract: A body bias control circuit including an output coupled to provide a bias voltage to a body terminal. The body bias control circuit is configured to change the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time. For voltages between the first and second bias voltages closer to a source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.

Abstract: A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.

Abstract: Provided is a bias circuit. The bias circuit includes: a first resistor connected between a ground terminal and a first node; a first bias transistor having a drain connected to the first node and a source connected to a second node; a second bias transistor having a drain connected to the second node and a source connected to a negative voltage terminal; a third bias transistor having a drain connected to the ground terminal and a source connected to a third node; and a second resistor connected between the third node and the negative voltage terminal, wherein a gate of the first bias transistor is connected to the second node; a gate of the second bias transistor is connected to the negative voltage terminal; a gate of the third bias transistor is connected to the first node; and a gate bias voltage signal is outputted through the third node.

Abstract: A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor.

Abstract: A circuit arrangement including a first transistor, a second transistor and a third transistor. The first transistor and the second transistor are configured so that the current flowing through the first transistor is proportional to the current flowing through the second transistor and the third transistor. The first transistor, the second transistor and the third transistor are configured to operate in an ohmic mode. The second transistor and the third transistor are coupled in series to each other. The first transistor, the second transistor and the third transistor match each other in at least one characteristic.

Abstract: A body bias control circuit including an output coupled to provide a bias voltage to a body terminal. The body bias control circuit is configured to change the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time. For voltages between the first and second bias voltages closer to a source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.

Abstract: In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate width and gate length of the transistor and gate width and gate length of the transistor are adjusted so that source-drain current flowing between the source and the drain of the transistor becomes equal to source-drain current flowing between the source and the drain of the transistor when the voltage applied to the input terminal is set to be preset trigger voltage. This configuration accomplishes detecting that the input voltage exceeds the trigger voltage with simple configuration.

Abstract: A low voltage ring oscillator circuit can have a frequency variation that depends on process variations of insulated gate field effect transistors (IGFETs) of a first conductivity type without substantially being affected by process variations to IGFETs of a second conductivity type. A ring oscillator stage may include an inverter including only IGFETs of the first conductivity type. The inverter may be coupled to a boot circuit that boosts the gate potential of a first IGFET of the first conductivity type with a timing such that IGFETs of the second conductivity type in the boot circuit do not affect the frequency variations of the ring oscillator circuit.

Abstract: A semiconductor device includes an input-part receiving a first voltage and an output-part outputing a second voltage. A current mirror part receives the first voltage. A reference voltage is supplied to a gate of a reference transistor. The reference transistor is electrically connected between the current-mirror part and a ground voltage. A monitor transistor includes a gate electrically connected to the second power-supply voltage, and is electrically connected between the current-mirror part and the ground voltage. A voltage-generation transistor includes a gate electrically connected to both the current-mirror part and the reference transistor. The voltage-generation transistor is electrically connected between the input-part and the output-part. A first capacitor including one end electrically connected to the output-part, and the other end electrically connected to both the current-mirror part and the reference transistor.