With Field-effect Transistor Patents (Class 327/541)
  • Patent number: 11874680
    Abstract: Disclosed is a power supply that automatically switches between a voltage regulation mode and an over current protection mode, as needed. The power supply includes a voltage regulator that generates a first control voltage for applying to the control terminal of a pass transistor during a voltage regulation mode to maintain an output voltage at a desired voltage level. The power supply includes a current limiter that generates a second control voltage for applying to the control terminal of the pass transistor during an over current protection mode to prevent an output current from rising above a maximum output current limit. The power supply includes additional circuitry that detects when over current protection is required and automatically switches the control voltage applied to the control terminal from the first control voltage to the second control voltage or vice versa, as necessary. Also disclosed is an associated power supply method.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: January 16, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventor: Shatabda Saha
  • Patent number: 11841721
    Abstract: The present disclosure realizes a configuration capable of setting and changing the value of a voltage that is output from a voltage regulator, while suppressing an increase in the size of an apparatus and keeping the apparatus from being complex. A control unit of a voltage regulator operates to switch a state of each port to either a first state or a second state. An input circuit unit applies a voltage corresponding to the combination of the first states at the ports to the base of a transistor. Electricity flows through the transistor when at least one of the ports is in the first state. A switch is turned on when electricity flows through the transistor. A Zener diode sets an output voltage applied to a second conductive path to a voltage corresponding to a voltage applied to the base of the transistor.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: December 12, 2023
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Kazushi Shimamoto, Yuuki Sugisawa
  • Patent number: 11824442
    Abstract: An error amplifier circuit for a DC-DC power converter controller is disclosed for providing an amplified error signal to a switch control circuit, the circuit comprising an error amplifier first stage. The first stage comprises: a first input terminal for receiving a voltage proportional to an output voltage of the converter; an output node; a first operational transconductance amplifier in a first path between the input terminal and the output node and having a first input connected to the input terminal, a second input connectable to a reference signal, and an output connected to the output node; and a second, parallel, path comprising a series combination of an amplifier, a second OTA and a capacitor. The second OTA has an output connected to the capacitor, a first input connected to an output of the amplifier, and a second input connected to the output. Associated control circuits, controllers and converters are also disclosed.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: November 21, 2023
    Assignee: NXP USA, Inc.
    Inventor: Denis Sergeevich Shuvalov
  • Patent number: 11809249
    Abstract: A port controller circuit is configured to control power transfer on a power path between a first terminal and a second terminal. The controller circuit includes first and second transistors connected in series between the first terminal and the second terminal, a control terminal of the first transistor receiving a first gate voltage and a control terminal of the second transistor receiving a second gate voltage. A first gate voltage control circuit generates the first gate voltage driving the control terminal of the first transistor and regulates the first gate voltage to keep the first transistor turned on. In response to the first gate voltage control circuit regulating the first gate voltage to a voltage value less than a first voltage level, the first gate voltage control circuit asserts a first signal to indicate a fault condition at the first transistor.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: November 7, 2023
    Assignee: Alpha and Omega Semiconductor International LP
    Inventor: Michael Scheel
  • Patent number: 11789481
    Abstract: Methods and devices for speeding up the onset of a target current through an output leg of a current mirror are presented. Upon activation of the current mirror, a pre-charge current is sourced to a node of the current mirror that is common to the output leg and an input leg of the current mirror. Sourcing of the pre-charge current is based on sensing, by a first transistor, of a voltage at the common node. Pre-charging of the common node continues up to a cutoff voltage sensed at the common node. Sourcing of the pre-charge current is provided by a second transistor coupled to the common node. Based on the voltage sensed at the common node, the first transistor controls the sourcing of the pre-charge current by the second transistor. Such control is based on a portion of a current from a current source that flows through the first transistor.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: October 17, 2023
    Assignee: PSEMI CORPORATION
    Inventor: Jaroslaw Adamski
  • Patent number: 11779214
    Abstract: A device for measuring and classifying ocular misalignment of a patient's eyes includes an enclosure, two lenses at the front of the enclosure, one corresponding to each eye of a patient, a divider within the enclosure, positioned laterally between the lenses, a screen within the enclosure, an integrated microprocessor connected to the screen, and at least one input control connected to the integrated microprocessor, at least one input control operable by the patient; where the integrated microprocessor generates and transmits two images to the screen, each image corresponding to each lens; where the integrated microprocessor receives input from the patient via at least one input control to manipulate at least one image on the screen; and where the integrated microprocessor calculates and outputs a quantification of ocular misalignment based on that input.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: October 10, 2023
    Inventors: Zachary Bodnar, Heather Moss, David Buickians
  • Patent number: 11762410
    Abstract: Methods, systems, and apparatuses for producing a compensated voltage reference. The method includes operating a voltage reference circuit. The method also includes activating a first compensation circuit when an operating temperature is less than or equal to a first temperature threshold. The first compensation circuit is configured to extract a first compensation current from the voltage reference circuit. The method further includes deactivating the first compensation circuit when the operating temperature is greater than the first temperature threshold. The method also includes activating a second compensation circuit when the operating temperature is greater than or equal to a second temperature threshold. The second compensation circuit is configured to extract a second compensation current from voltage reference circuit. The second temperature threshold is greater than the first temperature threshold.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: September 19, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Paolo Migliavacca
  • Patent number: 11688468
    Abstract: Devices and techniques are disclosed herein to provide a high-voltage bias signal in a standby state of the storage system without exceeding a limited maximum standby current allowance of the storage system. The high-voltage bias signal can enable a string driver circuit in the standby state to couple a global word line to a local word line, to provide a bias to, or sink a voltage from, a pillar of a string of memory cells of the storage system in the standby state, such as to reduce read disturbances in the storage system.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: June 27, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michele Piccardi, Xiaojiang Guo, Shigekazu Yamada
  • Patent number: 11662754
    Abstract: A reference voltage circuit (1) includes a PTAT voltage generation circuit (20) that generates a voltage with a positive temperature coefficient, a CTAT voltage generation circuit (10) that generates a voltage with a negative temperature coefficient, and a temperature characteristic adjustment circuit (30) that generates a voltage for adjusting temperature characteristics. The reference voltage circuit outputs a reference voltage (VOUT) formed by calculation based on the output of the PTAT voltage generation circuit, output of the CTAT voltage generation circuit, and output of the temperature characteristic adjustment circuit.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 30, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Hiroyuki Watanabe
  • Patent number: 11626870
    Abstract: A circuit comprises a gate driver having a supply voltage terminal and configured to generate an output at an output terminal based on an input. A voltage multiplexer is configured to connect a first voltage terminal to the supply voltage terminal responsive to a voltage select signal having a first value and connect a second voltage terminal to the supply voltage terminal responsive to the voltage select signal having a second value. First logic is configured to generate a fault signal responsive to detecting one of a first fault condition associated with operation of the gate driver or a second fault condition associated with operation of the gate driver and generate the voltage select signal having the second value based on the fault signal. Second logic is configured to generate the voltage select signal having the second value after a predetermined delay period based on a value of the input.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: April 11, 2023
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Mi Ran Baek, Junbae Lee
  • Patent number: 11606029
    Abstract: A power transistor and a cascode transistor are connected in series. A driver circuit has an output driving a control terminal of the power transistor. The driver circuit has a first power supply node coupled to receive a floating voltage that is also applied to a control terminal of the cascode transistor. A variable voltage generator generates the floating voltage. The floating voltage track either a power supply voltage or a reference voltage over a first range of voltage levels for the power supply voltage. The floating voltage further satisfies a ratio metric relationship dependent on the power supply voltage and reference voltage over a second range of voltage levels for said power supply voltage.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: March 14, 2023
    Assignee: STMicroelectronics International N.V.
    Inventor: Pravesh Kumar Saini
  • Patent number: 11593603
    Abstract: There is described a rectifier circuit for providing and limiting a supply voltage to an RFID tag, the circuit including a pair of antenna input terminals configured to receive an input signal from an RFID tag antenna. A plurality of charge pump stages are coupled in cascade in such a way that an input terminal of a first charge pump stage in the cascade is connected to ground and an input terminal of each subsequent charge pump stage in the cascade is coupled to an output terminal of the preceding charge pump stage in the cascade. A control logic is configured to select the output terminal of one charge pump stage among the plurality of charge pump stages to provide the supply voltage. Furthermore, an RFID tag and a method of providing and limiting a supply voltage to an RFID tag are described.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: February 28, 2023
    Assignee: NXP B.V.
    Inventors: Thomas Pichler, Ivan Jesus Rebollo Pimentel
  • Patent number: 11561562
    Abstract: A device includes a voltage regulator circuit, a power switch circuit, and a control circuit. The voltage regulator circuit generates an output voltage at an output terminal. The power switch circuit is coupled to the voltage regulator circuit. The control circuit receives a first control signal and generates a second control signal that includes a first portion gradually declining between a first time and a second time later than the first time. When the voltage regulator circuit is turned off and a logic state of the first control signal changes at the first time, the power switch circuit is turned on at the second time, in response to the second control signal, to adjust the output voltage.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: January 24, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Yong-Liang Jin, Ya-Qi Ma, Wei Li, Di Fan
  • Patent number: 11527954
    Abstract: A regulator circuit and a front-end module including the same may be disclosed. The regulator circuit may include a first output voltage generator and a second output voltage generator. The first output voltage generator may include a first resistor having a first end connected to power supplied from an outside, a first transistor connected between a second end of the first resistor and a ground terminal to supply a first voltage, and a second transistor receiving the first voltage through a control terminal and outputting a first output voltage through a first terminal. The second output voltage generator may be connected between the power and the first output voltage generator to output a second output voltage obtained by adding a predetermined voltage into the first output voltage.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: December 13, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Sanghoon Ha
  • Patent number: 11522455
    Abstract: A power converter for detecting oscillation of an output voltage including a switching regulator configured to perform switching so that an inductor is alternatively connected to or isolated from an external power voltage and generate the output voltage by a current that flows through the inductor and an oscillation detector configured to detect oscillation that occurs in the output voltage and output an oscillation detection signal by determining whether the oscillation belongs to an oscillation frequency detection range to be detected by the oscillation detector may be provided.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: December 6, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyunseok Nam
  • Patent number: 11449689
    Abstract: Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: September 20, 2022
    Inventor: Ali Tasdighi Far
  • Patent number: 11435426
    Abstract: Aspects of the invention include a circuit having a power header configured to couple to a power supply and to provide an output voltage. A sense circuit is coupled to the power header to receive the output voltage, the sense circuit including a replica voltage circuit coupled to a replica power header circuit and a transistor, the replica voltage circuit being configured to provide a replicated output voltage in accordance with the output voltage, the replica power header circuit being configured to couple to the power supply and the replicated output voltage to generate a replica current, the transistor being configured to deliver the replica current.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: September 6, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Miguel E. Perez, Michael Sperling, Michael Floyd, John Francis Bulzacchelli
  • Patent number: 11342931
    Abstract: A reference voltage controlling circuit and an analog-to-digital converter are disclosed. The reference voltage controlling circuit includes a reference voltage generating circuit, a plurality of groups of sampling switching units and a logic controlling circuit. The DAC capacitor array switches the sampling switching units to a second positive reference voltage and a second negative reference voltage before starting sampling or conversion, and is charged and discharged with the second positive reference voltage and the second negative reference voltage to raise a voltage to a preset voltage. The sampling switching unit is switched to a first positive reference voltage and a first negative reference voltage to charge and discharge the DAC capacitor array to a target voltage. The rising of the voltage from the preset voltage to the target voltage is completed by the first positive reference voltage and the first negative reference voltage.
    Type: Grant
    Filed: April 25, 2021
    Date of Patent: May 24, 2022
    Assignee: Radiawave Technologies Co., Ltd.
    Inventors: Xiaofeng Guo, Erkan Alpman, Jon Sweat Duster, Ning Zhang, Yulin Tan, Haigang Feng
  • Patent number: 11340641
    Abstract: A voltage regulator provides a load device with a regulated voltage, and includes a first regulator circuit, a second regulator circuit, a first control loop circuit, and a second control loop circuit. The load device and the first regulator circuit are connected in series. The load device and the second regulator circuit are connected in parallel. The first control loop circuit adaptively adjusts a first bias voltage of the first regulator circuit in response to a load condition at the output node of the voltage regulator, wherein the first control loop circuit includes a capacitor coupled between the first power rail and an output node of a feedback amplifier. The second control loop circuit adaptively adjusts a second bias voltage of the second regulator circuit in response to the load condition at the output node of the voltage regulator.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 24, 2022
    Assignee: MediaTek Inc.
    Inventors: Chun-Wei Chang, Song-Yu Yang, Ang-Sheng Lin
  • Patent number: 11335393
    Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yoshiro Riho, Yoshinori Matsui, Kiyohiro Furutani, Takahiko Fukiage, Ki-Jun Nam, John D. Porter
  • Patent number: 11329648
    Abstract: A discharge control circuit includes discharge elements, logic circuits, and at least one delay circuit. Each of the logic circuits controls turning-on and turning-off the discharge elements based on a control signal inputted externally. The delay circuit delays an output signal of a first logic circuit among the logic circuits. The discharge control circuit pulls out charges from a corresponding terminal in response to turning-on of the discharge elements. A signal delayed by the delay circuit is inputted to a second logic circuit among the logic circuits so that the discharge elements are controlled in a predetermined order by one control signal.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: May 10, 2022
    Assignee: MITSUMI ELECTRIC CO., LTD.
    Inventor: Yuichi Ueda
  • Patent number: 11295820
    Abstract: A voltage generation system might include a selectively-enabled resistive voltage divider having a first resistor connected between an output of the voltage generation system and a first feedback node and having a second resistor connected between the first feedback node and a first voltage node; a selectively-enabled capacitive voltage divider having a first capacitor connected between the output and a second feedback node and having a second capacitor connected between the second feedback node and the first voltage node; a comparator having a first input connected to the second feedback node, having a second input connected to a control signal node, and having an output; and a voltage generation circuit configured to generate a voltage level at the output responsive to a logic level of the output of the comparator and to a clock signal; wherein the first feedback node is selectively connected to the second feedback node.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Manan Tripathi, Michele Piccardi, Xiaojiang Guo
  • Patent number: 11233513
    Abstract: The present invention provides a reference voltage buffer comprises a reference voltage generator, a first operational amplifier, a first transistor, a first group of resistors, a first load, a second transistor, a second group of resistors and a second load. In the reference voltage buffer, the first load and the second load use active device to increase the settling time, and the first load, the second load and the reference voltage generator of the reference voltage buffer are resigned to have the same characteristics in response to the temperature variation to overcome the PVT issue, and the first load and the second load of the reference voltage buffer use the open-loop design to have large full-scale of the output reference voltages.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: January 25, 2022
    Assignee: MEDIATEK INC.
    Inventors: Hung-Chieh Tsai, Sheng-Hui Liao
  • Patent number: 11211928
    Abstract: A power switch fault detector detects faults in the current paths of power switches. A first operational amplifier detects a drain-source voltage of a first set of parallel connected field-effect transistors in a current path. A second operational amplifier detects a drain-source voltage of a second set of parallel connected field-effect transistors in the current path. A hardware or software processor is configured to compare a difference in magnitude of the drain-source voltages to a threshold voltage to determine whether a field-effect transistor of one of the first set or second set is compromised. The current path is isolated and one of the first set or second set of field-effect transistors is deactivated to determine whether a field-effect transistor of the first set or second set is stuck-open or shorted.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: December 28, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Alexandre Valero
  • Patent number: 11157028
    Abstract: In one embodiment, a droop detector circuit, comprising: a reference oscillator; plural delay lines configured to receive signals from the reference oscillator; and logic configured to detect droop in a voltage regulator based on an output of the voltage regulator and outputs of each of the plural delay lines.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: October 26, 2021
    Assignee: CENTAUR TECHNOLOGY, INC.
    Inventor: James R. Lundberg
  • Patent number: 11150678
    Abstract: A current mirror includes first and second transistors having current paths coupled to an input current line. The current paths for the first and second transistors are referenced to ground via respective first and second resistors having resistance values twice a first resistance value. The first transistor is diode connected. A third transistor has a current path coupled to an output current line and referenced to ground via a third resistor having a second resistance value equal to the first resistance value divided by a mirror factor. Control terminals of the first and third transistors are coupled together, and further coupled to a control terminal of the second transistor through a coupling resistor. A first capacitor is coupled between ground and the control terminal of the second transistor unit. A second capacitor is coupled between ground and the current path through the third transistor.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: October 19, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Germano Nicollini, Stefano Polesel
  • Patent number: 11133743
    Abstract: To provide an individual boost circuit capable of boosting a minute power voltage to a target voltage more reliably. An individual boost circuit includes a first PMOS transistor that has a gate to which a first clock voltage is applied and performs on- and off-operations; a second PMOS transistor that has a gate to which a second clock voltage that has a reciprocal relation with the first clock voltage is applied and performs the on- and off-operations; an auxiliary capacitor; a boost capacitor; an auxiliary charging circuit 211 that charges an auxiliary capacitor via the second PMOS transistor with a power voltage from an external power when the first PMOS translator enters an off-state and the second PMOS transistor enters an on-state; and a boost charging circuit 212 that charges the boost capacitor via the first PMOS transistor with the second clock voltage through the auxiliary capacitor when the first PMOS transistor enters the on-state and the second switching transistor enters the off-state.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: September 28, 2021
    Assignee: Tohoku University
    Inventors: Shinya Yoshida, Tsutomu Nakamura
  • Patent number: 11079785
    Abstract: There is provided a linear regulator including: a first output transistor connected between a first input terminal to which a first input voltage is applied and an output terminal from which an output voltage is outputted; a second output transistor connected between a second input terminal to which a second input voltage is applied and the output terminal; and a control circuit configured to control the first output transistor when the second input voltage of a predetermined range is not supplied to the second input terminal, and to control the second output transistor when the first input voltage of the predetermined range is not supplied to the first input terminal.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: August 3, 2021
    Assignee: Rohm Co., Ltd.
    Inventor: Shingo Hashiguchi
  • Patent number: 11067864
    Abstract: An embodiment of the present invention provides a display device which allows for the area of a wiring diverting region to be reduced. The display device (1) includes: a substrate (100) having a displaying region (30) and a non-displaying region (10); a plurality of first switching elements (TFT1, TFT2); a plurality of gate lines (50) each of which is respectively connected to a gate of one or more of the plurality of first switching elements; a plurality of second switching elements (TFT3); a plurality of sub gate lines (60) each of which is respectively connected to a gate of one or more of the plurality of second switching elements; and one or more connecting lines (70) each of which connects a respective one of the plurality of gate lines (50) to a respective one of the plurality of sub gate lines (60).
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: July 20, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Masahiro Yoshida
  • Patent number: 11063470
    Abstract: A system and method of managing a power infrastructure having a plurality of duty power modules (DPMs) configured to power a plurality of load centers. Various different operational modes may be deployed. Inherent redundancy mode is implemented by: monitoring operations of the power infrastructure; powering each load center during normal operations using DPMs through a load center switch via an enabled preferred setting (PS) input; providing an inherent redundancy (IR) bus coupled to each load center switch via an alternate setting (AS) input that is disabled during normal operations, wherein the IR bus is configured to receive excess capacity power exclusively from the DPMs; and in response to a detected DPM failure, disabling the PS input and enabling the AS input in the load center switch for an affected load center to capture power from the IR bus.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 13, 2021
    Inventor: Edward Michael John Ansett
  • Patent number: 11011091
    Abstract: An array substrate, a display panel, a display device, an operating method, and a manufacturing method are disclosed. The array substrate includes a wiring structure formed on a base substrate, and the wiring structure includes a common electrode line for connecting a common electrode, and a plurality of signal lines. The plurality of signal lines include at least one pair of signal lines, and the pair of signal lines include a first signal line and a second signal line. The first signal line is disposed on a first side of the common electrode line and is configured to transmit a driving signal for a gate driving circuit. The second signal line is disposed on a second side of the common electrode line and is configured to transmit an inverted signal of the driving signal.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: May 18, 2021
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qiang Zhang, Dianzheng Dong, Guangxing Wang, Pengming Chen, Wenpeng Xu, Wan Lin, Haixu Wang, Leiyang Wang
  • Patent number: 11007457
    Abstract: Aspects of the disclosure are directed to an apparatus for separating a second fluid or a particulate from a host fluid. That apparatus comprises a flow chamber with at least one inlet and at least one outlet. A drive circuit configured to provide a drive signal to a filter circuit configured to receive the drive signal and provide a translated drive signal. An ultrasonic transducer is cooperatively arranged with the flow chamber, and transducer includes at least one piezoelectric element configured to be driven by the current drive signal to create an acoustic standing wave in the flow chamber. At least one reflector opposing the ultrasonic transducer to reflect acoustic energy.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: May 18, 2021
    Inventors: Bart Lipkens, Ronald Musiak, Dane Mealey, Ali Shajii
  • Patent number: 10991437
    Abstract: A semiconductor device may include: an internal voltage supplier, and a voltage level controller. The internal voltage supplier may supply an internal power supply voltage to be used for the operation of the semiconductor device. The voltage level controller may determine whether a voltage level change condition of the semiconductor device is satisfied and controls the internal voltage supplier to change a voltage level of the internal power supply voltage based on a result of the determining.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: April 27, 2021
    Assignee: SK hynix Inc.
    Inventor: Jin Yong Seong
  • Patent number: 10971227
    Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: April 6, 2021
    Assignee: Unity Semiconductor Corporation
    Inventors: Christophe Chevallier, Robert Norman
  • Patent number: 10878882
    Abstract: Systems and methods of dynamically calibrating memory control signals during increase of wordline voltage for memory technologies subject to charge loss are disclosed. In one aspect, an exemplary method may comprise using an internal node, such as a wordline regulator output or return feedback line or a replica of the wordline, as proxy for the local wordline voltage. In one or more further embodiments, the proxy signal may be converted to digital signal or code and even determined in the background before the signal is needed for calibration. As a function of the disclosed technology, calibration of memory control signals, such as pass voltage and wordline read-verify voltage, may be performed during increase of the wordlines voltage with no impact or penalty on read/program time.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Michele Piccardi
  • Patent number: 10860046
    Abstract: A reference voltage generation device (100) includes a constant current circuit (101) configured to output a constant current; and a plurality of voltage generation circuits (102) each configured to generate an output voltage based on the constant current, wherein the constant current has a correlation represented by a first gradient with respect to a temperature change, and wherein a plurality of the output voltages from the plurality of voltage generation circuits (102) have correlations represented by second gradients that are inverse to the correlation represented by the first gradient with respect to the temperature change and have different gradient indices. The reference voltage generation device (100) is configured to generate a reference voltage based on the constant current and the output voltage of at least one voltage generation circuit selected from the plurality of voltage generation circuits.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: December 8, 2020
    Assignee: ABLIC INC.
    Inventor: Kazuhiro Tsumura
  • Patent number: 10824181
    Abstract: A reference voltage circuit includes a first MOS transistor pair having a first MOS transistor of an enhancement type having a gate and a drain connected to each other, and a second MOS transistor of a depletion type having a gate connected to a source of the first MOS transistor, a source connected to the drain of the first MOS transistor, and a drain connected to an output terminal; and a second MOS transistor pair having a third MOS transistor of an enhancement type having a gate and a drain connected to the output terminal and a source connected to the source of the second MOS transistor, and a fourth MOS transistor of a depletion type having a gate connected to the source of the third MOS transistor and a source connected to the output terminal. All the MOS transistors operate in a weak inversion region.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: November 3, 2020
    Assignee: ABLIC INC.
    Inventor: Kaoru Sakaguchi
  • Patent number: 10819296
    Abstract: Apparatus useful for receiving or transmitting voltage signals might include a current generator having first and second inputs and configured to generate a current flow between first and second outputs responsive to a voltage difference between its first and second inputs. The apparatus might further include a feedback amplifier having a first input connected to the first output of the current generator, a second input connected to the second output of the current generator, a first voltage signal node connected to its first input through a first resistance, and a second voltage signal node connected to its second input through a second resistance, wherein a first inverter is connected in parallel with the first resistance, a second inverter is connected in parallel with the second resistance, and a pair of cross-coupled inverters are connected between the first voltage signal node and the second voltage signal node.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Agatino Massimo Maccarrone, Luigi Pilolli
  • Patent number: 10819335
    Abstract: A reference voltage circuit includes a first output terminal from which a first reference voltage is supplied; a first MOS transistor of a depletion type, the first MOS transistor containing a drain connected to a power supply terminal, a gate connected to a ground terminal, and a source; a first voltage drop circuit including a first end connected to the source of the first MOS transistor and a second end connected to the first output terminal; and a second MOS transistor of a depletion type, the second MOS transistor containing a drain connected to the first output terminal, a gate connected to the ground terminal, and a source connected to the ground terminal.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: October 27, 2020
    Assignee: ABLIC Inc.
    Inventors: Kotaro Watanabe, Sukhwinder Singh
  • Patent number: 10811107
    Abstract: Provided are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes an external power supply voltage terminal configured to receive an external power supply voltage, an external ground voltage terminal configured to receive an external ground voltage, a ground voltage noise detector configured to detect a difference between the external ground voltage and an internal ground voltage of an internal ground voltage node and generate a ground voltage noise reference voltage, an internal power supply voltage reference voltage generator configured to generate an internal power supply voltage reference voltage based on the external power supply voltage and the ground voltage noise reference voltage, and an internal power supply voltage driver configured to generate an internal power supply voltage based on the internal power supply voltage reference voltage.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Ho Na, Young Sun Min, Dae Seok Byeon
  • Patent number: 10804917
    Abstract: A reference ripple suppression circuit adaptable to a successive approximation register (SAR) analog-to-digital converter (ADC) includes a plurality of code-dependent compensation cells, each including a logic circuit and a compensation capacitor. A first plate of the compensation capacitor is coupled to receive a reference voltage to be compensated, and a second plate of the compensation capacitor is coupled to receive an output of the logic circuit performing on an output code of the SAR ADC and at least one logic value representing a bottom-plate voltage of a switched digital-to-analog converter (DAC) of the SAR ADC. (k?1) of the code-dependent compensation cells are required maximally for k-th switching of the SAR ADC.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: October 13, 2020
    Assignees: NCKU Research and Development Foundation, Himax Technologies Limited
    Inventors: Soon-Jyh Chang, Hao-Sheng Wu
  • Patent number: 10775826
    Abstract: Embodiments of the present disclosure provide a circuit structure including: a first tap node, a first operational element coupled to the first tap node, the first operational element including at least one transistor having a back-gate, a second tap node coupled to the first operational unit, a second operational element coupled to the second tap node, the second operational element including at least one transistor having a back-gate, and a first back-gate biasing voltage regulator coupled to the second operational element and the first tap node. The first back-gate biasing voltage regulator is configured to supply the at least one transistor of the second operational element with a back-gate biasing voltage level that is different than a voltage level available to the second operational element from the second tap node.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ulrich G. Hensel, Jurgen Faul, Arif A. Siddiqi
  • Patent number: 10761552
    Abstract: An integrated circuit including a low drop out (LDO) regulator configured to implement transient response and loop stability in a capacitor-less configuration, including an error amplifier configured to receive a bandgap reference input; first and second pass elements configured to receive outputs from the error amplifier; first and second resistor feedback networks, the first resistor network configured to provide a feedback output as an input to the error amplifier; an overshoot protection circuit; and an output connected to the pass transistors; wherein the capacitor-less low dropout (LDO) regulator is operable without an output capacitor.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: September 1, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Raghuveer Murukumpet, Kent Lawrence, Asif Iqbal
  • Patent number: 10726910
    Abstract: Disclosed is a device including a sinking circuit to sink current from an output node and a driver circuit coupled to the sinking circuit. The driver circuit includes complementary differential pairs to receive a voltage at the output node and generate a control signal according to the received voltage. The sinking circuit is configured to change the current from the output node according to the control signal.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: July 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Albert Chang, Khin Htoo, Matt Chen
  • Patent number: 10720889
    Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate (i) a variable current and (ii) a constant current. The variable current may be proportional to a temperature of the first circuit. The second circuit may be configured to present a resistance through a plurality of first transistors between two ports in response to both the variable current and the constant current. The resistance may have a predefined dependence on the temperature.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 21, 2020
    Assignee: Integrated Device Technology, Inc.
    Inventors: Zhiyang Liu, Shawn Bawell
  • Patent number: 10715125
    Abstract: A circuit and a method for detecting a current zero-crossing point, and a circuit and method for detecting a load voltage are disclosed. The circuit for detecting current zero-crossing point includes: a load power supply circuit, a voltage-dividing resistor, a transistor switch, a zero-crossing detection circuit; the load power supply circuit includes: a load, a diode, and a transformer; one end of a primary winding of the transformer is connected with the operating voltage input terminal, the other end of the primary winding of the transformer is connected with a first end of the transistor switch and a first end of the voltage-dividing resistor, a second end of the voltage-dividing resistor and a second end of the transistor switch are connected with the ground, the load voltage is controlled by the transistor switch.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: July 14, 2020
    Assignee: JOULWATT TECHNOLOGY (HANGZHOU) CO., LTD
    Inventors: Pitleong Wong, Yang Lu, Yue Ji, Yuancheng Ren, Xunwei Zhou
  • Patent number: 10714038
    Abstract: A display device has an active matrix substrate including: a plurality of gate lines; a plurality of sub-gate lines provided to each of the gate lines, the sub-gate lines extends in a direction intersecting at right angles with a direction of the gate lines extending; first driving circuitry provided in a frame area and scanning the gate lines; a second driving circuitry provided in the frame area and scanning the sub-gate lines, where each of the sub-gate lines is connected with the gate line in a display area, the first driving circuitry supplies a scanning signal to each of the gate lines via both ends of the gate line, and the second driving circuitry includes n driving circuits supplying the scanning signal to each of the sub-gate lines, via at least one end of the sub-gate line.
    Type: Grant
    Filed: October 13, 2018
    Date of Patent: July 14, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Keisuke Yoshida
  • Patent number: 10665577
    Abstract: Techniques are disclosed for forming monolithic integrated circuit semiconductor structures that include a III-V portion implemented with III-N semiconductor materials, such as gallium nitride, indium nitride, aluminum nitride, and mixtures thereof. The disclosed semiconductor structures may further include a CMOS portion implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). The disclosed techniques can be used to form highly-efficient envelope tracking devices that include a voltage regulator and a radio frequency (RF) power amplifier that may both be located on the III-N portion of the semiconductor structure. Either of the CMOS or III-N portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of a III-N voltage regulator and RF power amplifier along with column IV CMOS devices on a single substrate.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: May 26, 2020
    Assignee: INTEL CORPORATION
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Seung Hoon Sung, Sanaz Gardner
  • Patent number: 10663996
    Abstract: There is provided a constant current circuit having a current characteristic satisfactory in a high voltage circuit while being low in manufacturing cost. The constant current circuit includes a high breakdown-voltage depletion type NMOS transistor and a low breakdown-voltage depletion type NMOS transistor connected in series between a first terminal and a second terminal. The low breakdown-voltage depletion type NMOS transistor includes a first depletion type NMOS transistor and a second depletion type NMOS transistor connected in series. The high breakdown-voltage depletion type NMOS transistor has a gate connected to a connecting point of the first depletion type NMOS transistor and the second depletion type NMOS transistor.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: May 26, 2020
    Assignee: ABLIC INC.
    Inventors: Takashi Matsuda, Fumihiko Maetani
  • Patent number: 10660180
    Abstract: Various embodiments of a light source driver are disclosed. In one embodiment, the light source driver may have a driving transistor coupled directly to at least one light source without having additional switches such that the light source driver may be operated with a low voltage supply. Optionally, the light source drivers may have a bypassing circuit configured to reduce power consumption, and peaking current generator configured to speed up the turn on time of the at least one light source. At least some of the circuits, and block diagrams disclosed herein may be implemented using conventional CMOS design and manufacturing techniques and processes to provide, for example, at least one or more integrated circuits.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: May 19, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventor: Kah Weng Lee