Abstract: Techniques are disclosed for forming monolithic integrated circuit semiconductor structures that include a III-V portion implemented with III-N semiconductor materials, such as gallium nitride, indium nitride, aluminum nitride, and mixtures thereof. The disclosed semiconductor structures may further include a CMOS portion implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). The disclosed techniques can be used to form highly-efficient envelope tracking devices that include a voltage regulator and a radio frequency (RF) power amplifier that may both be located on the III-N portion of the semiconductor structure. Either of the CMOS or III-N portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of a III-N voltage regulator and RF power amplifier along with column IV CMOS devices on a single substrate.

Abstract: There is provided a constant current circuit having a current characteristic satisfactory in a high voltage circuit while being low in manufacturing cost. The constant current circuit includes a high breakdown-voltage depletion type NMOS transistor and a low breakdown-voltage depletion type NMOS transistor connected in series between a first terminal and a second terminal. The low breakdown-voltage depletion type NMOS transistor includes a first depletion type NMOS transistor and a second depletion type NMOS transistor connected in series. The high breakdown-voltage depletion type NMOS transistor has a gate connected to a connecting point of the first depletion type NMOS transistor and the second depletion type NMOS transistor.

Abstract: Various embodiments of a light source driver are disclosed. In one embodiment, the light source driver may have a driving transistor coupled directly to at least one light source without having additional switches such that the light source driver may be operated with a low voltage supply. Optionally, the light source drivers may have a bypassing circuit configured to reduce power consumption, and peaking current generator configured to speed up the turn on time of the at least one light source. At least some of the circuits, and block diagrams disclosed herein may be implemented using conventional CMOS design and manufacturing techniques and processes to provide, for example, at least one or more integrated circuits.

Abstract: A detector circuit in which a change in a detection voltage due to temperature is suppressed is provided. The detector circuit includes a first rectification element having an anode to which an input signal is inputted. A second rectification element has a cathode connected with a cathode of the first rectification element and has an anode connected to an output terminal. A current mirror circuit for supplying a current to the first rectification element and for supplying a current-mirror current of the current to the second rectification element is included in the detector circuit.

Abstract: A current comparator including a first comparator configured to generate a first output signal based on a comparison of a first current to at least a second current; a second comparator configured to generate a second output signal based on a comparison of the first current to at least a third current; and a circuit configured to: direct the first current to the first comparator to perform the comparison of the first current to the at least the second current while blocking the first current from being applied to the second comparator; or direct the first current to the second comparator to perform the comparison of the first current to the at least the third current while blocking the first current from being applied to the first comparator.

Abstract: A semiconductor device on silicon-on-insulator (SOI) substrate includes: a first gate line and a second gate line extending along a first direction, a third gate extending along a second direction and between the first gate line and the second gate line, and a drain region adjacent to one side of the third gate line. Preferably, the third gate line includes a first protrusion overlapping the drain region.

Abstract: A signal transceiver includes a signal transmitter driving a first differential link between a supply voltage of the signal transmitter and a fraction of the supply voltage, and driving a second differential link between the faction of the supply voltage and a reference ground. The signal transceiver also includes a signal receiver in which the first differential link is coupled to a gate node of an NMOS transistor and to a source node of a PMOS transistor; and the second differential link is coupled to a source node of the NMOS transistor and to a gate node of the PMOS transistor.

Abstract: Disclosed is a device including a distributed controller and a common controller. The distributed controller includes a first circuit to generate an output voltage according to a control signal. The common controller includes a common feedback loop coupled to the distributed controller. The common feedback loop includes an amplifier circuit to generate the control signal, and a second circuit coupled to the amplifier circuit. The second circuit replicates the first circuit and stabilizes the control signal.

Abstract: A voltage holding circuit and an electronic device using thereof are provided. The voltage holding circuit includes a first transistor, a second transistor, and a first capacitor. A first terminal of the first transistor is coupled to an input voltage, and a control terminal of the first transistor receives a control signal. A first terminal of the second transistor is coupled to a second terminal of the first transistor, a second terminal of the second transistor is an output terminal of the voltage holding circuit, and a control terminal of the second transistor receives the control signal. A first terminal of the first capacitor is coupled to the second terminal of the first transistor and the first terminal of the second transistor. A holding voltage on the first terminal of the first capacitor is maintained by the first capacitor and parasitic diodes of the first transistor and the second transistor.

Abstract: A driver circuit for a transmitter includes a main path in parallel with an error correction path used for feed-forward error correction. The main path has an amplifier for amplifying a data signal to be transmitted from the transceiver. In parallel with the amplifier is a feedforward error correction circuit that provides an error correction signal that compensates for distortion introduced by the amplifier when the error correction signal is combined with the amplifier's output. The error correction circuit is designed to have a high impedance output so that voltage swings in the data signal do not create a demand for significant current from the feedforward error correction circuit, thereby reducing the current of the error correction signal. As an example, it is possible for the current of the error correction signal to substantially match that which is required to cancel the amplifier distortion, thereby minimizing distortion of the signal.

Abstract: A circuit and a method for detecting a current zero-crossing point, and a circuit and method for detecting a load voltage are disclosed.

Abstract: A semiconductor device includes a first a first transistor configured to operate at a first threshold voltage level. The first transistor includes a first gate structure and a first drain terminal electrically coupled to the first gate structure. The semiconductor device also includes a second transistor configured to operate at a second threshold voltage level different from the first threshold voltage level. The second transistor includes a second source terminal and a second gate structure electrically coupled to the first gate structure. The first gate structure and the second gate structure comprise a first component in common, and the second gate structure further includes at least one extra component disposed over the first component. The number of the at least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.

Abstract: An RC oscillator has a variable capacitor that sets the output frequency. The variable capacitor has m binary-weighted switched capacitor arrays, and each binary-weighted switched capacitor array has binary-weighted capacitors. p binary bits are decoded into an m-bit thermometer code that selects one of the m binary-weighted switched capacitor arrays to use n binary bits to switch its binary-weighted capacitors. Other binary-weighted switched capacitor arrays have all their capacitors switched on, or all their capacitors switched off by the thermometer code. The smallest or unit capacitance of each binary-weighted switched capacitor array is adjusted to compensate for the non-linear reciprocal relationship of frequency being proportional to 1/RC. The unit capacitance is increased for each successive binary-weighted switched capacitor array to reset to the ideal linear relationship of the (p,n)-bit code to frequency.

Abstract: A low-dropout shunt voltage regulator is provided, which includes a first current mirror module, a second current mirror module and an output module. A first terminal of the first current mirror module is electrically connected to the input voltage. The first current mirror module has high output resistance. A first terminal of the second current mirror module is electrically connected to a second terminal of the first current mirror module. A second terminal of the second current mirror module is electrically connected to a reference voltage. An output terminal of the output module is electrically connected to the third terminal of the first current mirror module. The output terminal and a first terminal of the output module are both connected to the second current mirror module. A second terminal of the output module is electrically connected to the reference voltage.

Abstract: A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a multiplexer coupled to the voltage divider, an operational amplifier that may receive a voltage from the multiplexer, and a plurality of resistors that may receive an output from the operational amplifier. The reference voltages may be provided from output terminals coupled to the resistors. A reference voltage generator may include a voltage divider, two multiplexers coupled to the voltage divider, an operational amplifier coupled to each multiplexer, and a plurality of resistors coupled between the outputs of the two operational amplifiers. Reference voltages may be provided from output terminals coupled to the resistors.

Abstract: A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a multiplexer coupled to the voltage divider, an operational amplifier that may receive a voltage from the multiplexer, and a plurality of resistors that may receive an output from the operational amplifier. The reference voltages may be provided from output terminals coupled to the resistors. A reference voltage generator may include a voltage divider, two multiplexers coupled to the voltage divider, an operational amplifier coupled to each multiplexer, and a plurality of resistors coupled between the outputs of the two operational amplifiers. Reference voltages may be provided from output terminals coupled to the resistors.

Abstract: In various embodiments, a circuit is provided. The circuit may include a plurality of cascode stages connected in series with one another, a voltage divider which is connected in parallel with the plurality of cascode stages and is coupled to the cascode stages in order to make available a first electrical backup potential at least one cascode stage of the plurality of cascode stages, and a controller which is configured to couple the at least one cascode stage of the plurality of cascode stages to a predefined second electrical backup potential if a voltage which is present at the voltage divider satisfies a predefined criterion.

Abstract: A technique for reducing jitter in an oscillating signal generated by an oscillator circuit includes reducing feedback of gate leakage current while increasing electrostatic discharge protection and reducing regulated power supply requirements of the oscillator circuit, as compared to conventional oscillator circuits. A circuit includes a first integrated circuit terminal and a thick gate native transistor of a first conductivity type having a first gate terminal having a first gate thickness. The first gate terminal is coupled to the first integrated circuit terminal. The thick gate native transistor has a first threshold voltage. The thick gate native transistor is configured as a source follower. The circuit includes a second transistor of the first conductivity type having a second gate terminal with a second gate thickness less than the first gate thickness. The second gate terminal is coupled to a source terminal of the thick gate native transistor.

Abstract: An integrated circuit including a low drop out (LDO) regulator configured to implement transient response and loop stability in a capacitor-less configuration, including an error amplifier configured to receive a bandgap reference input; first and second pass elements configured to receive outputs from the error amplifier; first and second resistor feedback networks, the first resistor network configured to provide a feedback output as an input to the error amplifier; an overshoot protection circuit; and an output connected to the pass transistors; wherein the capacitor-less low dropout (LDO) regulator is operable without an output capacitor.

Abstract: A display device includes: a display unit, a driver unit, and a control unit. The display unit includes a plurality of pixel units arranged in a matrix. The driver unit includes an output transistor configured to drive a plurality of scanning lines connected to the plurality of pixel units. The control unit is configured to supply to the driver unit in a display period, a signal for displaying an image on the display unit, and control a bias state of the output transistor in a display suspension period, so that an absolute value of a threshold voltage of the output transistor which is increased in the display period decreases.

Abstract: Aspects of the disclosure are directed to an apparatus for separating a second fluid or a particulate from a host fluid. That apparatus comprises a flow chamber with at least one inlet and at least one outlet. A drive circuit configured to provide a drive signal to a filter circuit configured to receive the drive signal and provide a translated drive signal. An ultrasonic transducer is cooperatively arranged with the flow chamber, and transducer includes at least one piezoelectric element configured to be driven by the current drive signal to create an acoustic standing wave in the flow chamber. At least one reflector opposing the ultrasonic transducer to reflect acoustic energy.

Abstract: An internal voltage generation device includes a voltage generation block configured to compare a reference voltage and a divided voltage, and generate an output voltage; and an internal voltage driving block including a pull-up driving unit which selectively pull-up drives an internal voltage according to the output voltage, and configured to output the output voltage to the pull-up driving unit through different paths according to a test signal.

Abstract: An image display device includes: a pixel array part formed of first to fourth scanning lines arranged in rows, signal lines arranged in columns, pixel circuits in a matrix connected to the scanning lines and signal lines, and a plurality of power source lines which supplies first to third potentials necessary for the operations of pixel circuit; a signal part which supplies a video signal to the signal lines; and a scanner part which supplies a control signal to the first to fourth scanning lines, and in turn scans the pixel circuit for every row, wherein the pixel circuits include a sampling transistor, a drive transistor, first to third switching transistors, a pixel capacitance, and a light emitting device, and a channel length of the drive transistor is made longer than a channel length of the switching transistors to suppress fluctuations in threshold voltage.

Abstract: A process information extractor circuit includes: a transistor array including a plurality of transistors, and configured such that, among the plurality of transistors, the number of transistors electrically coupled in series is adjusted depending on a code; a current source suitable for adjusting the amount of current flowing through the transistor array to a predetermined value; a comparator suitable for comparing a gate voltage of the transistors electrically coupled in series in the transistor array, with a reference voltage; and a code generator suitable for generating the code according to a comparison result of the comparator.

Abstract: Methods and circuits for maximizing gain of a voltage follower circuit are provided. The method includes using a NMOS voltage replica generation circuit, a PMOS voltage replica generation circuit, a NPN BJT voltage replica generation circuit, a n-channel JFET voltage replica generation circuit, a P-Channel JFET voltage replica generation circuit and a PNP BJT voltage replica generation circuit. The overall gain for the various transistor families is almost equal to unity.

Abstract: A rectangular-shaped interlevel connection layout structure is defined to electrically connect a first layout structure in a first chip level with a second layout structure in a second chip level. The rectangular-shaped interlevel connection layout structure is defined by an as-drawn cross-section having at least one dimension larger than a corresponding dimension of either the first layout structure, the second layout structure, or both the first and second layout structures. A dimension of the rectangular-shaped interlevel connection layout structure can exceed a normal maximum size in one direction in exchange for a reduced size in another direction. The rectangular-shaped interlevel connection layout structure can be placed in accordance with a gridpoint of a virtual grid defined by two perpendicular sets of virtual lines. Also, the first and/or second layout structures can be spatially oriented and/or placed in accordance with one or both of the two perpendicular sets of virtual lines.

Abstract: Representative implementations of devices and techniques provide a reduction in the spread of a bandgap voltage of a bandgap reference circuit. The biasing current for a target bipolar device is conditioned by passing it through one or more like bipolar devices prior to biasing the target bipolar device.

Abstract: The disclosure relates to a circuitry including a first contact connected to a power supply, a first compare unit connected to the first contact and to a first reference signal, wherein the first compare unit is configured to compare a voltage at the first contact with the first reference signal and provide a first output signal for further processing.

Abstract: A bias current topology with embodiments in current source, current reference, (pseudo bandgap) voltage reference, and bandgap voltage reference that operate at ultra low currents and low power supply voltages which may use main stream standard digital Complementary Metal-Oxide-Semiconductor (CMOS) processes. The bias current topology uses chiefly a self cascode (SC), whose active resistor MOSFET is paced in series with the gate input of the MOSFETs that help generate the proportional to absolute temperature (PTAT) voltage that is applied to the active resistor MOSFET to produce a bias current.

Abstract: The initialization signal generation circuit includes a first driver and a second driver. The first driver includes at least one passive element and drives an initialization signal while a level of an external voltage signal reaches an initial level. The second driver drives the initialization signal in response to a control signal from a point of time that a level of the external voltage signal reaches the initial level.

Abstract: An apparatus comprises a first signal input, a first transistor, a first line, a first circuit coupled to the first transistor through the first line, a second line coupled to the first line between the first transistor and the first circuit, a second transistor coupled to the first transistor through the second line, a second circuit coupled to the second transistor, the first circuit being a replica of the second circuit, a second signal input, and a third transistor coupled to the second signal input and the second circuit. The apparatus maintains a virtual voltage of the second circuit above a predetermined threshold by a voltage associated with the second line. The voltage associated with the second line is based on a difference between a first current associated with a portion of the first line and a second current associated with another portion of the first line.

Abstract: A nonvolatile memory device having a first resistive element coupled between a common node and a bit line; a second resistive element coupled between the common node and a word line; and a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output, wherein the word line is orthogonal to the bit line.

Abstract: A programmable linear voltage regulator and system for programming the regulator that improves the speed, power usage, and stability over conventional linear voltage regulators is disclosed. A controller that has knowledge of the current or expected activation of various loads sends bias control signals to a programmable biasing circuit of an error amplifier in the voltage regulator to adjust the bias current in accordance with the load current the regulator produces or is expected to produce. A look up table associated with the controller can be used to correlate the bias control signals with current or expected load conditions. Programming of the programmable biasing circuit may precede the enablement of a new load condition to ready the voltage regulator to handle the upcoming change in load current.

Abstract: An integrated circuit includes: a voltage rail; voltage control circuitry coupled to the voltage rail; and a circuit block coupled to the voltage control circuitry; wherein the voltage control circuitry is selectively configurable to operate the circuit block in at least a first mode of operation and a second mode of operation; wherein in the first mode of operation, the circuit block receives a voltage that is substantially the same as a voltage of the voltage rail; and wherein in the second mode of operation, the circuit block receives a voltage that is less than the voltage of the voltage rail by a threshold voltage.

Abstract: An audio signal processing device includes: an input section to which an audio signal is input; a bias processing section configured to add a bias signal to the audio signal; a calculation section configured to perform a power calculation on the audio signal to which the bias signal has been added by the bias processing section; and an adding unit configured to add the audio signal on which the power calculation is performed by the calculation section to the audio signal having been input to the input section.

Abstract: A device includes a voltage buffer, a load compensation circuit, and a closed-loop current feedback circuit. The voltage buffer is configured to output an output voltage and an output current. The output current is the sum of a load current and a bias current. The load compensation circuit is configured to output the bias current at a variable level based on a variation in the load current. The closed-loop current feedback circuit is configured to feedback a voltage level based on the variation to the load compensation circuit.

Abstract: A semiconductor device fabrication operation is commonly used to manufacture one or more integrated circuits onto a semiconductor substrate. The semiconductor device fabrication operation forms one or more transistors onto an arrangement of fabrication layers to form the one or more integrated circuits which introduces unwanted capacitances, often referred to as parasitic capacitances, into the one or more transistors. The one or more integrated circuits include one or more compensation modules that, when combined with the parasitic capacitances of the one or more transistors, ideally linearizes the non-linearity caused by the parasitic capacitances of the one or more transistors. For example, the one or more compensation modules incorporate a non-linear or a piecewise linear transfer function that is inversely related to the parasitic capacitances of the one or more transistors.

Abstract: A connection device for connecting a load to a power supply, comprising at least first and second current control devices arranged in parallel between the power supply and the load, and a controller arranged to switch the current control devices on in sequence for temporally overlapping on periods.

Abstract: In a method of operating a nonvolatile memory device, an impedance calibration verifying operation is performed based on a data read command. The impedance calibration verifying operation ascertains whether an impedance calibration operation is normally performed for a data input/output (I/O) terminal of the nonvolatile memory device. A detection value is stored in a storage unit. The detection value indicates a result of the impedance calibration verifying operation. The detection value is output based on a first command received after the nonvolatile memory device receives the data read command. A data read operation or the impedance calibration operation is selectively performed based on the detection value.

Abstract: A semiconductor device comprises a plurality of semiconductor chips stacked on a substrate. The semiconductor chip comprises: an internal power supply voltage generating circuit that generates an internal power supply voltage based on an external power supply; a power supply line that supplies the internal power supply voltage; an internal power supply pad connected to the power supply line; and a stabilizing capacitance connected to the power supply line. The internal power supply pad is electrically short-circuited with the internal power supply pad included in another semiconductor chip.

Abstract: A finger sensor may include pixels, pixel sensing traces each associated with a respective pixel, and electrodes overlying the pixel sensing traces. The finger sensor may also include pixel sensing circuitry coupled to the pixel sensing traces and the electrodes. The pixel sensing circuitry may be capable of operating in a measurement mode by operating the pixels so that at least some of the pixels are active, and at least some other of the pixels are inactive and coupling pixel sensing traces associated with the inactive pixels to a voltage reference. The pixel sensing circuitry may also be capable of operating in the measurement mode by coupling electrodes associated with the active pixels to the voltage reference and coupling electrodes associated with the inactive pixels to a drive signal.

Abstract: An output circuit includes first, second and third transistors. The first transistor includes first and second diffusion layers. The third transistor includes third and fourth diffusion layers. The first transistor shares the second diffusion layer with the second transistor and the third transistor shares the third diffusion layer with the second transistor. The second transistor is rendered conductive responsive to an activation of a first signal and non-conductive responsive to an inactivation of the first signal. The first and third transistors are rendered conductive responsive to an activation of a second signal that is different from the first signal and rendered non-conductive responsive to an in activation of the second signal.

Abstract: Methods, and apparatus configured to perform such methods, providing peak power management are useful in mitigating excessive current levels within a multi-die package. For example, a method might include providing a clock signal, counting primary clock cycles of the clock signal in a counter, monitoring an indication of high current demand for each die of the multi-die package, and determining a total unit consumption of current. The method may further include pausing an access operation for a particular die of the multi-die package at a designated point, and resuming the access operation if a value of the total unit consumption is less than or equal to a unit limit when a count value of the counter matches an assigned counter value of the particular die.

Abstract: An exemplary embodiment of the present disclosure provides a programming voltage generator for a nonvolatile memory device. The programming voltage generator comprises a power circuit, a detector, a switching circuit, a control signal generator, and a regulation circuit. The power circuit outputs a programming voltage according to a voltage control signal. The detector detects whether the programming voltage is larger than or equal to a breakdown voltage of the nonvolatile memory device, so as to output an indication signal. The switching circuit temporally drops the programming voltage according to the indication signal. The control signal generator generates a plurality of regulation control signals. The regulation circuit generates the voltage control signal according to the programming voltage and the regulation control signals.

Abstract: Described herein is an apparatus and system of a low-impedance reference voltage generator. The apparatus comprises: a voltage-control loop including a first transistor to provide an output voltage; and a current-control loop to sense current through the first transistor, relative to a reference current. The node having the output voltage is a low-impedance node.

Abstract: A switchable bias current biases, in an operational state, a differential amplifier with a full-slew bias current. A system on/off signal transitions from an operational state to a power-down state. The transition disables the differential amplifier and switches the switchable bias current to a reduced slew bias current. The system on/off signal transitions from the power-down state to the operational state, the differential amplifier is enabled, and the switchable bias current is delayed, by a reduced slew duration, from switching to the full-slew bias current. The enabled differential amplifier slews toward a reference voltage at a reduced slew rate caused by the reduced slew bias current. The switchable bias current, after the reduced slew duration, switches to the full-slew bias current. Optionally, a regulated pass gate is disabled in response to the system on/off signal transitioning from the operational state to the power-down state.

Abstract: A device includes a bandgap reference circuit and a start-up circuit. The bandgap reference circuit includes an amplifier and a first transistor. The amplifier has an inverting input terminal, a non-inverting input terminal, and an output terminal. The first transistor has a gate electrode electrically connected to the output terminal. The start-up circuit has a first path electrically connected to the output terminal and the non-inverting input terminal, and a second path electrically connected to the output terminal and the inverting input terminal.

Abstract: A multi level charge pump circuit may be associated with at least two power supplies, and may provide at least four levels of positive and negative voltage. The multi level charge pump may include first and second fly capacitors, and first and second tank capacitors. A plurality of PMOS transistors and NMOS transistors may allow generation of two high voltage levels and two low voltage levels for the multi level charge pump, the low voltage levels being derived from a charging of the two fly capacitors in series. This multi level charge pump may be embodied in an audio device within a platform without a dedicated SMPS circuit.

Abstract: A voltage reference generation circuit includes a current supply circuit and a core circuit. The current supply circuit is arranged to provide a plurality of currents. The core circuit is coupled to the current supply circuit, and arranged to receive the currents and accordingly generate a voltage reference. The core circuit includes a first transistor, a second transistor and a third transistor, wherein the first transistor and the third transistor generate a first gate-to-source voltage and a third gate-to-source voltage, respectively, according to a first current of the received currents; the second transistor generates a second gate-to-source voltage according to a second current of the received currents; and the voltage reference is generated according to the first gate-to-source voltage, the second gate-to-source voltage and the third gate-to-source voltage.

Abstract: A reference voltage generator has a depletion mode MOS transistor of a first conductivity type for supplying a constant current flow, and an enhancement mode MOS transistor of the first conductivity type having a diode connection to the depletion mode MOS transistor for generating a reference voltage based on a constant current supplied by the depletion mode MOS transistor. The enhancement mode MOS transistor has a mobility substantially equal to a mobility of the depletion mode MOS transistor such that the enhancement mode MOS transistor and the depletion mode MOS transistor have substantially equal temperature characteristics.