Abstract: A voltage regulator includes an error amplifier which receives a feedback voltage and a reference voltage, an amplifier circuit which receives an output voltage of the error amplifier and controls a gate of an output transistor by a first output voltage, and a non-regulation detection circuit which detects a non-regulation state of the voltage regulator based on a second output voltage of the amplifier circuit. The amplifier circuit includes a first transistor receiving the output voltage of the error amplifier at a gate of the first transistor, and a second transistor connected to a drain of the first transistor, and provides the second output voltage based on a gate-source voltage of the second transistor.

Abstract: An input circuit according to an embodiment includes an input terminal, a power terminal, an internal circuit, an input section, a power supply section, and a first circuit. The input section includes first and resistive parts, and a first transistor. The first resistive part is connected to the input terminal. The second resistive part is connected to the first resistive part. The gate of the first transistor is connected to the first resistive part. The first circuit includes a fifth resistive part and a third transistor. The fifth resistive part is connected to the second resistive part and a grounding line. The gate and one end of the third transistor are connected to the second resistive part. The other end of the third transistor is connected to the grounding line.

Abstract: Drones convertible into personal computers are disclosed, A disclosed unmanned aerial vehicle (UAV) includes a body and rotors carried by the body. The rotors move relative to the body from a first position when the UAV is in a drone mode to a second position when the UAV is in a computer mode.

Abstract: An apparatus includes a circuit that has a normal mode of operation and a low-power mode of operation. The circuit consumes more power in the normal mode of operation than in the low-power mode of operation. The apparatus further includes a power-supply circuit. The power-supply circuit provides a normal supply voltage to the circuit in the normal mode of operation. The power-supply circuit includes a non-linear circuit to provide a compressed supply voltage to the circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.

Abstract: A voltage compensation circuit and a voltage compensation method are provided. The voltage compensation circuit detects the load current provided by a power supply, generates a load voltage according to the load current, and compares the load voltage with at least one reference voltage to generate a switch control signal. The voltage compensation circuit further drives the at least one switch according to the switch control signal, provides a compensation resistance value according to the at least one switch that is turned on, and provides a compensation voltage to the power supply, so that the power supply provides a precise output voltage.

Abstract: The disclosure relates to an isolation and voltage regulation circuit for an electrochemical power source, the circuit comprising: an input terminal (202) for coupling to the power source and receiving an input voltage (Vin) from the power source; an output terminal (204) for coupling to a load; a diode circuit (206) connected between the input terminal and the output terminal; a diode controller (208) configured to control electrical conduction through the diode circuit between the input terminal and the output terminal, the diode controller having a first controller input (210) coupled to the output terminal and a second controller input (212); and a reference controller (220) configured to set a voltage at the second controller input (212) in accordance with a comparison between the input voltage (Vin) and a reference voltage (Vref).

Abstract: A system includes a first circuit, a second circuit and a regulator. The first circuit is configured to operate at a first operating voltage, wherein the first operating voltage drops by a first voltage level while the first circuit operates. The second circuit is coupled with the first circuit at a tap, and configured to operate at a second operating voltage. The regulator is configured to provide a supply voltage to the first circuit and the second circuit via the tap. The regulator is also configured to raise the supply voltage in response to the first voltage level.

Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

Abstract: A circuit includes an amplifier having a first power terminal configured to be coupled to a supply voltage and a second power terminal configured to be coupled to a reference potential. The circuit further includes a first impedance element coupled between a first input terminal of the amplifier and a first output terminal of the amplifier. The circuit additionally includes a second impedance element coupled between the first input terminal and the reference potential. The amplifier is configured to output a first voltage at a second output terminal of the amplifier in response to the supply voltage being greater than an output voltage at the first output terminal of the amplifier. The amplifier is further configured to output a second voltage at the second output terminal of the amplifier in response to the supply voltage being less than the output voltage at the first output terminal of the amplifier.

Abstract: A current mirror arrangement for duplex bidirectional communication between two circuit units may include in each circuit unit two identical transistors with their bases (36, 37) connected together and their bases and their collectors connected to each other respectively. Further, each of the connections between the bases and the collectors may be formed via a MOSFET. The MOSFETs of both circuit units may be connected together. More specifically, the MOSFETs' parasitic diodes of each circuit unit may be arranged in opposite directions with respect to the current system. The pair of MOSFETs in a first of the two circuit units may comprise n-channel enhancement-mode MOSFETs, and the pair of MOSFETs in a second of the two circuit units may comprise p-channel enhancement-mode MOSFETs.

Abstract: A bias circuit for power amplifiers is disclosed. A power amplifier bias circuit can include an emitter follower device and an emitter follower mirror device coupled to form a mirror configuration. The emitter follower device can be configured to provide a bias signal for a power amplifier at an output port. The power amplifier bias circuit can include a reference device configured to mirror an amplifying transistor of an amplifying device of the power amplifier. The emitter follower mirror device can be configured to provide a mirror bias signal to the reference device. A node between the emitter follower device and the emitter follower mirror device can have a voltage of approximately twice a base-emitter voltage (2Vbe) of the amplifying transistor.

Abstract: A device includes a circuit cell, a voltage regulator, a first switching unit, a second switching unit, and a third switching unit. The voltage regulator is configured to output a write voltage. The first switching unit is configured to generate, in response to a control voltage, a current represented by an auxiliary signal. The second switching unit is configured to receive the auxiliary signal, and to turn on to transmit the auxiliary signal to the circuit cell. The third switching unit is configured to receive the write voltage, and to turn on to transmit the write voltage to the circuit cell.

Abstract: A semiconductor device, a semiconductor system, and a control method of a semiconductor device are capable of accurately monitoring the lowest operating voltage of a circuit to be monitored. According to one embodiment, a monitor unit of a semiconductor system includes a voltage monitor that is driven by a second power supply voltage different from a first power supply voltage supplied to an internal circuit that is a circuit to be monitored and monitors the first power supply voltage, and a delay monitor that is driven by the first power supply voltage and monitors the signal propagation period of time of a critical path in the internal circuit.

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

Abstract: A semiconductor circuit in the disclosure includes a first circuit that is able to generate, on the basis of a voltage in a first node, an inverted voltage of the voltage and to apply the inverted voltage to a second node; a second circuit that is able to generate, on the basis of a voltage in the second node, an inverted voltage of the voltage and to apply the inverted voltage to the first node; a first transistor that couples the first node to a third node; a second transistor that supplies a first direct-current voltage to the third node; a third transistor including a drain or a source to be coupled to the third node and including a gate coupled to the first node or the second node; and a first storage element that is coupled to the third node, and is able to take a first resistance state or a second resistance state. The first circuit and the second circuit are configured to cause the voltage in the first node to easily become a predetermined initial voltage after application of power.

Abstract: Apparatus and associated methods relate to a dynamic quantizer circuit including a tail voltage supply magnitude (VTAIL) distinct from a general supply voltage (Avcc/Avss), VTAIL providing power to a tail clock buffer to generate tail clock signals to tail devices. In an illustrative example, a compensation processor may control a regulator producing a determined VTAIL value in response to one or more parametric signals, for example, the Avcc voltage value, a circuit temperature and a transistor speed process (TSP). The TSP signal may be determined, for example, by process-dependent circuit devices. The compensation processor may be, for example, configured to lower VTAIL in response to detecting a worst-case RMS noise corner, or to raise VTAIL in response to detecting a worst-case clock-to-q corner. Various adjustable VTAILs may be configured to continuously optimize RMS noise, offset and speed performance with low power consumption in various quantizers over process, voltage and/or temperature.

Abstract: A voltage regulation method, a controller, and a chip are provided. In the method, a controller receives a digital first status representation value sent by a sensor; the controller determines, according to the first status representation value and at least one of a second status representation value or a first expected value, whether to regulate the supply voltage of the load, where the second status representation value represents a node voltage that is at a previous moment and that is of the detection point of the load, and the first expected value represents an expected value of a node voltage of the detection point; and when determining to regulate the supply voltage of the load, the controller sends a digital control signal to a power gating array, to control the power gating array to regulate the supply voltage.

Abstract: The present application provides a capacitance sensing circuit, comprising an integrating circuit, comprising an integrating input terminal, coupled to the touch capacitance, wherein the integrating input terminal receives an input voltage; and an integrating output terminal, configured to output an output voltage; a comparator; a positive digital-to-analog (DA) converting unit; a negative DA converting unit; a control circuit, configured to control the positive DA converting unit and the negative DA converting unit; and a logic circuit, configured to output an output code, wherein the output code is related to a capacitance of the touch capacitance.

Abstract: Provided is a voltage regulator capable of stably suppressing overshoot. The voltage regulator includes a non-regulated state detection circuit for detecting a non-regulated state, and an overshoot suppression circuit. The overshoot suppression circuit is configured to operate when the non-regulated state detection circuit detects the non-regulated state.

Abstract: An apparatus includes a circuit that has a normal mode of operation and a low-power mode of operation. The circuit consumes more power in the normal mode of operation than in the low-power mode of operation. The apparatus further includes a power-supply circuit. The power-supply circuit provides a normal supply voltage to the circuit in the normal mode of operation. The power-supply circuit includes a non-linear circuit to provide a compressed supply voltage to the circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.

Abstract: In some examples, a device includes a power switch, a sensing switch configured to conduct an electrical current based on an electrical current conducted by the power switch. In some examples, the device also includes trimming circuitry configured to generate a monitored electrical current based on an aspect ratio of the trimming circuitry and based on the electrical current conducted by the sensing switch, wherein the aspect ratio of the trimming circuitry is adjustable.

Abstract: A semiconductor circuit includes a differential amplifier having a first positive terminal, a second positive terminal, a first negative terminal, a second negative terminal, and an output terminal. The output voltage is at a level that corresponds to a voltage level obtained by subtracting a voltage of the first negative terminal and the second negative terminal from a voltage sum of the first positive terminal and the second positive terminal. A first diode has a first anode connected to one of the first positive or the first negative terminal. A second diode has a second anode connected to the other of the first negative and first positive terminal. A predetermined reference voltage is applied to the second positive terminal. And a voltage corresponding to the output voltage of the differential amplifier is fed back to the second negative terminal.

Abstract: Described herein are technologies related to an implementation of a system to measure and compensate non-linearity (e.g., echo cancellation) in a transceiver circuitry of a device. Particularly, the echo cancellation utilizes reduced number of components for power savings, and further increases efficiency of signal or data packet transmissions in the device. An echo signal is determined by sampling a power amplifier output signal. The output signal is split into signals with different delays. Down conversion and digital interpolation of the signal with the shortest delay is performed. An echo cancellation signal is calculated based on the output signal as received as an input signal to a receive chain. The calculated signal is subtracted from a received echo signal to generate an echo free signal.

Abstract: A gate driving circuit is disclosed. The output circuit is connected with the input circuit and the pulling circuit at a first node, responding to scanning driving signal of previous stage to set the pulling circuit in a first status, using a first reference voltage level to set the first node at a first voltage, and held. The output circuit outputs scanning driving signal of current stage according to a first clock signal. The stabilizing circuit is connected with the pulling circuit at a second node, using the first reference voltage level to set the second node at the first voltage, and held. The pulling control circuit responds to a second clock signal to set the pulling circuit in a second status, using a second reference voltage level to pull voltages of the first and second nodes and to hold the voltages. Accordingly, a current leakage can be reduced.

Abstract: In a pressure detecting apparatus, a pressure sensor includes a piezoelectric sheet that generates a piezoelectric signal according to a load that is applied. A touch detecting unit detects contact with the pressure sensor. An acquirer acquires a piezoelectric output based on the piezoelectric signal. A rate-of-change calculator calculates a rate of change with respect to time of the piezoelectric output acquired within an arbitrary time range before a touch detection time when the touch detecting unit detects contact with the pressure sensor. An applied pressure calculator calculates applied pressure by correcting the piezoelectric output acquired after an end time of the time range used in the calculation of the rate of change using the rate of change. The apparatus enables precise measurement of applied pressure in a pressure sensor.

Abstract: Systems and methods for conditioning a power rail (e.g., reducing voltage droops and/or voltage overshoots on the power rail) are described herein. In one embodiment, a power circuit comprises a capacitor coupled to a high-voltage rail, and a droop slope limiter (DSL) coupled between the high-voltage rail and a power rail. The DSL is configured to detect a downward voltage slope on the power rail, and to control current flow from the high-voltage rail to the power rail through the DSL based on the detected downward voltage slope.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.

Abstract: A physical quantity detecting sensor includes a physical quantity detecting sensor element and an IC connected to the physical quantity detecting sensor element. The IC includes: a logic circuit; an analog circuit; a first regulator that supplies a logic power supply voltage generated based on a power supply voltage to the logic circuit; a second regulator that is switched to enable or disable and supplies an analog power supply voltage, which is generated based on the power supply voltage when the second regulator is set to enable, to the analog circuit; and a switch for supplying the logic power supply voltage to the analog circuit when the second regulator is set to disable.

Abstract: A system is based on an IC. A first component of the IC generates a signal that clocks the IC at a target operating frequency. A period corresponding to the target clock frequency exceeds a duration of a longest critical path associated with the IC. The first component and synchronous logic of the IC clocked therewith, each functions with the core supply voltage, which may be supplied to each via the same power supply rail. A second IC component detects errors that relate to an operation of the IC at the target clock frequency and determines a level for adjusting the core supply voltage. The Vdd adjustment ameliorates the frequency error. The voltage determination uses closed loop dynamic voltage and frequency scaling.

Abstract: A low-power low-dropout (LDO) voltage regulator device includes an error amplifier, a level-shifter circuit, and an NMOS pass transistor. The error amplifier compares a sampled portion of a regulated output voltage of the LDO voltage regulator with a reference voltage and generates an error signal. The level-shifter circuit is coupled to the error amplifier. The NMOS pass transistor provides the regulated output voltage with low dropout operation. The level-shifter circuit can shift a voltage level of the error signal to facilitate the low dropout operation of the NMOS pass transistor.

Abstract: An internal voltage generator includes: a comparison block suitable for comparing an internal voltage with a reference voltage and generating a first comparison signal having an analog level corresponding to a comparison result a first driving block suitable for driving an output terminal of the internal voltage with a source voltage in response to the first comparison signal; a logic block suitable for generating a second comparison signal having a logic level based on the first comparison signal; and a second driving block suitable for driving the output terminal of the internal voltage with the source voltage based on the second comparison signal.

Abstract: A voltage regulator includes a pass element, a buffer, and an error amplifier. The voltage regulator further includes a fast push-pull driver that has an inverter type amplification structure, is connected between a power output and a control input of the pass element, and reduces positive and negative peaks of the power output at a speed faster than a speed of a main feedback loop.

Abstract: Radio frequency identification (RFID) devices are provided including a contactless internal voltage generator configured to generate a rectification voltage responsive to a radio frequency (RF) input signal and an internal voltage responsive to the generated rectification voltage and a reference voltage; a clock generator configured to sense an amount of current to a sink path of the contactless internal voltage generator and to generate a clock signal using a variable resistance value, the variable resistance value based on the amount of current sensed; and an internal circuit driven by the internal voltage and the clock signal.

Abstract: A method and module for monitoring a voltage of a power cell, sampling and holding a voltage of the power cell, and balancing a voltage of the power cell. In accordance with an embodiment, an interface circuit is capable of operation in a plurality of operating modes. In accordance with another embodiment, the interface circuit is coupled to a filter section.

Abstract: A programming element including a first transistor, a second transistor, and a capacitor between a logic circuit using a semiconductor element and a power supply is provided. In the programming element, a node where a drain electrode of the first transistor, a gate electrode of the second transistor, and one of electrodes of the capacitor are electrically connected to each other is formed. A potential can be supplied to each of a source electrode of the first transistor and the other of the electrodes of the capacitor. The power supply and the logic circuit are electrically connected to each other through a source electrode and a drain electrode of the second transistor. A connection state between the power supply and the logic circuit is controlled in accordance with the state of the second transistor.

Abstract: An integrated circuit including a phase detector; a first charge pump and a second charge pump coupled to the phase detector, and configured to receive inputs from the phase detector, the first charge pump outputting a low current and the second charge pump outputting a high current; and a dual input loop filter coupled to the first charge pump and the second charge pump.

Abstract: Detection circuits cause a power supply circuit to start an initialization sequence by detecting abnormal behavior where an external power supply voltage is cut off, the power supply circuit generating a first internal power supply voltage from a first external power supply voltage and generating a second internal power supply voltage from a second external power supply voltage higher than the first external power supply voltage in terms of an absolute value, and an auxiliary amplifier that makes up for a drop in the first internal power supply voltage, using the second external power supply voltage as an operation power supply after detecting the abnormal behavior of the first external power supply voltage. A sample and hold circuit of a reference voltage of the auxiliary amplifier is configured in a hold state after detecting the abnormal behavior of the first external power supply voltage.

Abstract: In response to a first reference voltage, a regulator regulates an output voltage of a line, so that the output voltage is approximately equal to a target voltage. In response to the output voltage rising above a second reference voltage, pull down circuitry draws current from the line. In response to the output voltage falling below the second reference voltage by at least a predetermined amount, the pull down circuitry ceases to draw current from the line. The first and second reference voltages are based upon a same band gap reference as one another.

Abstract: The invention provides a voltage regulator. The voltage regulator (100) of the invention includes a comparison circuit (20) and a voltage divider circuit (110). The voltage divider circuit (110) has a PMOS transistor (T6) connected to a voltage source (VDD) and resistors (R1, R2, R3, R4, R5 and R6) serially connected between the transistor (T6) and a reference voltage. A feedback voltage generated from a node (N3) between resistors R4 and R5 is provided to the comparison circuit (20). In addition, a middle voltage (Vm) generated from a node (Nc) of the resistors is provided to a well region, so the parasitic capacitance is reduced.

Abstract: To provide a semiconductor device with such a new structure that the effect of variation in transistor characteristics can be reduced to achieve less variation in the output voltage of a memory cell. A memory cell includes a source follower (common drain) transistor for reading data held in a gate. A voltage applied to a transistor generating a reference current flowing through the memory cell is determined so that a gate-source voltage is approximately equal to the threshold voltage of the transistor. With such a structure, data stored in the memory cell can be read as a voltage that is less influenced by variation of transistors such as the field-effect mobility and the size.

Abstract: A low drop out voltage regulator includes an operational transconductance amplifier configured to be supplied with a supply voltage of the regulator, receive as inputs a reference voltage and a feedback voltage, and generate an intermediate current based upon a difference between the reference voltage and the feedback voltage. A current-to-voltage amplification stage is configured to be supplied with a boosted voltage greater than the supply voltage from a high voltage line, receive as input the intermediate current, and generate a driving voltage that is changed based upon the intermediate current. A pass transistor is controlled with the driving voltage to keep constant on a second conduction terminal thereof a regulated output voltage. A feedback network generates the feedback voltage based on the regulated output voltage.

Abstract: A front-end circuit for measurement devices, for example oscilloscopes or digitizers, may implement DC gain compensation using a programmable variable resistance. A MOS transistor may be configured and operated as a linear resistor with the ability to self-calibrate quickly, while compensating for temperature variations. An integrated CMOS-based variable resistor may be thereby used for an analog adjustable attenuator. Master and slave CMOS transistors may be operated in linear mode, and temperature effects on the linear transistors may be compensated for by using an integral loop controller (current controller) configured around the master MOS transistor. Circuits implemented with the compensated variable resistance have a wide range of adjustment with a control voltage, and may be used in the front-end (circuits) of an oscilloscope or digitizer, or in any other circuit and/or instrumentation benefitting from an adjustable attenuator.

Abstract: According to one embodiment, the voltage divider circuit divides the output voltage, and generates a feedback voltage. The output voltage switching transistor has one end connected to a feedback voltage side, and operates based on an output voltage switching signal. The first condenser has one end connected to the one end of the output voltage switching transistor, and the other end connected to a control terminal of the output voltage switching transistor.

Abstract: An electromagnetic coil drive device has a semiconductor switch connected in series with an electromagnetic coil for controlling a current supplied to the coil; a capacitor; a comparator for comparing a voltage to charge and discharge the capacitor with two different voltages, for generating a signal to operate on-off of the semiconductor switch in accordance with a result of a comparison; a first charging circuit to charge the capacitor based on a voltage applied to the coil; and a discharging circuit to discharge the capacitor. The first charging circuit has a first resistor and at least one compensating circuit connected in parallel with the first resistor; and a resistor and a Zener diode are connected in series in the compensating circuit.

Abstract: An amplifier applies a self-adapting voltage to an output terminal. A bias circuit provides a greater bias current in a first external connection condition, in the absence of a pull-up resistance connected to the output terminal, than when such a pull-up resistance is present. The amplifier applies a different voltage to the output terminal in the absence of a pull-up resistance than when such a pull-up resistance is present. The circuit can be used in a portable device for receiving charging current from a battery charger through a connector having a D+ pin for connection to the battery charger and connected to the amplifier output terminal for battery charger detection. The portable device can meet the USB battery charger specification rev. 1.2.

Abstract: A device that includes at least one current consuming component. The device is characterized by including a compensation circuit adapted to compare between a voltage level at a sensing point within an integrated circuit and between a reference voltage derived from a voltage peak level at the sensing point; and to selectively increase the voltage at the sensing point in response to the comparison. A method for compensating for voltage drops in an integrated circuit, the method includes providing at least a first supply voltage to an integrated circuit; the method is characterized by including: comparing between a voltage level at a sensing point within an integrated circuit to a reference voltage derived from a voltage peak level at the sensing point; and selectively increasing the voltage at the sensing point in response to the comparison.

Abstract: An LCD controller includes a charge pump for generating a charge voltage responsive to an external voltage and a clock signal. The controller further includes an oscillator for generating the clock signal responsive to an oscillator control signal. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an associated LCD display. A loop control circuit within the LCD controller monitors an LCD driver voltage from the LCD driver voltage circuit and generates the oscillator control signal responsive thereto to enable and disable the oscillator.

Abstract: An apparatus and method for controlling power supplied to data generating circuits based on performance, such as time delay associated with generating data. The apparatus includes a plurality of data generating circuits configured to generate data at respective outputs in response to a first signal; a plurality of timing circuits configured to generate a plurality of second signals related to time delays between the first signal initiating the generation of the data and an appearance of the data at the respective outputs of the data generating circuits; a power supply circuit configured to generate a voltage for supplying power to the data generating circuits; a power controller configured to control the voltage generated by the power supply circuit based on the plurality of second signals; and a serial data transfer circuit configured to serial transfer the plurality of second signals from the respective timing circuits to the power controller.

Abstract: A semiconductor integrated circuit and an integrated circuit, each of which includes multiple regions containing at least one switchable region to switch between supplying power and blocking power individually; a power supply controller to control switching supplying power and blocking power in the switchable region that switches supplying power and blocking power individually; a power supply variable impedance circuit to change a power supply impedance of the semiconductor integrated circuit; and a power supply impedance controller to obtain the power supplying state of the region from the power supply controller, to cause the power supply variable impedance circuit to change the power supply impedance, based on a supply state of the power in the switchable region.

Abstract: A power supply for supplying power to a chipset includes a first voltage regulating circuit, which is configured to convert an applied power supply signal into a group of first supply voltages, and a second voltage regulating circuit, which is configured to convert the applied power supply signal into a group of second supply voltages. A control circuit is provided, which is configured to selectively enable the second voltage regulating circuit to generate the group of second supply voltages. An output discharge circuit is provided, which is configured to discharge an output stage of the first voltage regulating circuit in response to a transition of the first voltage regulating circuit from an active state to an inactive state. This transition of the first voltage regulating circuit from an active state to an inactive state can occur in response to a change in magnitude of the power supply signal.