Abstract: Systems, methods, and apparatus for power management are disclosed. A power management integrated circuit has a bus interface circuit configured to couple the power management integrated circuit to a shared communication bus, one or more regulator circuits configured to provide current to a managed device, and a controller. The controller is configured to determine that current consumption by the managed device exceeds a threshold level, generate an extended current level message to be transmitted over the shared communication bus to the managed device and transmit a time value with the extended current level message, the time value indicative of an elapsed time between generation of the extended current level message and start of transmission of the extended current level message.

Abstract: The present document relates to a level shifter circuit configured to transform an input voltage at an input of the level shifter circuit into an output voltage at an output of the level shifter circuit. The level shifter circuit may comprise a first switching element coupled between an output supply voltage and a positive output terminal, wherein a control terminal of the first switching element is coupled to a negative output terminal. The level shifter circuit may comprise a second switching element coupled between the output supply voltage and the negative output terminal, wherein a control terminal of the second switching element is coupled to the positive output terminal. The level shifter circuit may comprise a drive circuit configured to drive the control terminals of the first and the second switching element based on the input voltage at the input of the level shifter circuit.

Abstract: Voltage regulators generate voltage rails that power a central processing unit (CPU). The CPU communicates power management instructions to a power supply controller that drives the voltage regulators. The power supply controller sets a voltage level of a voltage rail generated by a voltage regulator in accordance with a power management instruction received from the CPU. The power supply controller enables the voltage regulator to operate in discontinuous conduction mode (DCM) independent of power state commands from the CPU.

Abstract: A semiconductor device may include a sudden power detection circuit and an operation circuit. The sudden power detection circuit may generate a power-off control signal in a sudden power-off state. The operation circuit may discharge a specific node based on the power-off control signal.

Abstract: An adjuster includes a power transfer circuit, a negative feedback circuit, a constant current source circuit and a control circuit. Two inputs of an error amplifier in the negative feedback circuit receive a reference voltage and a feedback voltage corresponding to an output signal of the adjuster respectively, and the error amplifier is configured to output a first voltage signal when the feedback voltage is less than the reference voltage, and output a second voltage signal when the feedback voltage is greater than the reference voltage, during the starting process of the adjuster. The control circuit is configured to control the negative feedback circuit to be turned off and the constant current source circuit to be turned on, and control the constant current source circuit to be turned off and the negative circuit to be turned on according to the second voltage signal.

Abstract: An apparatus is provided which comprises: a planar dielectric surface, two or more conductive leads on the surface, the conductive leads extending away from the substrate surface, two or more conductive traces on the surface between the conductive leads, the traces substantially parallel to each other, and a wire coupling a first end of a first conductive trace to an opposite end of an adjacent second conductive trace, the wire extending away from the surface. Other embodiments are also disclosed and claimed.

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

Abstract: In certain aspects, a system includes a voltage controller, wherein the voltage controller includes switches coupled between a voltage supply rail and an output of the voltage controller, each of the switches having a control input, and a control circuit coupled to the control inputs of the switches. The system also includes a timing circuit coupled to the control circuit, wherein the timing circuit includes a delay line, and flops, each of the flops having an input and an output, wherein the input of each of the flops is coupled to a respective node on the delay line, and the outputs of the flops are coupled to the control circuit.

Abstract: Embodiments described herein relate to an LDO circuit device and overcurrent protection circuit of an LDO circuit. An overcurrent protection circuit is added to an LDO circuit to process an output current signal of the LDO circuit. When the output current signal of the LDO circuit increases, a voltage of a gate drive signal of a power switch in the LDO circuit is increased through adjustment performed by the overcurrent protection circuit, thereby declining the current capability of the power switch in the LDO circuit and restricting an output current thereof from continuing to increase. After feedback regulation, the output current of the LDO finally reaches to a stable value.

Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

Abstract: A power supply device for eliminating the ringing effect includes a transformer, an output stage circuit, a power switch element, a pulse width modulation integrated circuit, and a control circuit. The transformer includes a main coil, a secondary coil, and an auxiliary coil. A leakage inductor is built in the transformer. The main coil receives an input voltage through the leakage inductor. The secondary coil generates an induced voltage. The output stage circuit generates an output voltage according to the induced voltage. A first parasitic capacitor is built in the power switch element. The control circuit includes an auxiliary inductor coupled to the auxiliary coil. The control circuit monitors the power switch element. If the power switch element is switched from an enable state into a disable state, the control circuit will couple the auxiliary inductor to the main coil and the leakage inductor of the transformer.

Abstract: A power control circuit is disclosed. The power control circuit includes a first receiving circuit, a second receiving circuit, a first power supply circuit and a second power supply circuit. The first receiving circuit is electrically connected to a charging circuit and a first port and configured to charge a power unit according to a first port voltage. The second receiving circuit is electrically connected to the charging circuit and a second port and configured to charge the power unit according to a second port voltage. The second receiving circuit is further configured to be disabled according to the first port voltage. The first power supply circuit is configured to supply power to the first port. The second power supply circuit is configured to supply power to the second port. Thus, the power control circuit transmits power or data through different ports.

Abstract: A reference voltage training circuit may include: a normal buffer configured to generate a first received signal by receiving one of differential signals based on the other; a calibration signal generation circuit configured to generate a second received signal by receiving the one of the differential signals according to a reference voltage, and generate reference voltage calibration signals by comparing the phase of the second received signal to the phase of the first received signal; and a reference voltage generation circuit configured to calibrate the level of the reference voltage according to the reference voltage calibration signals.

Abstract: A data transfer circuit and a memory device including the data transfer circuit are provided. The data transfer circuit includes a first regulator provided with an external voltage to output a first internal voltage; a second regulator configured in a same manner as the first regulator and provided with the external voltage to output a second internal voltage; an amplifier configured for amplifying noise between the first internal voltage and the second internal voltage to output an amplification voltage; and a plurality of peripheral circuits performing by being provided with the first internal voltage.

Abstract: The present disclosure provides a bandgap reference circuit which includes a basic reference module to generate a basic reference voltage containing a first linear temperature-coefficient (TC) voltage and a first nonlinear TC voltage when a terminal node in the basic reference module is grounded. The bandgap reference circuit further includes a compensation module with an output node coupled to the terminal node of the basic reference module. The compensation module generates a compensation voltage at the output node with a second linear TC term and a second nonlinear TC term by using a first set of current sources proportional to absolute temperate (PTAT) and a second set of current sources with TC of zero. And the bandgap reference circuit combines the basic reference voltage and the compensation voltage, cancelling all the linear and nonlinear terms, and thus create a composite reference voltage independent of temperature.

Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.

Abstract: Disclosed is a low dropout linear regulator and a voltage stabilizing method therefor in embodiments. The low dropout linear regulator includes: a drive circuit, generating a first control signal according to a voltage reference and a feedback voltage and generating an output current according to the first control signal, a load capacitor providing an output voltage according to the output current; a voltage feedback circuit, obtaining the feedback voltage according to the output voltage; a current feedback circuit, generating a second control signal according to the output current; a switch circuit, providing the voltage reference according to the second control signal. Among them, in a first phase of a startup process, the voltage reference is less than or equal to an initial value, and the current feedback circuit limits the output current according to the second control signal; in a second phase of the startup process, the switch circuit switches a voltage value of the voltage reference to a target value.

Abstract: A method includes generating a voltage difference indication between a previous voltage on the bit line of a DRAM and a current voltage on a bit line. In an embodiment, the previous voltage corresponds to a logic 1 voltage or a logic 0 voltage stored in a previous DRAM cell of a column of DRAM cells, the current voltage corresponds to a logic 1 voltage or a logic 0 voltage being stored in the current DRAM cell of the column of DRAM cells, and the bit line is coupled to the column of DRAM cells. When the current DRAM cell is in a read mode, the method further includes the following steps: Generating a read voltage reference based on the voltage difference indication; Generating a read output voltage based on the read voltage reference; Supplying the read output voltage on to the bit line; and Outputting a representation of the read output voltage.

Abstract: In at least one embodiment, an interface electronic circuit for a capacitive acoustic transducer having a sensing capacitor is provided. The interface electronic circuit includes an amplifier, a voltage regulator, a common-mode control circuit, and a reference generator. The amplifier has an input coupled to an electrode of the sensing capacitor. The voltage regulator is configured to receive a regulator reference voltage, generate a regulated voltage based on the regulator reference voltage, and supply the regulated voltage to a supply input of the amplifier. The common-mode control circuit controls a common-mode voltage present on the input of the amplifier based on a common-mode reference voltage. The reference generator receives a supply voltage and generates the regulator reference voltage and the common-mode reference voltage with respective values that are variable as a function of the supply voltage.

Abstract: A driver circuitry includes a voltage application circuitry, a current detection circuitry, and a control circuitry. The voltage application circuitry is connected to a drive terminal of a transistor, and controls a voltage of an input signal and applies to the drive terminal. The current detection circuitry is connected to an output terminal of the transistor, and detects that a current output from the transistor becomes a size of a predetermined current or more. The control circuitry is connected to the current detection circuitry, and controls the voltage application circuitry based on the voltage of the input signal to output a voltage between the drive terminal and the output terminal at the timing when the current detection circuitry detects the current of the predetermined current or more.

Abstract: Embodiments of the present invention disclose a low dropout regulator and a phase-locked loop. The low dropout regulator includes: a reference voltage source, an error amplifier coupled to the reference voltage source, a regulating circuit, a load coupled to the regulating circuit, a first compensation circuit, and a second compensation circuit. The regulating circuit produces a regulating current under control of a control voltage from the error amplifier. The first compensation circuit is coupled between the error amplifier and the regulating circuit. The second compensation circuit is coupled between an input terminal and an output terminal of the regulating circuit.

Abstract: A voltage regulator includes an error amplifier which receives a feedback voltage and a reference voltage, an amplifier circuit which receives an output voltage of the error amplifier and controls a gate of an output transistor by a first output voltage, and a non-regulation detection circuit which detects a non-regulation state of the voltage regulator based on a second output voltage of the amplifier circuit. The amplifier circuit includes a first transistor receiving the output voltage of the error amplifier at a gate of the first transistor, and a second transistor connected to a drain of the first transistor, and provides the second output voltage based on a gate-source voltage of the second transistor.

Abstract: An input circuit according to an embodiment includes an input terminal, a power terminal, an internal circuit, an input section, a power supply section, and a first circuit. The input section includes first and resistive parts, and a first transistor. The first resistive part is connected to the input terminal. The second resistive part is connected to the first resistive part. The gate of the first transistor is connected to the first resistive part. The first circuit includes a fifth resistive part and a third transistor. The fifth resistive part is connected to the second resistive part and a grounding line. The gate and one end of the third transistor are connected to the second resistive part. The other end of the third transistor is connected to the grounding line.

Abstract: Drones convertible into personal computers are disclosed, A disclosed unmanned aerial vehicle (UAV) includes a body and rotors carried by the body. The rotors move relative to the body from a first position when the UAV is in a drone mode to a second position when the UAV is in a computer mode.

Abstract: An apparatus includes a circuit that has a normal mode of operation and a low-power mode of operation. The circuit consumes more power in the normal mode of operation than in the low-power mode of operation. The apparatus further includes a power-supply circuit. The power-supply circuit provides a normal supply voltage to the circuit in the normal mode of operation. The power-supply circuit includes a non-linear circuit to provide a compressed supply voltage to the circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.

Abstract: A voltage compensation circuit and a voltage compensation method are provided. The voltage compensation circuit detects the load current provided by a power supply, generates a load voltage according to the load current, and compares the load voltage with at least one reference voltage to generate a switch control signal. The voltage compensation circuit further drives the at least one switch according to the switch control signal, provides a compensation resistance value according to the at least one switch that is turned on, and provides a compensation voltage to the power supply, so that the power supply provides a precise output voltage.

Abstract: The disclosure relates to an isolation and voltage regulation circuit for an electrochemical power source, the circuit comprising: an input terminal (202) for coupling to the power source and receiving an input voltage (Vin) from the power source; an output terminal (204) for coupling to a load; a diode circuit (206) connected between the input terminal and the output terminal; a diode controller (208) configured to control electrical conduction through the diode circuit between the input terminal and the output terminal, the diode controller having a first controller input (210) coupled to the output terminal and a second controller input (212); and a reference controller (220) configured to set a voltage at the second controller input (212) in accordance with a comparison between the input voltage (Vin) and a reference voltage (Vref).

Abstract: A system includes a first circuit, a second circuit and a regulator. The first circuit is configured to operate at a first operating voltage, wherein the first operating voltage drops by a first voltage level while the first circuit operates. The second circuit is coupled with the first circuit at a tap, and configured to operate at a second operating voltage. The regulator is configured to provide a supply voltage to the first circuit and the second circuit via the tap. The regulator is also configured to raise the supply voltage in response to the first voltage level.

Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

Abstract: A circuit includes an amplifier having a first power terminal configured to be coupled to a supply voltage and a second power terminal configured to be coupled to a reference potential. The circuit further includes a first impedance element coupled between a first input terminal of the amplifier and a first output terminal of the amplifier. The circuit additionally includes a second impedance element coupled between the first input terminal and the reference potential. The amplifier is configured to output a first voltage at a second output terminal of the amplifier in response to the supply voltage being greater than an output voltage at the first output terminal of the amplifier. The amplifier is further configured to output a second voltage at the second output terminal of the amplifier in response to the supply voltage being less than the output voltage at the first output terminal of the amplifier.

Abstract: A current mirror arrangement for duplex bidirectional communication between two circuit units may include in each circuit unit two identical transistors with their bases (36, 37) connected together and their bases and their collectors connected to each other respectively. Further, each of the connections between the bases and the collectors may be formed via a MOSFET. The MOSFETs of both circuit units may be connected together. More specifically, the MOSFETs' parasitic diodes of each circuit unit may be arranged in opposite directions with respect to the current system. The pair of MOSFETs in a first of the two circuit units may comprise n-channel enhancement-mode MOSFETs, and the pair of MOSFETs in a second of the two circuit units may comprise p-channel enhancement-mode MOSFETs.

Abstract: A bias circuit for power amplifiers is disclosed. A power amplifier bias circuit can include an emitter follower device and an emitter follower mirror device coupled to form a mirror configuration. The emitter follower device can be configured to provide a bias signal for a power amplifier at an output port. The power amplifier bias circuit can include a reference device configured to mirror an amplifying transistor of an amplifying device of the power amplifier. The emitter follower mirror device can be configured to provide a mirror bias signal to the reference device. A node between the emitter follower device and the emitter follower mirror device can have a voltage of approximately twice a base-emitter voltage (2Vbe) of the amplifying transistor.

Abstract: A device includes a circuit cell, a voltage regulator, a first switching unit, a second switching unit, and a third switching unit. The voltage regulator is configured to output a write voltage. The first switching unit is configured to generate, in response to a control voltage, a current represented by an auxiliary signal. The second switching unit is configured to receive the auxiliary signal, and to turn on to transmit the auxiliary signal to the circuit cell. The third switching unit is configured to receive the write voltage, and to turn on to transmit the write voltage to the circuit cell.

Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

Abstract: A semiconductor device, a semiconductor system, and a control method of a semiconductor device are capable of accurately monitoring the lowest operating voltage of a circuit to be monitored. According to one embodiment, a monitor unit of a semiconductor system includes a voltage monitor that is driven by a second power supply voltage different from a first power supply voltage supplied to an internal circuit that is a circuit to be monitored and monitors the first power supply voltage, and a delay monitor that is driven by the first power supply voltage and monitors the signal propagation period of time of a critical path in the internal circuit.

Abstract: A semiconductor circuit in the disclosure includes a first circuit that is able to generate, on the basis of a voltage in a first node, an inverted voltage of the voltage and to apply the inverted voltage to a second node; a second circuit that is able to generate, on the basis of a voltage in the second node, an inverted voltage of the voltage and to apply the inverted voltage to the first node; a first transistor that couples the first node to a third node; a second transistor that supplies a first direct-current voltage to the third node; a third transistor including a drain or a source to be coupled to the third node and including a gate coupled to the first node or the second node; and a first storage element that is coupled to the third node, and is able to take a first resistance state or a second resistance state. The first circuit and the second circuit are configured to cause the voltage in the first node to easily become a predetermined initial voltage after application of power.

Abstract: Apparatus and associated methods relate to a dynamic quantizer circuit including a tail voltage supply magnitude (VTAIL) distinct from a general supply voltage (Avcc/Avss), VTAIL providing power to a tail clock buffer to generate tail clock signals to tail devices. In an illustrative example, a compensation processor may control a regulator producing a determined VTAIL value in response to one or more parametric signals, for example, the Avcc voltage value, a circuit temperature and a transistor speed process (TSP). The TSP signal may be determined, for example, by process-dependent circuit devices. The compensation processor may be, for example, configured to lower VTAIL in response to detecting a worst-case RMS noise corner, or to raise VTAIL in response to detecting a worst-case clock-to-q corner. Various adjustable VTAILs may be configured to continuously optimize RMS noise, offset and speed performance with low power consumption in various quantizers over process, voltage and/or temperature.

Abstract: A voltage regulation method, a controller, and a chip are provided. In the method, a controller receives a digital first status representation value sent by a sensor; the controller determines, according to the first status representation value and at least one of a second status representation value or a first expected value, whether to regulate the supply voltage of the load, where the second status representation value represents a node voltage that is at a previous moment and that is of the detection point of the load, and the first expected value represents an expected value of a node voltage of the detection point; and when determining to regulate the supply voltage of the load, the controller sends a digital control signal to a power gating array, to control the power gating array to regulate the supply voltage.

Abstract: The present application provides a capacitance sensing circuit, comprising an integrating circuit, comprising an integrating input terminal, coupled to the touch capacitance, wherein the integrating input terminal receives an input voltage; and an integrating output terminal, configured to output an output voltage; a comparator; a positive digital-to-analog (DA) converting unit; a negative DA converting unit; a control circuit, configured to control the positive DA converting unit and the negative DA converting unit; and a logic circuit, configured to output an output code, wherein the output code is related to a capacitance of the touch capacitance.

Abstract: Provided is a voltage regulator capable of stably suppressing overshoot. The voltage regulator includes a non-regulated state detection circuit for detecting a non-regulated state, and an overshoot suppression circuit. The overshoot suppression circuit is configured to operate when the non-regulated state detection circuit detects the non-regulated state.

Abstract: An apparatus includes a circuit that has a normal mode of operation and a low-power mode of operation. The circuit consumes more power in the normal mode of operation than in the low-power mode of operation. The apparatus further includes a power-supply circuit. The power-supply circuit provides a normal supply voltage to the circuit in the normal mode of operation. The power-supply circuit includes a non-linear circuit to provide a compressed supply voltage to the circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.

Abstract: In some examples, a device includes a power switch, a sensing switch configured to conduct an electrical current based on an electrical current conducted by the power switch. In some examples, the device also includes trimming circuitry configured to generate a monitored electrical current based on an aspect ratio of the trimming circuitry and based on the electrical current conducted by the sensing switch, wherein the aspect ratio of the trimming circuitry is adjustable.

Abstract: A semiconductor circuit includes a differential amplifier having a first positive terminal, a second positive terminal, a first negative terminal, a second negative terminal, and an output terminal. The output voltage is at a level that corresponds to a voltage level obtained by subtracting a voltage of the first negative terminal and the second negative terminal from a voltage sum of the first positive terminal and the second positive terminal. A first diode has a first anode connected to one of the first positive or the first negative terminal. A second diode has a second anode connected to the other of the first negative and first positive terminal. A predetermined reference voltage is applied to the second positive terminal. And a voltage corresponding to the output voltage of the differential amplifier is fed back to the second negative terminal.

Abstract: Described herein are technologies related to an implementation of a system to measure and compensate non-linearity (e.g., echo cancellation) in a transceiver circuitry of a device. Particularly, the echo cancellation utilizes reduced number of components for power savings, and further increases efficiency of signal or data packet transmissions in the device. An echo signal is determined by sampling a power amplifier output signal. The output signal is split into signals with different delays. Down conversion and digital interpolation of the signal with the shortest delay is performed. An echo cancellation signal is calculated based on the output signal as received as an input signal to a receive chain. The calculated signal is subtracted from a received echo signal to generate an echo free signal.

Abstract: A gate driving circuit is disclosed. The output circuit is connected with the input circuit and the pulling circuit at a first node, responding to scanning driving signal of previous stage to set the pulling circuit in a first status, using a first reference voltage level to set the first node at a first voltage, and held. The output circuit outputs scanning driving signal of current stage according to a first clock signal. The stabilizing circuit is connected with the pulling circuit at a second node, using the first reference voltage level to set the second node at the first voltage, and held. The pulling control circuit responds to a second clock signal to set the pulling circuit in a second status, using a second reference voltage level to pull voltages of the first and second nodes and to hold the voltages. Accordingly, a current leakage can be reduced.

Abstract: In a pressure detecting apparatus, a pressure sensor includes a piezoelectric sheet that generates a piezoelectric signal according to a load that is applied. A touch detecting unit detects contact with the pressure sensor. An acquirer acquires a piezoelectric output based on the piezoelectric signal. A rate-of-change calculator calculates a rate of change with respect to time of the piezoelectric output acquired within an arbitrary time range before a touch detection time when the touch detecting unit detects contact with the pressure sensor. An applied pressure calculator calculates applied pressure by correcting the piezoelectric output acquired after an end time of the time range used in the calculation of the rate of change using the rate of change. The apparatus enables precise measurement of applied pressure in a pressure sensor.

Abstract: Systems and methods for conditioning a power rail (e.g., reducing voltage droops and/or voltage overshoots on the power rail) are described herein. In one embodiment, a power circuit comprises a capacitor coupled to a high-voltage rail, and a droop slope limiter (DSL) coupled between the high-voltage rail and a power rail. The DSL is configured to detect a downward voltage slope on the power rail, and to control current flow from the high-voltage rail to the power rail through the DSL based on the detected downward voltage slope.

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.

Abstract: A physical quantity detecting sensor includes a physical quantity detecting sensor element and an IC connected to the physical quantity detecting sensor element. The IC includes: a logic circuit; an analog circuit; a first regulator that supplies a logic power supply voltage generated based on a power supply voltage to the logic circuit; a second regulator that is switched to enable or disable and supplies an analog power supply voltage, which is generated based on the power supply voltage when the second regulator is set to enable, to the analog circuit; and a switch for supplying the logic power supply voltage to the analog circuit when the second regulator is set to disable.

Abstract: A system is based on an IC. A first component of the IC generates a signal that clocks the IC at a target operating frequency. A period corresponding to the target clock frequency exceeds a duration of a longest critical path associated with the IC. The first component and synchronous logic of the IC clocked therewith, each functions with the core supply voltage, which may be supplied to each via the same power supply rail. A second IC component detects errors that relate to an operation of the IC at the target clock frequency and determines a level for adjusting the core supply voltage. The Vdd adjustment ameliorates the frequency error. The voltage determination uses closed loop dynamic voltage and frequency scaling.