Abstract: An assembly includes a three-level voltage converter and a second voltage converter. The three-level voltage converter is electrically coupled to a battery to convert a battery supply voltage to an intermediate voltage. The second voltage converter is electrically coupled to the three-level voltage converter to convert the intermediate voltage to a processor-supply voltage to operate a processor. At least the second voltage converter and the processor are mounted on a processor-package substrate. The three-level voltage converter can be mounted on the processor-package substrate or on a circuit board on which the processor-package substrate is mounted.

Abstract: An electronic device and a method of controlling an electronic device are provided. The electronic device includes a first transistor having a first resistor, second resistor, first transistor, and second transistor. The second resistor is connected to the first resistor. The first transistor is connected to the first resistor in parallel and has a first bulk. The second transistor is connected to the second resistor in parallel and has a second bulk. The first bulk of the first transistor receives a first voltage and the first bulk of the second transistor receives a second voltage. The first voltage and the second voltage are different.

Abstract: A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises a memory array region comprising a stack structure comprising levels of conductive structures vertically alternating with levels of insulative structures, and staircase structures at lateral ends of the stack structure.

Abstract: A system-on-chip according to an embodiment includes a core including a header switch circuit configured to transmit a power supply voltage applied to a first power rail as a supply voltage to a second power rail and a logic circuit configured to operate based on the supply voltage from the second power rail, and a low-dropout (LDO) regulator configured to regulate a magnitude of first current output to the second power rail based on a change in the supply voltage, wherein the LDO regulator is further configured to control on/off of a plurality of first header switches included in the header switch circuit based on an amount of the change in the supply voltage.

Abstract: A semiconductor device comprising an integrated circuit is provided. The integrated circuit comprises a first element configured to execute a predetermined operation, a second element, and a controller configured to perform control of setting the second element in a non-operation state in a case in which performance deterioration of the first element is a first degree and operating the second element in a case in which the performance deterioration of the first element is a second degree larger than the first degree.

Abstract: A hybrid charge pump is disclosed that employs novel arrangements of depletion-mode n-channel semiconductor devices and enhancement-mode p-channel semiconductor devices that eliminate or otherwise substantially reduce voltage drops that would otherwise occur across semiconductor device arrangements in existing charge pumps. As a result, the hybrid charge pump disclosed herein achieves the same output voltages as conventional charge pumps while requiring a reduced physical die area. Additionally, a hybrid charge pump arrangement disclosed herein employs a novel clocking scheme that reduces or eliminates reverse currents in the hybrid charge pump arrangement.

Abstract: A non-volatile memory device comprises memory cells, a first regulator, a second regulator, a first switch, a second switch and capacitor coupling switches. The first regulator comprises a first capacitor, and generates a first voltage at a first node connected to a first subset of the memory cells, to provide the first voltage to the first subset. The second regulator comprises a second capacitor, and generates a second voltage at a second node. The first switch selectively couples the second node to a second subset of the memory cells, to provide the second voltage to the second subset. The second switch selectively couples the first node to the second subset to also provide the first voltage to the second subset. The capacitor coupling switches selectively couple the second capacitor in parallel to the first capacitor when the first switch is deactivated, and the second switch is activated.

Abstract: The present invention relates to a new type of current driving circuit, which has high linearity during low current driving, comprising: a voltage-current conversion unit for converting an input voltage into a current; a digital analog converter (DAC) connected to an output terminal of the voltage-current conversion unit and for generating and outputting a voltage corresponding to an applied digital code; a field effect transistor having a first electrode connected to a load and a second electrode connected to a node connected to a resistor, and for allowing a current to flow to the load in response to a voltage applied to a gate; an amplifier for receiving the voltage output from the digital analog converter and a voltage generated by the resistor, generating a voltage for controlling such that a current flows from the field effect transistor, and applying same to the gate; a current supply source for supplying to the first electrode a current required for operating the field effect transistor in a saturatio

Abstract: An adaptive current mirror circuit for current shaping with temperature is disclosed. The adaptive current mirror includes a current generator circuit configured to receive and input current and generate an output current using the input current and an overdrive voltage. The adaptive current mirror further includes a compensation circuit configured to adjust a value of the overdrive voltage based on temperature.

Abstract: A method and apparatus for managing processor functionality includes receiving, by the processor, data relating to one or more environmental conditions. The processor compares the data to pre-existing parameters to determine whether or not the environmental conditions are within the pre-existing parameters for normal operation. If the data are within the pre-existing parameters for normal operation, the processor is operated in a normal operation mode. If the data are outside the pre-existing parameters for normal operation, the processor operates in a second operation mode which is dynamically determined and calibrated during power-on, boot and operation.

Abstract: An electric power converter includes a plurality of switch pairs respectively corresponding to a plurality of phases and each consisting of an upper-arm switch and a lower-arm switch. Each of the lower-arm switches of the switch pairs has a first terminal, a second terminal and a gate. The electric power converter further includes: a voltage generation circuit having its positive electrode side connected to the second terminal of only one of the lower-arm switches of the switch pairs; a negative-electrode-side electrical path connected to a negative electrode side of the voltage generation circuit; and at least one capacitor having a first end connected to the second terminal of one of the remainder of the lower-arm switches of the switch pairs, which is not connected with the voltage generation circuit, and a second end connected to the negative-electrode-side electrical path.

Abstract: A system contains a machine learning application specific integrated circuit (ASIC) and a power supply unit. The power supply unit and the ASIC are configured to be in data communication through dedicated pins on the ASIC and the power supply unit. The power supply unit detects a present power consumption of the ASIC. Upon determining that a threshold condition has been met, the power supply unit, responsive to the condition sends a digital signal to the ASIC. The ASIC contains a synchronizer which synchronizes the digital signal to be consistent with the ASICs internal clock frequency. A chip manager the synchronized signal and other signals to generate a throttling mask. The throttling mask is sent to a sequencer of the ASIC, which then limits the instruction flow into the processing units of the ASIC based on the mask. This in turn limits the power being consumed by the ASIC.

Abstract: Provided a voltage generating circuits including assist circuits and operating methods thereof. The voltage generating circuit which includes an assist circuit that generates an assist signal indicating an enable mode or a disable mode. When a first power supply voltage is lower than an assist reference voltage, the assist signal indicates the enable mode, and a compensation circuit generates a compensation signal based on the first power supply voltage. An internal voltage converter generates a regulated voltage based on the first power supply voltage, and a charge pump circuit generates a pump voltage based on the regulated voltage. The compensation signal compensates for the regulated voltage.

Abstract: A voltage regulation system includes a voltage regulator configured to receive a first reference voltage and output a regulated voltage; a bias voltage generator comprising a diode-connect transistor configured to receive a bias current and output a reference gate voltage; and a plurality of switch-load circuits, each of said plurality of switch-load circuits comprising a common-drain transistor configured to receive power from the regulated voltage and control from the reference gate voltage via a switch controlled by a logical signal and output a supply voltage to load with a decoupling capacitor, wherein a size of the common-drain transistor is scaled from a size of the diode-connect transistor in accordance with a ratio between a current of the load and the bias current.

Abstract: In an embodiment, a method for operating an ACF converter includes: turning on a low-side transistor that is coupled between a primary winding of a transformer and a reference terminal to cause a forward current to enter the primary winding, turning off the low-side transistor; after turning off the low-side transistor, turning on a high-side transistor that is coupled between the primary winding and a clamp capacitor to cause a reverse current to flow through the primary winding; and after turning on the high-side transistor, when an overcurrent of the reverse current is not detected, keeping the high-side transistor on for a first period of time, and turning off the high-side transistor after the first period of time, and when the overcurrent of the reverse current is detected, turning off the high-side transistor without keeping the high-side transistor on for the first period of time.

Abstract: A circuit includes an output node and an amplifier and first and second branches coupled between power supply and reference nodes. The first branch includes a first switching device coupled between a first amplifier input and the reference node, the second branch includes a second switching device coupled between the output node and a second amplifier input, and a third switching device is coupled between the power supply and output nodes. Responsive to a first voltage level on the power supply node, each of the first and second switching devices is switched off and the third switching device is switched on, and responsive to a second voltage level on the power supply node greater than the first voltage level, each of the first and second switching devices is switched on and the third switching device is switched off.

Abstract: A method and apparatuses for power regulation using an extended current limit are disclosed. The power regulator detects an occurrence of an output current of the regulator exceeding a first current limit, triggers an extended current limit timer based on the detected occurrence, regulates the output current according to a second current limit higher than the first current limit based on a duration of the extended current limit timer, and regulates the output current according to the first current limit based on an expiration of the duration of the extended current limit timer.

Abstract: An active phased array antenna (APAA) device includes antenna elements, active circuits, switches, and a control circuit. The antenna elements transmit and receive radio waves. The active circuits are connected to the antenna elements and start an operation upon supply of power distributed from a power supply circuit and transmit and receive signals via the antenna elements to which the active circuits are connected. The switches are connected to the active circuits, and start, upon being closed, supply of power to the active circuits to which the switches are connected, and stop, upon being opened, the supply of power to the active circuits to which the switches are connected. The control circuit transmits to the switches switching signals to turn the switches on and off to control starting and stopping of the supply of power to the active circuits. The control circuit sets timing differences in execution timings of executing the start of the stop of supply of power to the active circuits.

Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

Abstract: A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.

Abstract: In an embodiment, a method for operating an ACF converter includes: turning on a low-side transistor that is coupled between a primary winding of a transformer and a reference terminal to cause a forward current to enter the primary winding, turning off the low-side transistor; after turning off the low-side transistor, turning on a high-side transistor that is coupled between the primary winding and a clamp capacitor to cause a reverse current to flow through the primary winding; and after turning on the high-side transistor, when an overcurrent of the reverse current is not detected, keeping the high-side transistor on for a first period of time, and turning off the high-side transistor after the first period of time, and when the overcurrent of the reverse current is detected, turning off the high-side transistor without keeping the high-side transistor on for the first period of time.

Abstract: In one embodiment, an apparatus includes: an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; a loop circuit coupled to the amplifier, where the loop circuit is to receive the comparison signal and provide a regulated voltage to the amplifier as the feedback voltage in a first mode of operation, and in a second mode of operation to provide a predetermined feedback ratio point to the amplifier as the feedback voltage; and an output device coupled to the amplifier. The output device may be configured to receive a supply voltage and the comparison signal and output the regulated voltage at an output node based at least in part on the comparison signal.

Abstract: In an embodiment a method for testing a digital electronic circuit includes coupling an external test equipment to a digital electronic circuit in order to apply an external voltage signal to the digital electronic circuit when an automatic test pattern generation (ATPG) procedure with a given test pattern is performed, wherein a value of the external voltage signal is controlled by the external test equipment and measuring, at the external test equipment, the digital supply voltage at an output of the voltage regulator and at an input of the internal digital circuitry, wherein the external voltage signal is applied to the differential inputs of the op-amp voltage regulator through an adaptation circuit to obtain determined values of the digital supply voltage.

Abstract: A drive-sense circuit coupled to a variable impedance load. The drive-sense circuit includes a voltage reference circuit operable to generate a voltage reference signal. The drive-sense circuit further includes a regulated current source circuit operable to generate a regulated current signal based on an analog regulation signal, where the regulated current signal is provided on a line to the variable impedance load to keep a load voltage on the line substantially matching the voltage reference signal, and where an impedance of the variable impedance load affects the regulated current signal. The drive-sense circuit further includes a current loop correction circuit operable to generate a comparison signal based on the voltage reference signal and the load voltage, where the comparison signal represents the impedance, and where the analog regulation signal is representative of the comparison signal.

Abstract: A power down detection circuit that may detect a supply voltage decrease more accurately is provided. The power down detection circuit includes a BGR circuit generating a reference voltage VREF, a resistance division circuit generating a first internal voltage VCC_DIV1 and a second internal voltage VCC_DIV2 based on a supply voltage VCC, a first comparator outputting a reset signal PDDRST when detecting VCC_DIV1<VREF, a second comparator outputting a switching signal SEL when detecting VCC_DIV2<VREF, a charging pump circuit generating a boosted voltage VXX based on the supply voltage VCC, and a switching circuit switching an operating voltage supplied to the BGR circuit to the supply voltage VCC or the boosted voltage VXX based on the switching signal SEL.

Abstract: Methods, systems, and devices for compensating for kickback noise are described. A regulator may include an input circuit, a bias circuit, and an enable circuit. The regulator may be configured so that the enable circuit is positioned between the input circuit and the bias circuit. A balance resistor may be included in a path between an input of the regulator and a gate of a bias transistor included in the bias transistor. A size of the balance resistor may be based on an amount of charge drawn by the bias transistor during an activation event. Dimensions of the bias transistor may be modified based on an amount of charge drawn by the bias transistor during an activation event.

Abstract: The present disclosure provides a system and method for soft start scheme to control inrush current for VCONN in USB-C interface. The system includes: a serial shift register having flip-flops and adapted to obtain clock with programmable clock divider, frequency of clock changes dynamically by programming programmable clock divider; a resistor DAC unit configured to increment voltage in step-wise manner; a pass gate switch comprising NMOS gate switch and a PMOS gate switch connected in parallel and operatively coupled to the resistor DAC unit and configured to control an input voltage to a VCONN charge pump, said input voltage being in incremental steps such that the VCONN charge pump pumps an output voltage; and a VCONN switch gate operatively coupled to the VCONN charge pump and configured to supply the output voltage in controlled, incremental steps, such that the output voltage is ramped slowly to control the inrush current.

Abstract: An integrated circuit for a power supply circuit that generates an output voltage from an input voltage and includes an inductor and a transistor, the integrated circuit configured to switch the transistor to control a current of the inductor. The integrated circuit includes a first terminal that receives a power supply voltage, a second terminal that receives a voltage corresponding to an operation state of the integrated circuit, a storage circuit, a switching circuit that switches an operation mode of the integrated circuit based on voltage levels at the first and second terminals, the operation mode including a write mode, a test mode and a normal mode, a memory control circuit that writes setting information into the storage circuit, when the integrated circuit operates in the write mode, and a setting target circuit that operates based on the setting information stored in the storage circuit, when the integrated circuit operates in the test mode.

Abstract: A dropout detection circuit for an LDO voltage regulator is disclosed. An LDO voltage regulator includes a power transistor having a drain terminal coupled to an output voltage node and a gate terminal coupled to an output of an error amplifier. A source terminal of the power transistor is coupled to an input voltage node. The circuit further includes a detection circuit having a first input coupled to the gate terminal and a second input coupled to the drain terminal. The detection circuit is configured to generate an indication responsive to detecting that the LDO voltage regulator has entered operation below a minimum dropout.

Abstract: Systems, methods, and apparatus for power management are disclosed. A power management integrated circuit has a bus interface circuit configured to couple the power management integrated circuit to a shared communication bus, one or more regulator circuits configured to provide current to a managed device, and a controller. The controller is configured to determine that current consumption by the managed device exceeds a threshold level, generate an extended current level message to be transmitted over the shared communication bus to the managed device and transmit a time value with the extended current level message, the time value indicative of an elapsed time between generation of the extended current level message and start of transmission of the extended current level message.

Abstract: The present document relates to a level shifter circuit configured to transform an input voltage at an input of the level shifter circuit into an output voltage at an output of the level shifter circuit. The level shifter circuit may comprise a first switching element coupled between an output supply voltage and a positive output terminal, wherein a control terminal of the first switching element is coupled to a negative output terminal. The level shifter circuit may comprise a second switching element coupled between the output supply voltage and the negative output terminal, wherein a control terminal of the second switching element is coupled to the positive output terminal. The level shifter circuit may comprise a drive circuit configured to drive the control terminals of the first and the second switching element based on the input voltage at the input of the level shifter circuit.

Abstract: Voltage regulators generate voltage rails that power a central processing unit (CPU). The CPU communicates power management instructions to a power supply controller that drives the voltage regulators. The power supply controller sets a voltage level of a voltage rail generated by a voltage regulator in accordance with a power management instruction received from the CPU. The power supply controller enables the voltage regulator to operate in discontinuous conduction mode (DCM) independent of power state commands from the CPU.

Abstract: An adjuster includes a power transfer circuit, a negative feedback circuit, a constant current source circuit and a control circuit. Two inputs of an error amplifier in the negative feedback circuit receive a reference voltage and a feedback voltage corresponding to an output signal of the adjuster respectively, and the error amplifier is configured to output a first voltage signal when the feedback voltage is less than the reference voltage, and output a second voltage signal when the feedback voltage is greater than the reference voltage, during the starting process of the adjuster. The control circuit is configured to control the negative feedback circuit to be turned off and the constant current source circuit to be turned on, and control the constant current source circuit to be turned off and the negative circuit to be turned on according to the second voltage signal.

Abstract: A semiconductor device may include a sudden power detection circuit and an operation circuit. The sudden power detection circuit may generate a power-off control signal in a sudden power-off state. The operation circuit may discharge a specific node based on the power-off control signal.

Abstract: An apparatus is provided which comprises: a planar dielectric surface, two or more conductive leads on the surface, the conductive leads extending away from the substrate surface, two or more conductive traces on the surface between the conductive leads, the traces substantially parallel to each other, and a wire coupling a first end of a first conductive trace to an opposite end of an adjacent second conductive trace, the wire extending away from the surface. Other embodiments are also disclosed and claimed.

Abstract: In certain aspects, a system includes a voltage controller, wherein the voltage controller includes switches coupled between a voltage supply rail and an output of the voltage controller, each of the switches having a control input, and a control circuit coupled to the control inputs of the switches. The system also includes a timing circuit coupled to the control circuit, wherein the timing circuit includes a delay line, and flops, each of the flops having an input and an output, wherein the input of each of the flops is coupled to a respective node on the delay line, and the outputs of the flops are coupled to the control circuit.

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

Abstract: Embodiments described herein relate to an LDO circuit device and overcurrent protection circuit of an LDO circuit. An overcurrent protection circuit is added to an LDO circuit to process an output current signal of the LDO circuit. When the output current signal of the LDO circuit increases, a voltage of a gate drive signal of a power switch in the LDO circuit is increased through adjustment performed by the overcurrent protection circuit, thereby declining the current capability of the power switch in the LDO circuit and restricting an output current thereof from continuing to increase. After feedback regulation, the output current of the LDO finally reaches to a stable value.

Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

Abstract: A power supply device for eliminating the ringing effect includes a transformer, an output stage circuit, a power switch element, a pulse width modulation integrated circuit, and a control circuit. The transformer includes a main coil, a secondary coil, and an auxiliary coil. A leakage inductor is built in the transformer. The main coil receives an input voltage through the leakage inductor. The secondary coil generates an induced voltage. The output stage circuit generates an output voltage according to the induced voltage. A first parasitic capacitor is built in the power switch element. The control circuit includes an auxiliary inductor coupled to the auxiliary coil. The control circuit monitors the power switch element. If the power switch element is switched from an enable state into a disable state, the control circuit will couple the auxiliary inductor to the main coil and the leakage inductor of the transformer.

Abstract: A power control circuit is disclosed. The power control circuit includes a first receiving circuit, a second receiving circuit, a first power supply circuit and a second power supply circuit. The first receiving circuit is electrically connected to a charging circuit and a first port and configured to charge a power unit according to a first port voltage. The second receiving circuit is electrically connected to the charging circuit and a second port and configured to charge the power unit according to a second port voltage. The second receiving circuit is further configured to be disabled according to the first port voltage. The first power supply circuit is configured to supply power to the first port. The second power supply circuit is configured to supply power to the second port. Thus, the power control circuit transmits power or data through different ports.

Abstract: A reference voltage training circuit may include: a normal buffer configured to generate a first received signal by receiving one of differential signals based on the other; a calibration signal generation circuit configured to generate a second received signal by receiving the one of the differential signals according to a reference voltage, and generate reference voltage calibration signals by comparing the phase of the second received signal to the phase of the first received signal; and a reference voltage generation circuit configured to calibrate the level of the reference voltage according to the reference voltage calibration signals.

Abstract: A data transfer circuit and a memory device including the data transfer circuit are provided. The data transfer circuit includes a first regulator provided with an external voltage to output a first internal voltage; a second regulator configured in a same manner as the first regulator and provided with the external voltage to output a second internal voltage; an amplifier configured for amplifying noise between the first internal voltage and the second internal voltage to output an amplification voltage; and a plurality of peripheral circuits performing by being provided with the first internal voltage.

Abstract: The present disclosure provides a bandgap reference circuit which includes a basic reference module to generate a basic reference voltage containing a first linear temperature-coefficient (TC) voltage and a first nonlinear TC voltage when a terminal node in the basic reference module is grounded. The bandgap reference circuit further includes a compensation module with an output node coupled to the terminal node of the basic reference module. The compensation module generates a compensation voltage at the output node with a second linear TC term and a second nonlinear TC term by using a first set of current sources proportional to absolute temperate (PTAT) and a second set of current sources with TC of zero. And the bandgap reference circuit combines the basic reference voltage and the compensation voltage, cancelling all the linear and nonlinear terms, and thus create a composite reference voltage independent of temperature.

Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.

Abstract: Disclosed is a low dropout linear regulator and a voltage stabilizing method therefor in embodiments. The low dropout linear regulator includes: a drive circuit, generating a first control signal according to a voltage reference and a feedback voltage and generating an output current according to the first control signal, a load capacitor providing an output voltage according to the output current; a voltage feedback circuit, obtaining the feedback voltage according to the output voltage; a current feedback circuit, generating a second control signal according to the output current; a switch circuit, providing the voltage reference according to the second control signal. Among them, in a first phase of a startup process, the voltage reference is less than or equal to an initial value, and the current feedback circuit limits the output current according to the second control signal; in a second phase of the startup process, the switch circuit switches a voltage value of the voltage reference to a target value.

Abstract: A method includes generating a voltage difference indication between a previous voltage on the bit line of a DRAM and a current voltage on a bit line. In an embodiment, the previous voltage corresponds to a logic 1 voltage or a logic 0 voltage stored in a previous DRAM cell of a column of DRAM cells, the current voltage corresponds to a logic 1 voltage or a logic 0 voltage being stored in the current DRAM cell of the column of DRAM cells, and the bit line is coupled to the column of DRAM cells. When the current DRAM cell is in a read mode, the method further includes the following steps: Generating a read voltage reference based on the voltage difference indication; Generating a read output voltage based on the read voltage reference; Supplying the read output voltage on to the bit line; and Outputting a representation of the read output voltage.

Abstract: In at least one embodiment, an interface electronic circuit for a capacitive acoustic transducer having a sensing capacitor is provided. The interface electronic circuit includes an amplifier, a voltage regulator, a common-mode control circuit, and a reference generator. The amplifier has an input coupled to an electrode of the sensing capacitor. The voltage regulator is configured to receive a regulator reference voltage, generate a regulated voltage based on the regulator reference voltage, and supply the regulated voltage to a supply input of the amplifier. The common-mode control circuit controls a common-mode voltage present on the input of the amplifier based on a common-mode reference voltage. The reference generator receives a supply voltage and generates the regulator reference voltage and the common-mode reference voltage with respective values that are variable as a function of the supply voltage.

Abstract: A driver circuitry includes a voltage application circuitry, a current detection circuitry, and a control circuitry. The voltage application circuitry is connected to a drive terminal of a transistor, and controls a voltage of an input signal and applies to the drive terminal. The current detection circuitry is connected to an output terminal of the transistor, and detects that a current output from the transistor becomes a size of a predetermined current or more. The control circuitry is connected to the current detection circuitry, and controls the voltage application circuitry based on the voltage of the input signal to output a voltage between the drive terminal and the output terminal at the timing when the current detection circuitry detects the current of the predetermined current or more.

Abstract: Embodiments of the present invention disclose a low dropout regulator and a phase-locked loop. The low dropout regulator includes: a reference voltage source, an error amplifier coupled to the reference voltage source, a regulating circuit, a load coupled to the regulating circuit, a first compensation circuit, and a second compensation circuit. The regulating circuit produces a regulating current under control of a control voltage from the error amplifier. The first compensation circuit is coupled between the error amplifier and the regulating circuit. The second compensation circuit is coupled between an input terminal and an output terminal of the regulating circuit.