Using Field-effect Transistor Patents (Class 327/543)
  • Patent number: 11323113
    Abstract: A current flow control device includes a plurality of semiconductor switches disposed between a power source and a load and that are connected in parallel with each other, and the current flow control device being configured to control the flow of current between the power source and the load by turning on and off the semiconductor switches. The plurality of semiconductor switches include a first and a second semiconductor switch. The current flow control device includes a driving circuit configured to apply, to the first semiconductor switch, a voltage that is higher than a voltage output from the power source, to turn on the first semiconductor switch, a switch control unit configured to turn on the second semiconductor switch, and a resistor that is connected in series with a terminal on the power source side of the second semiconductor switch, the resistor lowering a voltage applied to the terminal.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: May 3, 2022
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventor: Hideo Morioka
  • Patent number: 11276780
    Abstract: A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Tahir Ghani, Stephen Cea
  • Patent number: 11271548
    Abstract: A starting circuit capable of further reducing an influence of a variation in the threshold voltage of a transistor is proposed. The starting circuit includes an N-type first MOS transistor whose threshold voltage is near 0 V, a resistor interposed between a source terminal of the first MOS transistor and a ground, and a control circuit controlling a gate voltage of the first MOS transistor. An amount of first current transmitted to a device to be driven and starting the device is controlled according to the control of the gate voltage.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: March 8, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hiroyuki Watanabe
  • Patent number: 11251759
    Abstract: An apparatus has four transistors. The first and third transistors each have a gate coupled to a first input terminal and second input terminal respectively, a source coupled to a current source and to a first terminal of a bias voltage source, and a substrate coupled to a second terminal of the bias voltage source. The second and fourth transistors each have a gate coupled to the first input terminal and the second input terminal respectively, a source coupled to the drain of the first and third transistors respectively, a drain coupled to a lower voltage supply and a substrate coupled to its source. The bias voltage source increases the threshold voltages of the first and third transistors above the second and fourth transistors, respectively. This ensures that the first and third transistors turn on after the second and fourth transistors, respectively.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: February 15, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vadim Valerievich Ivanov, Srinivas Kumar Pulijala
  • Patent number: 11239656
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for current sensing and current limiting. An example apparatus includes a first main transistor including a first main transistor gate terminal coupled between an output terminal and an intermediate node; a second main transistor including a second main transistor gate terminal coupled between the intermediate node and a ground terminal; a first amplifier including a first amplifier output coupled to the first main transistor gate terminal; a second amplifier including a second amplifier output coupled to the second main transistor gate terminal; and a third amplifier including a third amplifier inverting input coupled to the intermediate node, a third amplifier non-inverting input coupled to a sense transistor, and a third amplifier output coupled to a third gate terminal of a third transistor.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: February 1, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Roy Alan Hastings
  • Patent number: 11196422
    Abstract: A cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, a battery-indifferent or pure energy harvesting multi-mode system, a method of operating a cell logic structure for a battery-indifferent or pure energy harvesting multi-mode system, and a method of operating battery-indifferent or pure energy harvesting multi-mode system.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: December 7, 2021
    Assignee: NATIONAL UNIVERSITY OF SINGAPORE
    Inventors: Longyang Lin, Saurabh Jain, Massimo Alioto
  • Patent number: 11158360
    Abstract: A memory device including a voltage boosting circuit, a switching circuit and a word line driving circuit is provided. The voltage boosting circuit is activated in a sleep mode. The voltage boosting circuit, based on an activation signal, performs a voltage boosting operation on a power voltage of a power voltage rail to generate a boosting voltage and transmit the boosting voltage to a control voltage rail. The switching circuit is turned on or cut-off according to a first mode selection signal. The word line driving circuit generates a plurality of word line signals according to the boosting voltage in the sleep mode; in addition, the word line driving circuit generates the word line signals according to the power voltage in a normal mode.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: October 26, 2021
    Assignee: DigWise Technology Corporation, LTD
    Inventors: Shih-Hao Chen, Wen-Pin Hsieh
  • Patent number: 11126249
    Abstract: Disclosed are devices, systems, and methods for the use of memory including a data table configured to store a plurality of elements, wherein the plurality of elements are arranged into a plurality of buckets and each of the plurality of buckets comprising a plurality of entries. A first power domain can be associated with an entry of each bucket or with a first bucket. A second power domain can be associated with a second entry of each bucket or a second bucket. Processing logic can be configured to search for a particular value stored in an element of the plurality of elements by selecting buckets of the plurality of buckets and selecting at least one entry of each of the buckets. A programmable register can be used to select a powered state of the second power domain based on a configuration of the programmable register.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: September 21, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Kari Ann O'Brien, Bijendra Singh, Thomas A. Volpe
  • Patent number: 11068007
    Abstract: A voltage reference includes a flipped gate transistor coupled between a first node configured to carry an operating voltage and a second node configured to carry a negative supply voltage. A first transistor and a second transistor are coupled in series between the first node and the second node, a gate of the first transistor is coupled with a gate of the flipped gate transistor, and a gate of the second transistor is configured to receive the negative supply voltage. An output node between the first transistor and the second transistor is configured to output a reference voltage, and a current source coupled between the output node and the second node is configured to supply a current through the first transistor based on a current through the flipped gate transistor.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mohammad Al-Shyoukh, Alex Kalnitsky
  • Patent number: 11029718
    Abstract: An apparatus is provided which includes: a first supply node; a second supply node; a first transistor coupled to the first supply node, the first transistor is to provide a first current which is complementary to absolute temperature (CTAT); a second transistor coupled to the first supply node, the second transistor is to provide a second current which is proportional to absolute temperature (PTAT); a resistive device coupled in series at a node with the first and second transistors, and coupled to the second supply node, wherein the node is to sum the CTAT and the PTAT currents.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventor: Matthias Eberlein
  • Patent number: 10971941
    Abstract: A charging circuit for an electrical energy storage system having electrical energy storage units. The charging circuit includes a first input and a second input for electrically connecting to an energy source, a first output and a second output, and first pole connections and second pole connections. The pole connections are connected in an electrically conductive manner to corresponding pole connections of the electrical energy storage units. In addition, the charging circuit includes first switches, second switches, and third switches.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: April 6, 2021
    Assignee: Robert Bosch GmbH
    Inventor: Berengar Krieg
  • Patent number: 10886267
    Abstract: The reference voltage generation device includes a constant current circuit which includes a first MOS transistor, and a voltage generation circuit which includes a second MOS transistor. The first MOS transistor includes a gate electrode, a source region, a drain region, and a channel impurity region which have a first conductivity type and has a first channel size. The second MOS transistor includes a gate electrode of a second conductivity type, and a source region, a drain region, and a channel impurity region which have the first conductivity type and has a second channel size different from the first channel size. The channel impurity regions have different impurity concentrations.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: January 5, 2021
    Assignee: ABLIC INC.
    Inventor: Hideo Yoshino
  • Patent number: 10879801
    Abstract: A power converter can include: first and second terminals; N A-type switching power stage circuits, each having a first energy storage element, where N is a positive integer, a first terminal of a first A-type switching power stage circuit in the N A-type switching power stage circuits is coupled to the first terminal of the power converter, and a second terminal of each of the N A-type switching power stage circuits is coupled to the second terminal of the power converter; one B-type switching power stage circuit; and N second energy storage elements, each being coupled to one of the N A-type switching power stage circuits, and the B-type switching power stage circuit is coupled between a terminal of one of the N second energy storage elements corresponding to the B-type switching power stage circuit and the second terminal of the power converter.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: December 29, 2020
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Wang Zhang, Chen Zhao
  • Patent number: 10848151
    Abstract: The present invention provides a driving system operating in a first or second modes. The driving system includes first and second resistance adjusting circuits, a divider, a controller and a driver. The divider divides a second resistance adjusting signal generated by the second resistance adjusting circuit by a standard value to generate a first control signal. The controller receives the first control signal and generates a second control signal. When the driving system operates in the first mode, the driver receives the second control signal, according to the second control signal, the driver adjusts an output impedance of itself and adjusts equalization amplitude of a first differential output signal generated by itself. When the driving system operates in the second mode, the driver generates a second differential output signal and adjusts the output impedance according to a first resistance adjusting signal generated by the first resistance adjusting circuit.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 24, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Yulin Deng, Xinwen Ma
  • Patent number: 10775827
    Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: September 15, 2020
    Assignee: pSemi Corporation
    Inventors: Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta
  • Patent number: 10778092
    Abstract: The present disclosure provides a negative voltage generating circuit having an automatic voltage adjustment function, including a negative voltage generating circuit and a feedback control module. The negative voltage generated by the negative voltage generating circuit is adjusted by the feedback control module. The negative voltage generating circuit having the automatic voltage adjustment function of the present disclosure can automatically adjust the charge current of the charge pump according to the load current, thereby realizing the stability of the output voltage, such that the traditional analog circuit structure can work normally under the extremely low power supply voltage, and is particularly suitable for the deep submicron process. The present disclosure also realizes the digital adjustment of the output voltage, the negative voltage output is no longer single, and can be adjusted according to actual needs.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 15, 2020
    Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Rongbin Hu, Yonglu Wang, Zhengping Zhang, Jian'an Wang, Guangbing Chen, Dongbing Fu, Yuxin Wang, Hequan Jiang, Gangyi Hu
  • Patent number: 10778111
    Abstract: A current regulating apparatus capable of regulating an electrical current with a high level of precision and over a wide range of voltages includes a first depletion mode field-effect transistor (FET), a second depletion mode FET, and a fixed resistor. The second depletion mode FET and fixed resistor are connected in series and across the gate-source terminals of the first depletion mode FET. The first depletion mode FET operates as an adjustable current source while the second depletion mode FET is controlled to operate as a voltage controlled resistor. The magnitude of current regulated by the current regulating apparatus is determined based on both the resistance of the fixed resistor and a current-setting control voltage applied to the gate of the second depletion mode FET. Various precision values of regulated current can be realized by simply changing the current-setting control voltage.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: September 15, 2020
    Assignee: Eridan Communications, Inc.
    Inventor: Waclaw Godycki
  • Patent number: 10593744
    Abstract: An apparatus includes transistor and a set of one or more serially-connected diodes coupled to the transistor. The transistor includes a gate, and first and second terminals. A first diode in the set of serially-connected diodes has a first terminal connected to the second terminal of the transistor. At least one of the diodes includes a first layer including silicon having a first type of carrier as its majority carrier, a first terminal, and a second terminal. The first terminal includes a second layer formed on the first layer, a third layer comprising amorphous hydrogenated silicon having a second type of carrier as its majority carrier formed on the second layer, and a conductive layer formed on the third layer. The second terminal includes a fourth layer comprising crystalline hydrogenated silicon of the first carrier type formed on the first layer, and a conductive layer formed on the fourth layer.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10581423
    Abstract: Fault tolerant switches are provided herein. In certain embodiments, a fault tolerant switch includes a switch, a gate driver, and a clamp. The switch includes a switch p-type field effect transistor (PFET) and a switch n-type field effect transistor (NFET) electrically connected in series and controlled by the gate driver. Additionally, the clamp is electrically connected in parallel with the switch, and includes a forward protection circuit including a first diode and a first clamp FET in series, and a reverse protection circuit including a second diode and a second clamp FET in series. The clamp further includes a first gate bias circuit configured to bias a gate of the first clamp FET and a second gate bias circuit configured to bias a gate of the second clamp FET.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: March 3, 2020
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Srivatsan Parthasarathy, Sirui Luo, Thomas Paul Kearney, Yuanzhong Zhou, Donal Bourke, Jean-Jacques Hajjar
  • Patent number: 10571516
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include converter circuitry that operates to provide a drive current. The integrated circuit may include process detector circuitry having multiple drive strength devices that are driven by the drive current from the converter circuitry. The multiple drive strength devices may provide multiple drive strength signals based on the drive current. The integrated circuit may include comparator circuitry having a comparator that receives the multiple drive strength signals from the multiple drive strength devices, detects a voltage difference between the multiple drive strength signals, and provides an output signal based on the detected voltage difference.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: February 25, 2020
    Assignee: ARM Limited
    Inventors: Bal S. Sandhu, George McNeil Lattimore
  • Patent number: 10559641
    Abstract: An apparatus includes a junction field-effect transistor (JFET) and a set of one or more serially-connected diodes. The JFET includes a first layer including silicon of a first conductivity type, a gate, and first and second terminals. The gate includes a second layer formed on the first layer and including intrinsic amorphous hydrogenated silicon, a third layer formed on the second layer and including amorphous hydrogenated silicon of a second conductivity type, and a conductive layer formed on the third layer. Each of the first and second terminals includes a fourth layer formed on the first layer, the fourth layer including crystalline hydrogenated silicon of the first conductivity type, and a conductive layer formed on the fourth layer. Each of the serially-connected diodes has first and second terminals, a first of the serially-connected diodes having the first terminal connected to the second terminal of the JFET.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10511304
    Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Lei Pan, Zhen Tang, Miranda Ma
  • Patent number: 10475871
    Abstract: An apparatus includes a junction field-effect transistor (JFET) and a set of one or more serially-connected diodes. The JFET includes a first layer including silicon of a first conductivity type, a gate, and first and second terminals. The gate includes a second layer formed on the first layer and including intrinsic amorphous hydrogenated silicon, a third layer formed on the second layer and including amorphous hydrogenated silicon of a second conductivity type, and a conductive layer formed on the third layer. Each of the first and second terminals includes a fourth layer formed on the first layer, the fourth layer including crystalline hydrogenated silicon of the first conductivity type, and a conductive layer formed on the fourth layer. Each of the serially-connected diodes has first and second terminals, a first of the serially-connected diodes having the first terminal connected to the second terminal of the JFET.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: November 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 10396693
    Abstract: A method for controlling a brushless direct current (BLDC) motor is disclosed. The method includes: receiving a constant current; comparing the constant current to a reference current; based on the comparison revealing that the constant current is smaller than the reference current, providing a first speed command to the rotational speed control unit to increase a speed of the BLDC motor; based on the comparison revealing that the constant current is larger than the reference current, providing a second speed command to the rotational speed control unit to decrease a speed of the BLDC motor; based on the comparison revealing that the constant current is the same as the reference current, providing a third speed command to the rotational speed control unit to maintain a speed of the BLDC motor; and controlling, by the rotational speed control unit, a speed of the BLDC motor.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: August 27, 2019
    Assignee: LG Electronics Inc.
    Inventors: Jongseong Ji, Wontae Kim
  • Patent number: 10396777
    Abstract: An ORing circuit is provided. The ORing circuit includes an input port, an output port, an ORing FET, a comparing circuit, a first transistor and a second transistor. The ORing FET is connected between the input port and the output port and comprises a source connected with the input port, a gate and a drain connected with the output port. The comparing circuit is connected with the input port and the gate. The first transistor comprises a first terminal, a second terminal and a third terminal. The first terminal is connected with the input port and the source, and the third terminal is connected with the gate. The second transistor comprises a fourth terminal, a fifth terminal and a sixth terminal. The fourth terminal is connected with the output port and the drain, and the sixth terminal is connected with the second terminal of the first transistor.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: August 27, 2019
    Assignee: DELTA ELECTRONICS (THAILAND) PUBLIC COMPANY LIMITED
    Inventor: Cheevanantachai Phichej
  • Patent number: 10387690
    Abstract: This invention is an SOC with an integrated single rail power supply that interfaces with the host controller and dynamically changes the host interface supply to 3.3 volts or 1.8 volts based on the sensed card speed grade. The SOC initially selects 3.3 volts to supply to the memory card. The SOC communicates with memory card vis input/output circuits to determine a memory type. The controller selects a 3.3 volt or 1.8 volt supply for the memory card based upon the determination. The SOC powers the input/output circuits at the same supply voltage as the memory card. This invention employs 1.8 volt transistors in the input/output circuits using a bias voltage to protect these transistor from the full 3.3 volt power when the memory card is powered to 3.3 volts.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 20, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Siva Srinivas Kothamasu, Haydar Bilhan
  • Patent number: 10355605
    Abstract: A flyback converter with adjustable frequency curve includes a primary winding configured to receive an input voltage, a secondary winding coupled to the primary winding to generate an output DC voltage, a feedback circuit configured to receive the output DC signal and generate a feedback signal, a multi-mode control circuit, an auxiliary winding configured to provide power for operating the multi-mode control circuit, an exterior adjustable circuit connected between the auxiliary winding and the multi-mode controller for adjusting the input voltage level of the input feedthrough of the multi-mode control circuit, wherein the multi-mode control circuit configured to generate a switch control signal based on the information associated with the adjusted input signal through the input feedthrough of the multi-mode control circuit and the feedback signal, and a switching device configured to receive the switch control signal and change a current flowing through the primary winding.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 16, 2019
    Assignee: WUXI XU DA ELECTRONIC TECHNOLOGY CO, LTD.
    Inventors: Huang-Chi Lin, Chi-Hao Wu, Jun-Hsiung Huang
  • Patent number: 10289137
    Abstract: In accordance with an embodiment of the present invention, a method of controlling current through a transistor includes measuring a voltage across the transistor, measuring a current through the transistor, determining a safe operating current for the measured voltage across the transistor, and adjusting a voltage of a control node of the transistor using a feedback controller until the measured current through the transistor is not greater than the determined safe operating current.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: May 14, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Kennith Kin Leong, Gerald Deboy, Sebastian Uitz, Juan Sanchez
  • Patent number: 10283065
    Abstract: A display device comprises: a timing controller that is turned on to a floating state by a first logic voltage and, after a switching period, switches from the floating state to a normal operating state based on a reset signal to generate timing control signals; a level shifter configured to receive the first logic voltage and a second logic voltage and level-shift the timing control signals to the second logic voltage; and an output enable signal control part that outputs an output enable signal at enable level LOW or disable level HIGH, in synchronization with the reset signal, wherein, during the switching period, the level shifter receives the output enable signal at the disable level HIGH and does not level-shift the timing control signals.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: May 7, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Dogon Lee, Yeontaek Yoo
  • Patent number: 10234485
    Abstract: A measuring arrangement for determining at least one measured variable with a sensor device (2), a signal outlet for outputting of an output signal and a current-adjusting device for adjusting the current of the output signal provides a measuring arrangement whose power consumption is at a maximum for preferably all states of operation. The object is obtained the measuring arrangement that a load current device and a regulating device are provided. Here, the regulating device controls the load current device based on a voltage drop via the current-adjusting device (4).
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: March 19, 2019
    Assignee: KROHNE MESSTECHNIK GMBH
    Inventor: Steffen Dymek
  • Patent number: 10216209
    Abstract: A digital Low Drop-Out regulator includes: an event-driven circuit for generating a trigger signal by asynchronously detecting whether an output voltage is out of a threshold range to generate a first error information signal and a first control signal; a time-driven circuit for generating a second error information signal by detecting a change in the output voltage synchronized with a clock signal, and generating a second control signal by combining the first and second error information signals; a clock/trigger control circuit for generating the clock signal having a first or second cycle based on the trigger signal and the first and second error information signals; a first array driver for controlling driving force of the output voltage in response to the first control signal; and a second array driver for controlling the driving force of the output voltage in response to the second control signal.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: February 26, 2019
    Assignees: SK Hynix Inc., THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
    Inventors: Hyun-Ju Ham, Jong-Hwan Kim, Min-Goo Seok, Do-Yun Kim, Sung Justin Kim
  • Patent number: 9996100
    Abstract: A current reference circuit and a semiconductor IC including the current reference circuit, the current reference circuit including a proportional to absolute temperature (PTAT) current generator configured to generate, in an output branch, a first current proportional to a temperature; and a current subtractor configured to generate a reference current by subtracting a second current generated based on a current flowing in an internal branch of the PTAT current generator, from the first current flowing in the output branch. The second current is set to have a same temperature-based change characteristic as the first current and a level different from a level of the first current.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: June 12, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ho-Young Shin
  • Patent number: 9978866
    Abstract: A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung Tsai, Kuo-Feng Yu, Kei-Wei Chen
  • Patent number: 9864393
    Abstract: In some embodiments, a circuit includes a first transistor, a second transistor, a resistive device and an amplifier. The first transistor includes a first drain and a first gate. The second transistor includes a second drain and a second gate. The resistive device is coupled between the first gate and the second gate. The amplifier includes a first input coupled to the first drain and a second input coupled to the second drain. The amplifier is configured to keep a voltage level at the first drain and that at the second drain equal to each other.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD
    Inventors: Jaw-Juinn Horng, Amit Kundu
  • Patent number: 9866216
    Abstract: A circuit includes a biasing circuit that includes a diode stack coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a transistor, a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the diode stack in response to a transition of the ISO signal between a first voltage and a second voltage. The biasing circuit also is configured to output a signal to a level shifter to hold an output of the level shifter in a known state for a specified amount of time after power-up of the circuit for proper operation of the level shifter.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: January 9, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Iulian C. Gradinariu, Jayant Ashokkumar, Bogdan Samson, Vijay Raghavan
  • Patent number: 9768799
    Abstract: An analog to digital converter is provided. The analog to digital converter includes: an arithmetic operator combining an analog input signal with a feedback signal; a loop filter filtering an output signal of the arithmetic operator; a quantizer quantizing an output signal of the loop filter to output a digital signal; and a feedback converting the digital signal to output a feedback signal, in which the quantizer includes: a plurality of VCOs each receiving a positive output signal and a negative output signal of the loop filter and outputting VCO signals; a plurality of samplers receiving the VCO signals output from the plurality of VCOs, respectively and outputting sampled signals; and a phase detector detecting a phase difference in the sampled signals output from the plurality of samplers, respectively, to detect a phase difference in two VCO signals output from the plurality of VCOs, respectively.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 19, 2017
    Assignee: Industry University Cooperation Foundation Hanyang University
    Inventors: Changsik Yoo, Donghyeok Jeong, Jinho Noh
  • Patent number: 9696351
    Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: July 4, 2017
    Assignee: STMicroelectronics International N.V.
    Inventors: Daljeet Kumar, Tapas Nandy, Surendra Kumar
  • Patent number: 9559014
    Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: January 31, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang
  • Patent number: 9450568
    Abstract: A bias circuit includes second order process variation compensation in a current source topology having a compensation transistor operating in saturation mode as a current source. An additional compensation transistor is biased to operate in a linear mode to provide an active resistor to vary a control voltage applied to the saturation mode compensation transistor and widen the range of sourced control current, thus widening the achievable range of the control voltage applied to the biasing transistor to produce a predetermined level of bias current despite process variations. The additional compensation transistor has been shown to be able to compensate for another approximately 20-25% of the induced variations leaving less than approximately 10% and preferably less than 5% variation in the bias current from the predetermined level at certain bias conditions and over typical fabrication process variations.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 20, 2016
    Assignee: Raytheon Company
    Inventors: Michael G. Hawkins, David D. Heston
  • Patent number: 9438240
    Abstract: A circuit includes a biasing circuit that includes a load circuit coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the load circuit in response to a transition of the ISO signal between a high voltage and a low voltage. The biasing circuit also includes circuitry to generate an isolation delayed (ISO_DEL) signal. The ISO_DEL signal has a high voltage in response to the biasing signal being within a first threshold level and the ISO_DEL signal has a low voltage in response to the biasing signal being within a second threshold level. The biasing circuit outputs the ISO_DEL signal.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: September 6, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Iulian C. Gradinariu, Jayant Ashokkumar, Bogdan Samson, Vijay Raghavan
  • Patent number: 9367077
    Abstract: A BGR circuit includes a first bipolar transistor and a second bipolar transistor that are connected between a power supply terminal and a ground terminal, each base of the first bipolar transistor and the second bipolar transistor being connected to an output terminal. A first resistor is connected between the ground terminal and the first bipolar transistor. A second resistor and a third resistor are connected in series between the first resistor and the second bipolar transistor. A temperature correction circuit is connected between the ground terminal and a node between the second resistor and the third resistor, and includes a first transistor having a base connected to an end of the first bipolar transistor of the first resistor. The temperature correction circuit further includes a fourth resistor connected in series to the first transistor.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: June 14, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideki Kiuchi
  • Patent number: 9354646
    Abstract: A voltage generator of a contactless integrated circuit (IC) card includes a regulator configured to generate a first internal voltage based on an input voltage and a first reference voltage, the input voltage being received through an antenna of the contactless IC card. The voltage generator includes an internal voltage generator configured to generate a second internal voltage, the second internal voltage being used to operate an internal circuit of the contactless IC card. The voltage generator includes a reference voltage generator configured to generate a second reference voltage based on the first internal voltage, the second reference voltage being generated without regard to a fluctuation component of the first internal voltage. The voltage generator includes a switching unit configured to provide one of the first and second internal voltages as the first reference voltage in response to first and second switching control signals.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: May 31, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Ho Kim, Il-Jong Song, Jong-Pil Cho
  • Patent number: 9347986
    Abstract: A device for monitoring the latency of electronic circuits based on microtechnology and/or nanotechnology, said circuits to be tested being supplied with the aid of a voltage Vdd, having a low level and a high level, for the detection of delay faults of said circuits, comprises: at least one device of type I placed between the high level of the power supply voltage and the elements of the circuit to be tested, and/or at least one device of type II placed between the low level of the power supply voltage of the elements of the elements of said circuit to be tested, the device of type I and the device of type II comprising at least one low-latency electrical path, said low-latency path being connected in parallel with a high-latency electrical path, a test signal monitoring the opening of the low-latency paths while the high-latency electrical paths are open.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: May 24, 2016
    Assignee: Commissariat A L'Energie et Aux Energies Alternatives
    Inventors: Valentin Gherman, Yannick Bonhomme
  • Patent number: 9350239
    Abstract: A power management system that can include an application processor and a power management unit (PMU). The PMU can generate a regulated output voltage based on control signals generated by a switch control module of the application processor. The control signals can be determined based on a comparison of monitored voltages within the application processor and a generated reference voltage. The reference voltage can be generated based on fed back signals corresponding to the control signals. The application processor and the PMU can be formed utilizing different size manufacturing process technologies. For example, the PMU can be formed utilizing a larger size manufacturing process technology than the application processor.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: May 24, 2016
    Assignee: Broadcom Corporation
    Inventors: Vadim Bishtein, Eric Martin Hayes, Kerry Thompson, Walter Soto, Stephen Douglas Cook
  • Patent number: 9350278
    Abstract: A current sensing circuit includes: a first controlled device; a first controlled device; a first current mirror configured to cause a first mirror current to flow through a first load device based on a first control signal received by the first controlled device; a second controlled device; a second current mirror configured to cause a second mirror current to flow through a second load device based on a second control signal received by the second controlled device; and an amplifier configured to output a voltage signal based on the first mirror current flowing through the first load device and the second mirror current flowing through the second load device. The first control signal is substantially proportional to a first drive signal applied to a first controlled remote device, and the second control signal is substantially proportional to a second drive signal applied to of a second controlled remote device.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: May 24, 2016
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard A. Schwab, John R. Agness
  • Patent number: 9329219
    Abstract: A control module includes an input module configured to operate in a normal operating state and a fault diagnosis state. The input module receives an input signal from a circuit module and generates a voltage based on the input signal. In the normal operating state, a fault diagnostic module determines whether the voltage is in a first range or a second range. The first range and the second range indicate that a fault is detected in the circuit module. The fault diagnostic module determines that the detected fault is a first fault type if the voltage is in the first range, transitions the input module from the normal operating state to the fault diagnosis state if the voltage is in the second range, and determines whether the detected fault is a second fault type or a third fault type based on the voltage in the fault diagnosis state.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: May 3, 2016
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Timothy P. Philippart, Steven Zechiel
  • Patent number: 9287276
    Abstract: A semiconductor memory cell array is disclosed that includes a memory cell unit. The memory cell unit includes an active region, a first transistor, a second transistor, a gate structure, and an interconnect. The first transistor and the second transistor are formed on the active region. The gate structure is formed on the active region and between the first transistor and the second transistor. The interconnect connects the gate structure and at least one of sources of the first transistor and the second transistor to a power line.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: March 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shi-Wei Chang, Hong-Chen Cheng, Chien-Chi Tien, Li-Chun Tien, Kuo-Hua Pan, Jhon-Jhy Liaw
  • Patent number: 9280168
    Abstract: A highly distributed current reference for a solid-state memory comprises a centrally located current digital-to-analog converter (IDAC) and a plurality of remotely located tile current references. The IDAC comprises a first active device that generates a reference current, and a device that forms a first source degeneration resistance for the first active device. The IDAC outputs a voltage signal that represents a magnitude of the reference current. A remotely located tile current reference comprises a second active device and a device that forms a second source degeneration resistance for the second active device. The source degeneration resistances and capacitance coupled to the voltage signal output from the IDAC compensate for current, temperature, supply and process variations.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: March 8, 2016
    Assignee: Intel Corporation
    Inventors: Matthew G. Dayley, Yadhu Vamshi S. Vancha
  • Patent number: 9280165
    Abstract: Provided are: a power supply control circuit having a configuration in which an N-channel FET and a P-channel FET can appropriately and selectively be used so as to control power feeding with high efficiency and at low cost; and a power supply control device including the power supply control circuit. An N-channel FET (NchFET in the drawings) and a P-channel FET (PchFET in the drawings) are connected in parallel with each other between the positive voltage side (+B) of a battery (direct current power supply) and a plurality of ECUs (loads) 4, 4, . . . , so as to appropriately control ON and OFF.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: March 8, 2016
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Shigeyuki Fujii
  • Patent number: RE46107
    Abstract: An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Steven Swei, Chih-Chang Lin, Tien-Chun Yang, Chan-Hong Chern, Ming-Chieh Huang