Using Field-effect Transistor Patents (Class 327/543)
  • Patent number: 10396693
    Abstract: A method for controlling a brushless direct current (BLDC) motor is disclosed. The method includes: receiving a constant current; comparing the constant current to a reference current; based on the comparison revealing that the constant current is smaller than the reference current, providing a first speed command to the rotational speed control unit to increase a speed of the BLDC motor; based on the comparison revealing that the constant current is larger than the reference current, providing a second speed command to the rotational speed control unit to decrease a speed of the BLDC motor; based on the comparison revealing that the constant current is the same as the reference current, providing a third speed command to the rotational speed control unit to maintain a speed of the BLDC motor; and controlling, by the rotational speed control unit, a speed of the BLDC motor.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: August 27, 2019
    Assignee: LG Electronics Inc.
    Inventors: Jongseong Ji, Wontae Kim
  • Patent number: 10396777
    Abstract: An ORing circuit is provided. The ORing circuit includes an input port, an output port, an ORing FET, a comparing circuit, a first transistor and a second transistor. The ORing FET is connected between the input port and the output port and comprises a source connected with the input port, a gate and a drain connected with the output port. The comparing circuit is connected with the input port and the gate. The first transistor comprises a first terminal, a second terminal and a third terminal. The first terminal is connected with the input port and the source, and the third terminal is connected with the gate. The second transistor comprises a fourth terminal, a fifth terminal and a sixth terminal. The fourth terminal is connected with the output port and the drain, and the sixth terminal is connected with the second terminal of the first transistor.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: August 27, 2019
    Assignee: DELTA ELECTRONICS (THAILAND) PUBLIC COMPANY LIMITED
    Inventor: Cheevanantachai Phichej
  • Patent number: 10387690
    Abstract: This invention is an SOC with an integrated single rail power supply that interfaces with the host controller and dynamically changes the host interface supply to 3.3 volts or 1.8 volts based on the sensed card speed grade. The SOC initially selects 3.3 volts to supply to the memory card. The SOC communicates with memory card vis input/output circuits to determine a memory type. The controller selects a 3.3 volt or 1.8 volt supply for the memory card based upon the determination. The SOC powers the input/output circuits at the same supply voltage as the memory card. This invention employs 1.8 volt transistors in the input/output circuits using a bias voltage to protect these transistor from the full 3.3 volt power when the memory card is powered to 3.3 volts.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 20, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Siva Srinivas Kothamasu, Haydar Bilhan
  • Patent number: 10355605
    Abstract: A flyback converter with adjustable frequency curve includes a primary winding configured to receive an input voltage, a secondary winding coupled to the primary winding to generate an output DC voltage, a feedback circuit configured to receive the output DC signal and generate a feedback signal, a multi-mode control circuit, an auxiliary winding configured to provide power for operating the multi-mode control circuit, an exterior adjustable circuit connected between the auxiliary winding and the multi-mode controller for adjusting the input voltage level of the input feedthrough of the multi-mode control circuit, wherein the multi-mode control circuit configured to generate a switch control signal based on the information associated with the adjusted input signal through the input feedthrough of the multi-mode control circuit and the feedback signal, and a switching device configured to receive the switch control signal and change a current flowing through the primary winding.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 16, 2019
    Assignee: WUXI XU DA ELECTRONIC TECHNOLOGY CO, LTD.
    Inventors: Huang-Chi Lin, Chi-Hao Wu, Jun-Hsiung Huang
  • Patent number: 10289137
    Abstract: In accordance with an embodiment of the present invention, a method of controlling current through a transistor includes measuring a voltage across the transistor, measuring a current through the transistor, determining a safe operating current for the measured voltage across the transistor, and adjusting a voltage of a control node of the transistor using a feedback controller until the measured current through the transistor is not greater than the determined safe operating current.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: May 14, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Kennith Kin Leong, Gerald Deboy, Sebastian Uitz, Juan Sanchez
  • Patent number: 10283065
    Abstract: A display device comprises: a timing controller that is turned on to a floating state by a first logic voltage and, after a switching period, switches from the floating state to a normal operating state based on a reset signal to generate timing control signals; a level shifter configured to receive the first logic voltage and a second logic voltage and level-shift the timing control signals to the second logic voltage; and an output enable signal control part that outputs an output enable signal at enable level LOW or disable level HIGH, in synchronization with the reset signal, wherein, during the switching period, the level shifter receives the output enable signal at the disable level HIGH and does not level-shift the timing control signals.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: May 7, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Dogon Lee, Yeontaek Yoo
  • Patent number: 10234485
    Abstract: A measuring arrangement for determining at least one measured variable with a sensor device (2), a signal outlet for outputting of an output signal and a current-adjusting device for adjusting the current of the output signal provides a measuring arrangement whose power consumption is at a maximum for preferably all states of operation. The object is obtained the measuring arrangement that a load current device and a regulating device are provided. Here, the regulating device controls the load current device based on a voltage drop via the current-adjusting device (4).
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: March 19, 2019
    Assignee: KROHNE MESSTECHNIK GMBH
    Inventor: Steffen Dymek
  • Patent number: 10216209
    Abstract: A digital Low Drop-Out regulator includes: an event-driven circuit for generating a trigger signal by asynchronously detecting whether an output voltage is out of a threshold range to generate a first error information signal and a first control signal; a time-driven circuit for generating a second error information signal by detecting a change in the output voltage synchronized with a clock signal, and generating a second control signal by combining the first and second error information signals; a clock/trigger control circuit for generating the clock signal having a first or second cycle based on the trigger signal and the first and second error information signals; a first array driver for controlling driving force of the output voltage in response to the first control signal; and a second array driver for controlling the driving force of the output voltage in response to the second control signal.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: February 26, 2019
    Assignees: SK Hynix Inc., THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
    Inventors: Hyun-Ju Ham, Jong-Hwan Kim, Min-Goo Seok, Do-Yun Kim, Sung Justin Kim
  • Patent number: 9996100
    Abstract: A current reference circuit and a semiconductor IC including the current reference circuit, the current reference circuit including a proportional to absolute temperature (PTAT) current generator configured to generate, in an output branch, a first current proportional to a temperature; and a current subtractor configured to generate a reference current by subtracting a second current generated based on a current flowing in an internal branch of the PTAT current generator, from the first current flowing in the output branch. The second current is set to have a same temperature-based change characteristic as the first current and a level different from a level of the first current.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: June 12, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ho-Young Shin
  • Patent number: 9978866
    Abstract: A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung Tsai, Kuo-Feng Yu, Kei-Wei Chen
  • Patent number: 9866216
    Abstract: A circuit includes a biasing circuit that includes a diode stack coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a transistor, a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the diode stack in response to a transition of the ISO signal between a first voltage and a second voltage. The biasing circuit also is configured to output a signal to a level shifter to hold an output of the level shifter in a known state for a specified amount of time after power-up of the circuit for proper operation of the level shifter.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: January 9, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Iulian C. Gradinariu, Jayant Ashokkumar, Bogdan Samson, Vijay Raghavan
  • Patent number: 9864393
    Abstract: In some embodiments, a circuit includes a first transistor, a second transistor, a resistive device and an amplifier. The first transistor includes a first drain and a first gate. The second transistor includes a second drain and a second gate. The resistive device is coupled between the first gate and the second gate. The amplifier includes a first input coupled to the first drain and a second input coupled to the second drain. The amplifier is configured to keep a voltage level at the first drain and that at the second drain equal to each other.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD
    Inventors: Jaw-Juinn Horng, Amit Kundu
  • Patent number: 9768799
    Abstract: An analog to digital converter is provided. The analog to digital converter includes: an arithmetic operator combining an analog input signal with a feedback signal; a loop filter filtering an output signal of the arithmetic operator; a quantizer quantizing an output signal of the loop filter to output a digital signal; and a feedback converting the digital signal to output a feedback signal, in which the quantizer includes: a plurality of VCOs each receiving a positive output signal and a negative output signal of the loop filter and outputting VCO signals; a plurality of samplers receiving the VCO signals output from the plurality of VCOs, respectively and outputting sampled signals; and a phase detector detecting a phase difference in the sampled signals output from the plurality of samplers, respectively, to detect a phase difference in two VCO signals output from the plurality of VCOs, respectively.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 19, 2017
    Assignee: Industry University Cooperation Foundation Hanyang University
    Inventors: Changsik Yoo, Donghyeok Jeong, Jinho Noh
  • Patent number: 9696351
    Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: July 4, 2017
    Assignee: STMicroelectronics International N.V.
    Inventors: Daljeet Kumar, Tapas Nandy, Surendra Kumar
  • Patent number: 9559014
    Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: January 31, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang
  • Patent number: 9450568
    Abstract: A bias circuit includes second order process variation compensation in a current source topology having a compensation transistor operating in saturation mode as a current source. An additional compensation transistor is biased to operate in a linear mode to provide an active resistor to vary a control voltage applied to the saturation mode compensation transistor and widen the range of sourced control current, thus widening the achievable range of the control voltage applied to the biasing transistor to produce a predetermined level of bias current despite process variations. The additional compensation transistor has been shown to be able to compensate for another approximately 20-25% of the induced variations leaving less than approximately 10% and preferably less than 5% variation in the bias current from the predetermined level at certain bias conditions and over typical fabrication process variations.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 20, 2016
    Assignee: Raytheon Company
    Inventors: Michael G. Hawkins, David D. Heston
  • Patent number: 9438240
    Abstract: A circuit includes a biasing circuit that includes a load circuit coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the load circuit in response to a transition of the ISO signal between a high voltage and a low voltage. The biasing circuit also includes circuitry to generate an isolation delayed (ISO_DEL) signal. The ISO_DEL signal has a high voltage in response to the biasing signal being within a first threshold level and the ISO_DEL signal has a low voltage in response to the biasing signal being within a second threshold level. The biasing circuit outputs the ISO_DEL signal.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: September 6, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Iulian C. Gradinariu, Jayant Ashokkumar, Bogdan Samson, Vijay Raghavan
  • Patent number: 9367077
    Abstract: A BGR circuit includes a first bipolar transistor and a second bipolar transistor that are connected between a power supply terminal and a ground terminal, each base of the first bipolar transistor and the second bipolar transistor being connected to an output terminal. A first resistor is connected between the ground terminal and the first bipolar transistor. A second resistor and a third resistor are connected in series between the first resistor and the second bipolar transistor. A temperature correction circuit is connected between the ground terminal and a node between the second resistor and the third resistor, and includes a first transistor having a base connected to an end of the first bipolar transistor of the first resistor. The temperature correction circuit further includes a fourth resistor connected in series to the first transistor.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: June 14, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideki Kiuchi
  • Patent number: 9354646
    Abstract: A voltage generator of a contactless integrated circuit (IC) card includes a regulator configured to generate a first internal voltage based on an input voltage and a first reference voltage, the input voltage being received through an antenna of the contactless IC card. The voltage generator includes an internal voltage generator configured to generate a second internal voltage, the second internal voltage being used to operate an internal circuit of the contactless IC card. The voltage generator includes a reference voltage generator configured to generate a second reference voltage based on the first internal voltage, the second reference voltage being generated without regard to a fluctuation component of the first internal voltage. The voltage generator includes a switching unit configured to provide one of the first and second internal voltages as the first reference voltage in response to first and second switching control signals.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: May 31, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Ho Kim, Il-Jong Song, Jong-Pil Cho
  • Patent number: 9350239
    Abstract: A power management system that can include an application processor and a power management unit (PMU). The PMU can generate a regulated output voltage based on control signals generated by a switch control module of the application processor. The control signals can be determined based on a comparison of monitored voltages within the application processor and a generated reference voltage. The reference voltage can be generated based on fed back signals corresponding to the control signals. The application processor and the PMU can be formed utilizing different size manufacturing process technologies. For example, the PMU can be formed utilizing a larger size manufacturing process technology than the application processor.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: May 24, 2016
    Assignee: Broadcom Corporation
    Inventors: Vadim Bishtein, Eric Martin Hayes, Kerry Thompson, Walter Soto, Stephen Douglas Cook
  • Patent number: 9347986
    Abstract: A device for monitoring the latency of electronic circuits based on microtechnology and/or nanotechnology, said circuits to be tested being supplied with the aid of a voltage Vdd, having a low level and a high level, for the detection of delay faults of said circuits, comprises: at least one device of type I placed between the high level of the power supply voltage and the elements of the circuit to be tested, and/or at least one device of type II placed between the low level of the power supply voltage of the elements of the elements of said circuit to be tested, the device of type I and the device of type II comprising at least one low-latency electrical path, said low-latency path being connected in parallel with a high-latency electrical path, a test signal monitoring the opening of the low-latency paths while the high-latency electrical paths are open.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: May 24, 2016
    Assignee: Commissariat A L'Energie et Aux Energies Alternatives
    Inventors: Valentin Gherman, Yannick Bonhomme
  • Patent number: 9350278
    Abstract: A current sensing circuit includes: a first controlled device; a first controlled device; a first current mirror configured to cause a first mirror current to flow through a first load device based on a first control signal received by the first controlled device; a second controlled device; a second current mirror configured to cause a second mirror current to flow through a second load device based on a second control signal received by the second controlled device; and an amplifier configured to output a voltage signal based on the first mirror current flowing through the first load device and the second mirror current flowing through the second load device. The first control signal is substantially proportional to a first drive signal applied to a first controlled remote device, and the second control signal is substantially proportional to a second drive signal applied to of a second controlled remote device.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: May 24, 2016
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard A. Schwab, John R. Agness
  • Patent number: 9329219
    Abstract: A control module includes an input module configured to operate in a normal operating state and a fault diagnosis state. The input module receives an input signal from a circuit module and generates a voltage based on the input signal. In the normal operating state, a fault diagnostic module determines whether the voltage is in a first range or a second range. The first range and the second range indicate that a fault is detected in the circuit module. The fault diagnostic module determines that the detected fault is a first fault type if the voltage is in the first range, transitions the input module from the normal operating state to the fault diagnosis state if the voltage is in the second range, and determines whether the detected fault is a second fault type or a third fault type based on the voltage in the fault diagnosis state.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: May 3, 2016
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Timothy P. Philippart, Steven Zechiel
  • Patent number: 9287276
    Abstract: A semiconductor memory cell array is disclosed that includes a memory cell unit. The memory cell unit includes an active region, a first transistor, a second transistor, a gate structure, and an interconnect. The first transistor and the second transistor are formed on the active region. The gate structure is formed on the active region and between the first transistor and the second transistor. The interconnect connects the gate structure and at least one of sources of the first transistor and the second transistor to a power line.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: March 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shi-Wei Chang, Hong-Chen Cheng, Chien-Chi Tien, Li-Chun Tien, Kuo-Hua Pan, Jhon-Jhy Liaw
  • Patent number: 9280168
    Abstract: A highly distributed current reference for a solid-state memory comprises a centrally located current digital-to-analog converter (IDAC) and a plurality of remotely located tile current references. The IDAC comprises a first active device that generates a reference current, and a device that forms a first source degeneration resistance for the first active device. The IDAC outputs a voltage signal that represents a magnitude of the reference current. A remotely located tile current reference comprises a second active device and a device that forms a second source degeneration resistance for the second active device. The source degeneration resistances and capacitance coupled to the voltage signal output from the IDAC compensate for current, temperature, supply and process variations.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: March 8, 2016
    Assignee: Intel Corporation
    Inventors: Matthew G. Dayley, Yadhu Vamshi S. Vancha
  • Patent number: 9280165
    Abstract: Provided are: a power supply control circuit having a configuration in which an N-channel FET and a P-channel FET can appropriately and selectively be used so as to control power feeding with high efficiency and at low cost; and a power supply control device including the power supply control circuit. An N-channel FET (NchFET in the drawings) and a P-channel FET (PchFET in the drawings) are connected in parallel with each other between the positive voltage side (+B) of a battery (direct current power supply) and a plurality of ECUs (loads) 4, 4, . . . , so as to appropriately control ON and OFF.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: March 8, 2016
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Shigeyuki Fujii
  • Patent number: 9190121
    Abstract: A semiconductor memory device and a method for generating a reference voltage needed for operating the same are disclosed. The semiconductor memory device includes a first decoder configured to generate a default set signal in response to a reset signal and a clock enable signal, a second decoder configured to generate a reference voltage set signal in response, and a reference voltage provider configured to generate an internal reference voltage.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: November 17, 2015
    Assignee: SK Hynix Inc.
    Inventor: Dong Kyun Kim
  • Patent number: 9176513
    Abstract: The high dynamic range exponential current generator produces an output waveform (current/voltage) which is an exponential function of the input waveform (current/voltage). The exponential characteristics are obtained in BiCMOS or Bipolar technologies using the intrinsic characteristics (IC/VBE) of the bipolar transistors. The high dynamic range exponential current generator is biased in weak inversion region. MOSFETs biased in weak inversion region are used not to utilize the inherent exponential (IDS/VGS) relationship but to simply implement x2 and x4 terms using translinear loops. The term x4 is realized by two cascaded squaring units. The approximation equation used is ? x ? 0.025 + ( 1 + 0.125 ? x ) 4 0.025 + ( 1 - 0.125 ? x ) 4 .
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: November 3, 2015
    Assignee: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS
    Inventors: Munir A. Al-Absi, Karama M. Al-Tamimi
  • Patent number: 9170596
    Abstract: An integrated circuit includes a first circuit. The first circuit includes a first transistor having a first dopant type. The first circuit further includes a first cascode transistor having the first dopant type, wherein the first cascode transistor connected in series with the first transistor. The first circuit further includes a second transistor having a second dopant type opposite to the first dopant type, wherein the second transistor is connected in series with the first transistor. The first circuit includes a second cascode transistor having the second dopant type, wherein the second cascode transistor is connected in series with the second transistor. The integrated circuit further includes a first bias circuit configured to adjust a threshold voltage of at least one of the first cascode transistor or the second cascode transistor.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: October 27, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Yvonne Lin
  • Patent number: 9136831
    Abstract: According to the invention, there is provided a frequency to voltage converter for generating an output voltage proportional to the frequency of input signal. It comprises a switched capacitor circuit for receiving input signal and generating an input current proportional to said frequency, the switched capacitor having a capacitor charging and discharging at said frequency; an operational transconductance amplifier (OTA) for receiving at least one control voltage representative of the input current and generating current proportional to the at least one control voltage; at least one negative feedback circuit connecting input and output of the OTA, each negative feedback circuit comprising: a control transistor coupled to a node of the OTA; a diode connected transistor coupled to the control transistor for sensing current flowing through the control transistor; and a feedback transistor coupled to another node of the OTA.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: September 15, 2015
    Assignee: INDIA INSTITUTE OF TECHNOLOGY, BOMBAY
    Inventors: Gowdhaman Santosh Kumar, Shojaei Baghini Maryam, Anavangot Vineeth, Mukherjee Jayanta
  • Patent number: 9134782
    Abstract: Power supply voltage to an integrated circuit (IC) or a portion of an IC is maintained at an optimum level matching the IC performance. Voltage ranges and delay measures for corresponding operating frequencies are stored in tables in a voltage control block. When a new frequency of operation is desired, the voltage control block measures delay performance of the IC, and sets the supply voltage to a value specified in a corresponding entry in a table. The voltage control block then continues to measure delay performance, and dynamically adjusts the power supply voltage to an optimum value thereby minimizing power consumption.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: September 15, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Sreenivas Aerra Reddy, Srinivasan Arulanandam, Venkataraman Rajaraman
  • Patent number: 9077336
    Abstract: A transistor control circuit includes: an electrode control circuit configured to apply a positive potential to a control electrode in a transistor that includes the control electrode between a gate and a drain.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: July 7, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Tadahiro Imada
  • Publication number: 20150137881
    Abstract: A pull-up resistor circuit is provided for an IC, including a voltage source, a voltage output for providing a first voltage to supply power for providing a second voltage for an input/output (I/O) port of the IC, a first PMOS transistor, a second PMOS transistor and a control signal generator. The first PMOS transistor and the second PMOS transistor are connected in series to provide pull-up resistance, where the first PMOS transistor is coupled to a first control signal to control a pull-up function of the pull-up resistor circuit in a normal mode. Further, the control signal generator is for generating a second control signal coupled to the second PMOS transistor to control a bias voltage of the pull-up resistor circuit to prevent a reverse current from the voltage output to the voltage source under a high-voltage-tolerant mode when the second voltage is higher than the first voltage.
    Type: Application
    Filed: November 19, 2014
    Publication date: May 21, 2015
    Inventors: KAI ZHU, JIE CHEN, WENJUN WENG, SHANYUE MO, ZHIGUANG GUO
  • Patent number: 9024681
    Abstract: A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal; and a resistor having (i) a first end connected to the output terminal and (ii) a second end connected to a second power source. This arrangement allows the signal processing circuit to maintain an output potential even after a bootstrap effect has worn off.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: May 5, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuhichiroh Murakami, Yasushi Sasaki, Etsuo Yamamoto
  • Patent number: 9019005
    Abstract: In various embodiments, a circuit is provided including a supply terminal, a logic circuit, an inverter and a control transistor which may include a body region, first and second source/drain regions, a gate insulating region having a layer thickness and a gate region. The first source/drain region may be coupled to the supply terminal. The logic circuit may have an internal supply terminal connected to the second source/drain region of the control transistor and a plurality of transistors each having a gate insulating region having a second layer thickness. The inverter input may be coupled to the internal supply terminal of the logic circuit and the output to the gate region of the control transistor. The inverter may include a transistor with a gate insulating region having a third layer thickness substantially equal to the first and second layer thicknesses.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: April 28, 2015
    Assignee: Infineon Technologies AG
    Inventor: Martin Feldtkeller
  • Publication number: 20150097615
    Abstract: Manufacturing a DC-DC converter on a chip includes: providing a die having a p-type top side and an n-type bottom side; removing an interior portion, creating a hole; flipping the interior portion; inserting the interior portion into the hole; fabricating high-side switch cells in the interior portion's top side and low-side switch cells in the exterior portion's top side; sputtering a magnetic material on the entire top side; burrowing tunnels into the magnetic material; and applying conductive material on the magnetic material and within the tunnels, electrically coupling pairs of high-side and low-side switches, with each pair forming a micro-power-switching phase, where the conductive material forms an output node of the phase, and the conductive material in the burrowed tunnels forms, in each phase, a torodial inductor with a single loop coil and, for the plurality of phases, a directly coupled inductor.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 9, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jamaica L. Barnette
  • Patent number: 9000857
    Abstract: A circuit generates a compensation signal that can remove noise in a VCO introduced by a supply signal (i.e., supply-side noise). The circuit includes two transistors connected in series. A resistor is connected between the gate of the first transistor and the supply signal, and a capacitor is connected between the gate of the second transistor and the supply signal. The circuit is designed so that the transconductance of one transistor is greater than or equal to twice the transconductance of a second transistor. The compensation signal is supplied through a capacitor, which compensates for capacitors in a VCO, to an internal supply node of the VCO. At the internal supply node, the compensation signal removes (or greatly reduces) the noise introduced by the supply signal noise, resulting in a less-noisy output signal from the VCO.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics International N.V.
    Inventors: Abhirup Lahiri, Nitin Gupta
  • Patent number: 8994448
    Abstract: Systems and methods for generating internal chip supply bias from high voltage control line inputs are presented. One of a plurality of the high voltage control lines is selected and accordingly internal path switching circuitry is enabled to pass the selected high voltage control line while protecting the associated components from over-stress.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: March 31, 2015
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Fleming Lam
  • Publication number: 20150084538
    Abstract: Provided is an apparatus and method for electrical stability compensation. The apparatus includes a drive transistor connecting a power supply to a load, a first variable capacitor having a gate and a source, and a switch transistor for controlling a connection between a programming signal source and a gate of the drive transistor. The gate of the first variable capacitor is connected to the gate of the drive transistor. The first variable capacitor is configured to draw a charge from the gate of the drive transistor during a driving phase for the load.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Inventors: Maofeng YANG, Nikolas PAPADOPOULOS, William WONG, Manoj SACHDEV
  • Patent number: 8987937
    Abstract: To include an internal voltage generating circuit that includes a capacitor having a first electrode and a second electrode and generates an internal voltage by repeating a charge operation for charging the capacitor to a VDD level and a discharge operation for applying the VDD level to the first electrode of the capacitor to generate a voltage of two times the VDD level on the second electrode, and a control circuit that performs a control to apply a voltage that is lower than the VDD level to the capacitor when the internal voltage generating circuit is in a standby state. According to the present invention, when the internal voltage generating circuit is in a standby state, because a voltage applied to both ends of the capacitor is reduced, it is possible to reduce the power consumption due to a leakage current.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: March 24, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Koichiro Hayashi
  • Patent number: 8988143
    Abstract: A switchable current source in which a reference voltage value to be used in driving the gate of an output transistor is sampled and stored. The reference voltage is derived using a reference current source which feeds a current sensing transistor. The current sensing transistor is turned off when the output transistor is turned off, so that the reference current source then does not consume power. A large reference current Iref can then be used for a short time.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: March 24, 2015
    Assignee: NXP B.V.
    Inventor: Marco Berkhout
  • Patent number: 8981833
    Abstract: Low-power circuits for providing stable voltage and current references rely on currents flowing through ultra-thin dielectric layer components for operation. A current reference circuit includes driving circuitry operative to apply a voltage to the first terminal of the component with respect to the second terminal of the component in order to cause a current to flow through the dielectric layer, and sources a reference output current that is based on the current flow through the dielectric layer in response to the applied voltage. A voltage reference circuit includes a current source which applies a current to the ultra-thin dielectric layer component, and maintains an output node at a stable reference output voltage level based on the voltage across the ultra-thin dielectric layer component in response to the current flow through the dielectric layer.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: March 17, 2015
    Assignee: Dust Networks, Inc
    Inventors: Mark Alan Lemkin, Thor Nelson Juneau
  • Publication number: 20150070085
    Abstract: A pass device configured from a common gate transistor, wherein an input voltage is applied to the source and an output at the drain is applied to a load. The input resistance of the pass device increases as the input voltage is reduced and limits the useful range of the input voltage. Increasing the gate to source voltage (Vgs) by applying a negative voltage to the gate reduces the input resistance and increases the range of operation of the pass device.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 12, 2015
    Applicant: Dialog Semiconductor GmbH
    Inventors: Julian Tyrrell, Ambreesh Bhattad
  • Patent number: 8963626
    Abstract: In various embodiments, a circuit is provided including a supply terminal, a logic circuit, an inverter and a control transistor which may include a body region, first and second source/drain regions, a gate insulating region having a layer thickness and a gate region. The first source/drain region may be coupled to the supply terminal. The logic circuit may have an internal supply terminal connected to the second source/drain region of the control transistor and a plurality of transistors each having a gate insulating region having a second layer thickness. The inverter input may be coupled to the internal supply terminal of the logic circuit and the output to the gate region of the control transistor. The inverter may include a transistor with a gate insulating region having a third layer thickness substantially equal to the first and second layer thicknesses.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: February 24, 2015
    Assignee: Infineon Technologies AG
    Inventor: Martin Feldtkeller
  • Publication number: 20150042401
    Abstract: An input receiver includes a first pass transistor coupled between an input pad and an internal receiver node. The first pass transistor includes a controlled floating gate capacitively coupled to the input pad. A source follower transistor couples between the internal receiver node and a power supply. A gate for the source follower transistor couples to the input pad.
    Type: Application
    Filed: August 8, 2013
    Publication date: February 12, 2015
    Applicant: QUALCOMM INCORPORATED
    Inventors: Stephen Knol, Michael Brunolli, Chiew-Guan Tan, Damen Redelings
  • Publication number: 20150035591
    Abstract: A low-noise reference voltages distribution circuit (10) is disclosed, comprising a multi-output voltage to current converter (V/I_Conv) adapted to receive an input reference voltage (VR) for providing a plurality of output reference currents (I1, . . . , IN) to be converted into a plurality of local reference voltages (V01, V0N) at corresponding receiving circuits (LCR1, LCRN) adapted to be connected to said reference voltages distribution circuit (10). The multi-output voltage to current converter (V/I_Conv) comprises: -an input section (20) adapted to generate on the basis of said input reference voltage (VR) a reference current (I0), the input section (20) comprising a current mirror input transistor (M0E) having a voltage controlled input terminal (g0E); -an output section (50) comprising a plurality of current mirror output transistors (M01, M0N) each adapted to provide a corresponding output reference current of said plurality of reference currents (I1, . . .
    Type: Application
    Filed: February 26, 2013
    Publication date: February 5, 2015
    Inventors: Germano Nicollini, Andrea Barbieri
  • Patent number: 8947159
    Abstract: Provided is a reference voltage generation circuit that has a flat temperature characteristic even when there are fluctuations in manufacturing step. After a semiconductor manufacturing process is finished, electrical characteristics of a semiconductor device are evaluated. Temperature characteristic of each reference voltage (VREF) of three unit reference voltage generation circuits (10) is evaluated. Then only a unit reference voltage generation circuit (10) having the most flat temperature characteristics is selected from among the three unit reference voltage generation circuits (10). Only fuses (13, 14) of the selected unit reference voltage generation circuit (10) are not cut, but other fuses (13, 14) are cut. Accordingly only the selected unit reference voltage generation circuit (10) operates, and the other unit reference voltage generation circuits (10) do not operate.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: February 3, 2015
    Assignee: Seiko Instruments Inc.
    Inventor: Hideo Yoshino
  • Publication number: 20150028943
    Abstract: Traditionally, designs have been very conservative on power grid design using higher margins than those needed for safe operation. This is especially true for process driver designs which may not have enough data on process characteristics. This invention allows us to recoup these inefficiencies and to speed up the power up/power down dynamically. This invention sequences plural power supply switches serially or in plural parallel sets as set by a wake up mode.
    Type: Application
    Filed: July 29, 2014
    Publication date: January 29, 2015
    Inventors: Sureshkumar Govindaraj, Jose L. Flores
  • Patent number: 8941437
    Abstract: A bias circuit includes: a reference current generation circuit that has a first reference-current element disposed in a first current path and has a second reference-current element disposed in a second current path; a first current mirror circuit that has a first transistor connected in series with the first reference-current element and has a second transistor connected in series with the second reference-current element; a third reference-current element disposed in a third current path disposed between the power supply terminal and the reference-current element; a third transistor connected in series with the third reference-current element; a bypass capacitor connected between the power supply terminal and a second node connected to a control terminal of the third transistor; an activation circuit connected to the first node; and a first switch connected between the first node and the second node.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: January 27, 2015
    Assignee: Fujitsu Limited
    Inventor: Hiroyuki Nakamoto
  • Patent number: RE46107
    Abstract: An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Steven Swei, Chih-Chang Lin, Tien-Chun Yang, Chan-Hong Chern, Ming-Chieh Huang