Abstract: One embodiment of an integrated circuit includes a local circuit block, a first power supply for supplying power to a first terminal of the local circuit block, a second power supply for supplying power to a second terminal of the local circuit block, a first transmission gate coupled between the second terminal of the local circuit block and a current path from the second power supply, and a second transmission gate coupled between the current path from the second power supply and a gate of a p-type metal-oxide-semiconductor (PMOS) transistor in the first transmission gate, the second transmission gate including a single transistor.

Abstract: A MOS transistor generates an output current based on a voltage induced across a drain and a source thereof. A gate bias voltage generator circuit generates a gate bias voltage so as to operate the MOS transistor in a strong-inversion linear region, and applies the gate bias voltage to a gate of the MOS transistor. A drain bias voltage generator circuit generates a drain bias voltage, and applies the drain bias voltage to the drain of the MOS transistor. An added bias voltage generator circuit generates an added bias voltage, which has a predetermined temperature coefficient and includes a predetermined offset voltage, so that the output current becomes constant against temperature changes. The drain bias voltage generator circuit adds the added bias voltage to the drain bias voltage, and applies a voltage of the adding results to the drain of the MOS transistor as the drain bias voltage.

Abstract: Disclosed is a bias circuit which includes a bias voltage generating part configured to generate a bias voltage using a reference current and a variable current; a reference current source part configured to provide the reference current to the bias voltage generating part; and a current adjusting part configured to provide the variable current to the bias voltage generating part and to adjust the amount of the variable current according to voltage levels of at least two input signals. The bias circuit prevents an increase in power consumption and improves a slew rate at the same time.

Abstract: A semiconductor integrated circuit is provided. First and second voltage generation units generate a first voltage and a second voltage with respect to a temperature rise, respectively. First and second current generation units generate a first current and a second current having a negative characteristic with respect to a temperature rise in response to a voltage comparison signal, respectively. A voltage comparison unit compares a voltage level of a first current transfer node with a voltage level of a second current transfer node and generates the voltage comparison signal according to the comparison result. A reference voltage output unit is connected in series to the second voltage generation unit and outputs a reference voltage maintaining a set level, without regard to a temperature variation, in proportion to a third current generated in response to the voltage comparison signal.

Abstract: A circuit includes a gate node, and a bias circuit coupled to the gate node. The bias circuit is configured to, in response to a change in a gate voltage on the gate node, provide a positive feedback to the gate voltage. A power circuit is coupled to the gate node, wherein the power circuit includes a power Metal-Oxide-Semiconductor (MOS) transistor. The power circuit is configured to, in response to a change in the gate voltage, provide a negative feedback to the gate voltage. An output node is coupled to the power circuit.

Abstract: A system and method for voltage controlled oscillator (VCO) biasing in low voltage circuits including low resistance elements that are especially susceptible to noise. In one embodiment, a poly resistor and triode resistor is used to cancel or offset the effects that temperature variations have on the circuit. The triode resistor is powered by a voltage source that uses a pair of diodes coupled to a constant transconductance (gm) circuit to generate a reduced noise voltage that is independent of the power supply noise. The size of the triode resistor and poly resistors can be varied.

Abstract: A voltage divider circuit generating a divided voltage by dividing an input voltage with a predetermined voltage division ratio, and outputting the divided voltage is disclosed. The voltage divider circuit includes a first resistor circuit including multiple resistors connected in series, the resistors being connected in parallel to corresponding fuses; and a second resistor circuit including multiple resistors connected in series, the resistors being connected in parallel to corresponding fuses, the second resistor circuit being connected in series to the first resistor circuit. The divided voltage is output from the connection of the first resistor circuit and the second resistor circuit, and the fuses of the first resistor circuit and the second resistor circuit are subjected to trimming so that the combined resistance of the first resistor circuit and the second resistor circuit is constant.

Abstract: A voltage regulator includes a driver transistor, a feedback voltage generator, a reference voltage generator, a first differential amplifier, and a differential gain controller. The driver transistor is connected between input and output terminals to conduct a current therethrough according to a control signal applied to a gate terminal thereof. The feedback voltage generator is connected to the output terminal to generate a feedback voltage. The reference voltage generator generates a reference voltage. The first differential amplifier has an output thereof connected to the gate terminal of the driver transistor, and a pair of differential inputs thereof connected to the feedback voltage generator and the reference voltage generator, respectively, to generate the control signal at the output thereof. The differential gain controller is connected to the output of the first differential amplifier to control the differential gain according to a difference between the input and output voltages.

Abstract: In a constant current circuit, a drain terminal is connected to an output terminal of a current, and a gate voltage operable in a saturation region is applied to a source-grounded transistor. An increase current generating circuit generates an increase current equivalent to an increase of a current due to a channel length modulation effect of the transistor. A current mirror circuit generates a current having the same value as that of the increase current generated by the increase current generating circuit and supplies the generated current to the drain terminal of the transistor.

Abstract: A charging circuit includes a first current mirror including a first branch circuit, a second branch circuit and a third branch circuit for generating a first conduction current, a second conduction current and a third conduction current according to the input voltage, a second current mirror including a fourth branch circuit coupled to the first branch circuit and including a first channel width, and a fifth branch circuit coupled to the second branch circuit and including a second channel width, wherein a load circuit is coupled between the first current mirror and the second current mirror, and the first current mirror as well as the second current mirror correspondingly adjust values of the first conduction current, the second conduction current and the third conduction current according to the first channel width as well as the second channel width, so as to process a charging operation of the load circuit.

Abstract: A power transistor module including a power transistor with a first common power node, and a split control node. A first clip is connected to a portion of a second power node so that current through a first control segment of the control node is directed through a first transistor portion and through the first clip. A second clip is connected to another portion of the second power node so that current through a second control segment is directed through a second transistor portion and through the second clip. A ratio of an area of the first transistor portion to a combined area of the first and second portions is 5 percent to 75 percent. A shunt is coupled in series to the first clip. The shunt may be directly electrically connected to the first portion of the power transistor.

Abstract: A semiconductor device in accordance with an aspect of the present invention includes first and second power-supply circuits each of which generates an internal power-supply voltage by converting a voltage value of a power-supply voltage into a different voltage value, a first internal circuit that receives a supply of the internal power-supply voltage from the first power-supply circuit through a first line, a second internal circuit that receives a supply of the internal power-supply voltage from the second power-supply circuit through a second line, an inter-block line that connects the first and second lines to each other, and a control circuit that operates the first and second internal circuits in a predetermined operating cycle, and controls a length of a period during which the first and second internal circuits operate simultaneously.

Abstract: A substrate bias control circuit includes a process voltage temperature (PVT) effect transducer that responds to a PVT effect. A PVT effect quantifier is coupled to the PVT effect transducer. The PVT effect quantifier quantifies the PVT effect to provide an output. The PVT effect quantifier includes at least one counter and a period generator. The period generator provides a time period for the counter. A bias controller that is coupled to PVT effect quantifier is configured to receive the output of the PVT effect quantifier. The bias controller is configured to provide a bias voltage. The bias controller includes a bias voltage comparator.

Abstract: A constant current circuit includes a depletion type MOS transistor, a first current mirror circuit, and a second current mirror circuit. The first and second current mirror circuits each include first and second MOS transistors where a gate of the first and second MOS transistors is connected to a drain of the first MOS transistor. A third MOS transistor has a gate connected to one terminal of a resistor and to the drain of the first MOS transistor of the first current mirror circuit, a source connected to a ground terminal, and a drain connected to an output terminal of the second current mirror circuit.

Abstract: A linear voltage regulator includes a pair of amplifiers. A first amplifier of the pair is used in conventional fashion to generate a regulated output voltage by controlling an impedance of a pass transistor in the linear voltage regulator, the controlling being based on a difference between a reference voltage and a voltage at a first node in a voltage divider network connected between the output terminal of the voltage regulator and a ground terminal. The second amplifier of the pair compares the regulated output voltage and a voltage at a second node in the voltage divider network, and injects a proportional current into the first node. Generation of a regulated output voltage lesser than the reference voltage is thereby enabled.

Abstract: A system for uniform power regulation of an integrated circuit is disclosed. In each of a plurality of regions, the system includes a comparison circuit having a first input coupled to receive a reference voltage and a second input coupled to receive a feedback voltage. The comparison circuit provides a gating voltage to a driver circuit that is coupled to a first supply voltage. The driver circuit is configured to provide a regulated voltage responsive to the gating voltage. A feedback adjustment circuit is configured to trim the regulated voltage by a region-specific trim value and output the trimmed regulated voltage as the feedback voltage on the output.

Abstract: A current mirror arrangement comprises a switchable, adjustable current source (Q1, Q2) for providing an impression current (IP), a current mirror (SP) having an input (E) for feeding in an impression current (IP) and an output (A) for providing a current (I), and a step-up generator (AG) coupled to the current mirror (SP) such that the current (I) is switched on with an adjustable slew rate. In addition, a method for switching on a current is provided.

Abstract: A current-source circuit includes a plurality of input-side transistors; a plurality of output-side transistors current-mirror-coupled to the plurality of input-side transistors; an output terminal from which an output current is output; and a switching control circuit to switch the plurality of input-side transistors and activate at least one of the plurality of input-side transistors sequentially.

Abstract: A linear voltage regulator includes a pair of amplifiers. A first amplifier of the pair is used in conventional fashion to generate a regulated output voltage by controlling an impedance of a pass transistor in the linear voltage regulator, the controlling being based on a difference between a reference voltage and a voltage at a first node in a voltage divider network connected between the output terminal of the voltage regulator and a ground terminal. The second amplifier of the pair compares the regulated output voltage and a voltage at a second node in the voltage divider network, and injects a proportional current into the first node. Generation of a regulated output voltage lesser than the reference voltage is thereby enabled.

Abstract: An internal voltage generating circuit includes a drive signal generating unit, a drive signal controlling unit, and a driving unit. The drive signal generating unit is configured to compare an internal voltage with first and second reference voltages and generate a first pull-up drive signal and a first pull-down drive signal. The drive signal controlling unit is configured to buffer the first pull-up drive signal and the first pull-down drive signal and generate a second pull-up drive signal and a second pull-down drive signal, wherein the second pull-up drive signal and the second pull-down drive signal are deactivated when the first pull-up drive signal and the first pull-down drive signal are activated. The driving unit is configured to drive the internal voltage in response to the second pull-up drive signal and the second pull-down drive signal.

Abstract: The LDO has at least three stages supplied by a supply voltage. A first stage has a differential amplifier and a folded cascode device with a regulated current mirror. The LDO has two nodes that are configured to couple the differential amplifier and the regulated current mirror and to receive a differential signal, respectively. The regulated current mirror is configured to convert and amplify the differential signals to a single ended signal. Said LDO has a first capacitor configured for frequency compensation, said first capacitor coupled between said first stage and a second stage. The LDO has a second capacitor for balancing capacitive loading of a first cascode circuit, said second capacitor coupled between said first stage and said supply voltage. Said first cascode circuit is configured to suppress different voltages between input and output of the capacitors caused of a modulation of said supply voltage.

Abstract: Implementations to mitigating side effects of impedance transformation circuits are described. In particular, mitigation circuitry may be coupled to a high impedance circuit to minimize or eliminate non-linear output of the high impedance circuit in order to provide a well-defined bias voltage to the input of a buffer or amplifier device coupled to a capacitive sensor. Additionally, the mitigation circuitry may be coupled to the high impedance circuit to reduce or eliminate rectifying effects of the high impedance circuit. Accordingly, a bias voltage can be utilized to provide a stable operating point of the buffer or amplifier device via a high impedance circuit utilizing one or more impedance transformations.

Abstract: In one implementation, an apparatus may include a first negative channel metal oxide semiconductor (NMOS) transistor circuit coupled to a first voltage source, a second NMOS transistor circuit coupled to the first voltage source, the second NMOS transistor circuit having a smaller channel width to channel length ratio than the first NMOS transistor circuit, a first positive channel metal oxide semiconductor (PMOS) transistor circuit coupled to a second voltage source and coupled to the second NMOS transistor circuit, and a second PMOS transistor circuit coupled to the second voltage source, the second PMOS transistor circuit having a larger channel width to channel length ratio than the first PMOS transistor circuit.

Abstract: A device includes a first internal voltage generation circuit generating a first internal voltage in response to an external power supply voltage, a second internal voltage generation circuit generating a second internal voltage in response to the external power supply voltage, the second internal voltage being different in voltage level from the first internal voltage, and a preset signal generation circuit responding to a power-on of the external power supply voltage to the device and generating, independently of the first internal voltage, first and second preset signals that bring the first and the second internal voltage generation circuits into respective initial states, the preset signal generating circuit stopping generation of the first preset signal when the external power supply voltage reaches a first voltage level and stopping generation of the second preset signal when the external power supply voltage reaches a second voltage level different from the first voltage level.

Abstract: Back-gate voltage control provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in logic circuits having a small load in logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to a gate input signal.

Abstract: A voltage switching circuitry comprises a switching arrangement with a given number N of switches in series between a first terminal receiving a first voltage and a second terminal receiving a second voltage. The first voltage level is higher than the second voltage level, and N is at least equal to 2. A voltage-by-N divider, having N?1 output taps, is arranged to divide the first voltage by N to a scaled down version of the first voltage having a voltage level below voltage max ratings of the switches. The N?1 output taps of the divider are arranged to respectively output N?1 third voltages having respective levels staged below the first voltage level. N?1 max voltage generators generate N?1 fourth voltages, respectively equal to the maximum of the second voltage and of each of the N?1 third voltages. A switch control unit generates N control signals using the N?1 fourth voltages. These N control signals have respective voltage levels staged between the first voltage level and the second voltage level.

Abstract: A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal; and a resistor having (i) a first end connected to the output terminal and (ii) a second end connected to a second power source. This arrangement allows the signal processing circuit to maintain an output potential even after a bootstrap effect has worn off.

Abstract: Devices and circuits for voltage reference architectures that can increase the PSRR parameter by improving the saturation margin for an output transistor. For example, a device can include a current source coupled between a first power supply line and a circuit node, a voltage production circuit coupled between the circuit node and a second power supply line to produce a plurality of voltages respectively at voltage nodes thereof, a multiplexer coupled to the voltage nodes of the voltage production circuit and the output node and configured to select and output one of the voltages to the output node, and a control circuit configured to supply the one of the voltages to the circuit node.

Abstract: In a current switch, a bias generation circuit electrically connected to a high voltage power supply generates a bias current. The bias current is mirrored by a current mirror containing a first plurality of transistors to a first one of a second plurality of transistors. The first one of the second plurality of transistors amplifies the mirrored bias current and transmits the amplified bias current to a second one of the second plurality of transistors. The second one of the second plurality of transistors sinks the amplified bias current into a node shared by an internal reference voltage, thereby putting the node in a first logic state. A third one of the second plurality of transistors receives the amplified bias current from the second one of the second plurality of transistors and sinks the amplified bias current into a node shared by a gate of a high voltage p-type transistor, thereby putting the node in the first logic state.

Abstract: Provided is a constant current circuit and a reference voltage circuit with improved line regulation without needing a start-up circuit. The constant current circuit includes: a constant current generation circuit including NMOS transistors and a resistor; a current mirror circuit including a pair of depletion mode NMOS transistors, for allowing a current of the constant current generation circuit to flow; and a feedback circuit for maintaining constant voltages of source terminals of the pair of depletion mode NMOS transistors.

Abstract: A reference voltage generation circuit for a semiconductor integrated circuit includes a first reference voltage generation unit configured to generate a reference voltage in mode other than a self-refresh mode, and a second reference voltage generation unit configured to additionally drive an output terminal of the first reference voltage generation unit in an initial reference voltage setting period.

Abstract: A semiconductor device includes an internal voltage input buffer configured to determine voltage levels of a pull-up driving node and a pull-down driving node as a result of a comparison between a voltage level of an internal voltage node and a voltage level of a reference voltage node such that the pull-up driving node and the pull-down driving node to maintain a voltage level difference, and an internal voltage driving block configured to pull-up drive the internal voltage node in response to the voltage level of the pull-up driving node and pull-down drive the internal voltage node in response to the voltage level of the pull-down driving node.

Abstract: According to an aspect of the invention, a reference signal generating circuit includes a band gap reference main unit that includes a first cascode current mirror unit having a plurality of first conductive-type transistors; a second cascode current mirror unit having a plurality of second conductive-type transistors; a reference unit that uses a band gap to generate a reference signal; a first bias voltage generating unit that generates a bias voltage of the second cascode current mirror unit; a second bias voltage generating unit that generates a bias voltage of the first cascode current mirror unit; and an output unit that generates a reference signal based upon an output of the band gap reference main unit to generate and outputs the reference signal, wherein the second cascode current mirror unit is connected between the first cascode current mirror unit and the reference unit.

Abstract: In one embodiment, a current mirror circuit includes first to fourth insulated gate field effect transistors (FETs), and a bias circuit. The gate electrodes of the first and second FETs are connected to each other. The source electrode of the third FET is connected to the drain electrode of the first FET, and the drain electrode of the third FET is connected to the gate electrodes of the first and second FETs and a current input terminal. The gate electrode of the fourth FET is connected to the gate electrode of the third FET, the source electrode of the fourth FET is connected to the drain electrode of the second FET, and the drain electrode of the fourth FET becomes a current output terminal. The bias circuit is configured to provide a bias voltage to the gate electrodes of the third and fourth FETs.

Abstract: A switched capacitor type D/A converter receives m-bit (m represents an integer) input data, and outputs an analog signal that corresponds to the input data value. Switch circuits are provided to respective bits of the input data, and are classified into two groups: a first group configured to turn on when the corresponding input data bit is 1, and to turn off when the corresponding input data bit is 0; and a second group configured to turn on when the corresponding input data bit is 0, and to turn off when the corresponding input data bit is 1. Each switch of the first and second switch groups is configured as a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The ground voltage 0 V is applied to the lower power supply terminal of each of the first and second inverters configured to supply a gate signal to each switch.

Abstract: Provided is a power supply integrated circuit including an overheat protection circuit with high detection accuracy. The overheat protection circuit includes: a current generation circuit including: a first metal oxide semiconductor (MOS) transistor including a gate terminal and a drain terminal that are connected to each other, the first MOS transistor operating in a weak inversion region; a second MOS transistor including a gate terminal connected to the gate terminal of the first MOS transistor, the second MOS transistor having the same conductivity type as the first MOS transistor and operating in a weak inversion region; and a first resistive element connected to a source terminal of the second MOS transistor; and a comparator for comparing a reference voltage having positive temperature characteristics and a temperature voltage having negative temperature characteristics, which are obtained based on a current generated by the current generation circuit.

Abstract: A constant voltage circuit is disclosed that includes an output control transistor and an overcurrent protection circuit. The overcurrent protection circuit includes a proportional current generation circuit part, a current division circuit part, a division ratio control circuit part, a current-voltage conversion circuit part, and an output current control circuit part. When the output voltage of the current-voltage conversion circuit part reaches a predetermined voltage, the output current control circuit part prevents an increase in the output current of the output control transistor so as to reduce a voltage output from an output terminal. When the voltage output from the output terminal is reduced to a predetermined limit voltage, the division ratio control circuit part changes the division ratio of the current division circuit part so that a current supplied to the current-voltage conversion circuit part increases so as to reduce the output current of the output control transistor.

Abstract: A reference current generating circuit has: first and second current mirror circuits and first and second output terminals. The first current mirror circuit has: a first transistor of a first polarity being an input-side transistor; and a first resistor connected between a gate of the first transistor and a power supply terminal. The second current mirror circuit has a second transistor of a second polarity being an input-side transistor. An output node of the first current mirror circuit is connected to an input node of the second current mirror circuit, and an input node of the first current mirror circuit is connected to an output node of the second current mirror circuit. A control voltage applied to the gate of the first transistor is output from the first output terminal. A control voltage applied to a gate of the second transistor is output from the second output terminal.

Abstract: A power source arrangement comprises a controlled and clocked operated power source, that power source providing an output voltage out of a plurality of output voltages in response to a first multiplication factor. One or more regulated current sources are connected to the controlled and clocked operated power source to provide an output current to respective loads. Each of the one or more regulated current sources is adapted to provide a first indication signal upon a regulated operation of the respective current source. The power source arrangement further comprises a dummy power source as well as a dummy current source connected to the dummy power source. The dummy current source receives a load signal corresponding to a voltage drop over the loads connected to the one or more regulated current sources and provides a second indication signal in response thereto.

Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.

Abstract: A semiconductor device has an analog switch, in which a P channel transistor and an N channel transistor are connected in parallel between an input terminal and an output terminal; a variable voltage circuit, which variably generates, according to an input voltage applied to the input terminal, potentials of a first gate voltage and first back gate voltage of the P channel transistor and of a second gate voltage and second back gate voltage of the N channel transistor; and a control circuit, which supplies to the variable voltage circuit a control signal controlling the analog switch to be conducting or non-conducting. In response to the control signal causing the analog switch to be conducting, the variable voltage circuit outputs the variable-generated first gate voltage and second gate voltage to the respective gates of the P channel transistor and N channel transistor.

Abstract: An output current detecting circuit includes: a current detecting transistor having a size smaller than that of an output transistor and a control terminal, to which a voltage same as a control voltage of the output transistor is applied; a sensing resistor connected to the current detecting transistor in a serial mode; a comparison circuit comparing a voltage converted by the sensing resistor and a reference voltage to judge a magnitude of a current flowing through the output transistor; and a reference voltage generating circuit, wherein the reference voltage generating circuit includes a constant current circuit flowing a constant current and a resistance element having one terminal connected to a power source voltage terminal, the reference voltage generating circuit generating the reference voltage based on a power source voltage by the conversion of the constant current into a voltage by flowing the constant current through the resistance element.

Abstract: A method and apparatus is disclosed to compensate for gate leakage currents of thin oxide devices that have very thin oxide layers in a current mirror of a digital-to-analog converter (DAC). The DAC converts a digital input signal from a digital representation in a digital signaling domain to an analog representation in an analog signaling domain to provide an analog output signal. The DAC uses one or more transistors to convert the digital input signal from the digital representation to the analog representation. These transistors are typically implemented using thin oxide devices that have very thin oxide layers and corresponding gate leakage currents that are associated with these very thin oxide layers. The current-steering DAC provides these gate leakage currents independent of its corresponding reference source without any substantial affect upon its full scale output.

Abstract: A current source circuit includes a reference current source circuit; a reference voltage source circuit generating a voltage proportional to a thermal voltage based on the reference current; a first transistor connected between the reference voltage source circuit and the second power supply voltage and through which a first current flows; a second transistor which has a gate applied with a voltage as a result of addition of the voltage generated by the reference voltage source circuit and a voltage between a source and a drain of the first transistor and through which a second current flows; a current source supplying a third current of a current value proportional to that of the first current; and a third transistor through which a difference current between the second current and the third current flows. An output current is supplied based on the difference current.

Abstract: Devices and circuits for voltage reference architectures that can increase the PSRR parameter by improving the saturation margin for an output transistor. For example, a device can include a current source coupled between a first power supply line and a circuit node, a voltage production circuit coupled between the circuit node and a second power supply line to produce a plurality of voltages respectively at voltage nodes thereof, a multiplexer coupled to the voltage nodes of the voltage production circuit and the output node and configured to select and output one of the voltages to the output node, and a control circuit configured to supply the one of the voltages to the circuit node.

Abstract: A dynamic biasing circuit includes a first input pair coupled to a second input pair, the first input pair including a first transistor and a second transistor with sources coupled to each other, and the second input pair comprising a third transistor and a fourth transistor with sources coupled to each other, the sources receiving a bias current. A first current mirror that generates an output current is coupled to the first input pair. A second current mirror is coupled to the first input pair and the second input pair. The second current mirror is configured to force the current to drop in the fourth transistor in response to sensing a current drop in the first transistor such that the bias current flows through the second and third transistors that boosts the output current.

Abstract: Techniques for operating a touchscreen display are disclosed herein. In one embodiment, the touchscreen display device includes power regulation circuitry that supplies a first set of voltages to a display panel using high and low supply rails during a display period. During the blanking period following the display period, the high and low supply rails may be adjusted to a second set of voltages that provide for proper operation of touch-sensitive elements in the touchscreen display. Following the end of the blanking period, a portion of charge from the low supply rail is recycled by transferring the charge from the low supply rail back to the high supply rail to bring the high and low supply rails back to the first set of voltages for the next display period.

Abstract: A solid-state image sensor device comprises an image sensor section for outputting analog signals of an image being taken; a plurality of AD converter sections, arranged with respect to the column direction of the image sensor section, for converting the analog signals into digital signals; a drive circuit section for controlling the image sensor section and the AD converter sections; and a plurality of differential interface sections for transmitting the digital signals converted by the AD converter sections as differential output signals to an external device. Each of the differential interface sections comprises a current value changeover circuit and offset voltage holding circuit operative when an operation mode changeover is made.

Abstract: Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.

Abstract: Techniques to provide bootstrap control of a CMOS transistor switch. The techniques may include driving a control terminal of a CMOS transistor switch to a first predetermined voltage to set the CMOS transistor switch to an off-state. The first predetermined voltage may be drained to a discharge voltage and the control terminal may be driven to a second predetermined voltage to set the CMOS transistor switch to an on-state. The control terminal may be driven to the first predetermined voltage to return the CMOS transistor switch to the off-state.