Using Field-effect Transistor Patents (Class 327/543)
  • Patent number: 8988143
    Abstract: A switchable current source in which a reference voltage value to be used in driving the gate of an output transistor is sampled and stored. The reference voltage is derived using a reference current source which feeds a current sensing transistor. The current sensing transistor is turned off when the output transistor is turned off, so that the reference current source then does not consume power. A large reference current Iref can then be used for a short time.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: March 24, 2015
    Assignee: NXP B.V.
    Inventor: Marco Berkhout
  • Patent number: 8987937
    Abstract: To include an internal voltage generating circuit that includes a capacitor having a first electrode and a second electrode and generates an internal voltage by repeating a charge operation for charging the capacitor to a VDD level and a discharge operation for applying the VDD level to the first electrode of the capacitor to generate a voltage of two times the VDD level on the second electrode, and a control circuit that performs a control to apply a voltage that is lower than the VDD level to the capacitor when the internal voltage generating circuit is in a standby state. According to the present invention, when the internal voltage generating circuit is in a standby state, because a voltage applied to both ends of the capacitor is reduced, it is possible to reduce the power consumption due to a leakage current.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: March 24, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Koichiro Hayashi
  • Patent number: 8981833
    Abstract: Low-power circuits for providing stable voltage and current references rely on currents flowing through ultra-thin dielectric layer components for operation. A current reference circuit includes driving circuitry operative to apply a voltage to the first terminal of the component with respect to the second terminal of the component in order to cause a current to flow through the dielectric layer, and sources a reference output current that is based on the current flow through the dielectric layer in response to the applied voltage. A voltage reference circuit includes a current source which applies a current to the ultra-thin dielectric layer component, and maintains an output node at a stable reference output voltage level based on the voltage across the ultra-thin dielectric layer component in response to the current flow through the dielectric layer.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: March 17, 2015
    Assignee: Dust Networks, Inc
    Inventors: Mark Alan Lemkin, Thor Nelson Juneau
  • Publication number: 20150070085
    Abstract: A pass device configured from a common gate transistor, wherein an input voltage is applied to the source and an output at the drain is applied to a load. The input resistance of the pass device increases as the input voltage is reduced and limits the useful range of the input voltage. Increasing the gate to source voltage (Vgs) by applying a negative voltage to the gate reduces the input resistance and increases the range of operation of the pass device.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 12, 2015
    Applicant: Dialog Semiconductor GmbH
    Inventors: Julian Tyrrell, Ambreesh Bhattad
  • Patent number: 8963626
    Abstract: In various embodiments, a circuit is provided including a supply terminal, a logic circuit, an inverter and a control transistor which may include a body region, first and second source/drain regions, a gate insulating region having a layer thickness and a gate region. The first source/drain region may be coupled to the supply terminal. The logic circuit may have an internal supply terminal connected to the second source/drain region of the control transistor and a plurality of transistors each having a gate insulating region having a second layer thickness. The inverter input may be coupled to the internal supply terminal of the logic circuit and the output to the gate region of the control transistor. The inverter may include a transistor with a gate insulating region having a third layer thickness substantially equal to the first and second layer thicknesses.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: February 24, 2015
    Assignee: Infineon Technologies AG
    Inventor: Martin Feldtkeller
  • Publication number: 20150042401
    Abstract: An input receiver includes a first pass transistor coupled between an input pad and an internal receiver node. The first pass transistor includes a controlled floating gate capacitively coupled to the input pad. A source follower transistor couples between the internal receiver node and a power supply. A gate for the source follower transistor couples to the input pad.
    Type: Application
    Filed: August 8, 2013
    Publication date: February 12, 2015
    Applicant: QUALCOMM INCORPORATED
    Inventors: Stephen Knol, Michael Brunolli, Chiew-Guan Tan, Damen Redelings
  • Publication number: 20150035591
    Abstract: A low-noise reference voltages distribution circuit (10) is disclosed, comprising a multi-output voltage to current converter (V/I_Conv) adapted to receive an input reference voltage (VR) for providing a plurality of output reference currents (I1, . . . , IN) to be converted into a plurality of local reference voltages (V01, V0N) at corresponding receiving circuits (LCR1, LCRN) adapted to be connected to said reference voltages distribution circuit (10). The multi-output voltage to current converter (V/I_Conv) comprises: -an input section (20) adapted to generate on the basis of said input reference voltage (VR) a reference current (I0), the input section (20) comprising a current mirror input transistor (M0E) having a voltage controlled input terminal (g0E); -an output section (50) comprising a plurality of current mirror output transistors (M01, M0N) each adapted to provide a corresponding output reference current of said plurality of reference currents (I1, . . .
    Type: Application
    Filed: February 26, 2013
    Publication date: February 5, 2015
    Inventors: Germano Nicollini, Andrea Barbieri
  • Patent number: 8947159
    Abstract: Provided is a reference voltage generation circuit that has a flat temperature characteristic even when there are fluctuations in manufacturing step. After a semiconductor manufacturing process is finished, electrical characteristics of a semiconductor device are evaluated. Temperature characteristic of each reference voltage (VREF) of three unit reference voltage generation circuits (10) is evaluated. Then only a unit reference voltage generation circuit (10) having the most flat temperature characteristics is selected from among the three unit reference voltage generation circuits (10). Only fuses (13, 14) of the selected unit reference voltage generation circuit (10) are not cut, but other fuses (13, 14) are cut. Accordingly only the selected unit reference voltage generation circuit (10) operates, and the other unit reference voltage generation circuits (10) do not operate.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: February 3, 2015
    Assignee: Seiko Instruments Inc.
    Inventor: Hideo Yoshino
  • Publication number: 20150028943
    Abstract: Traditionally, designs have been very conservative on power grid design using higher margins than those needed for safe operation. This is especially true for process driver designs which may not have enough data on process characteristics. This invention allows us to recoup these inefficiencies and to speed up the power up/power down dynamically. This invention sequences plural power supply switches serially or in plural parallel sets as set by a wake up mode.
    Type: Application
    Filed: July 29, 2014
    Publication date: January 29, 2015
    Inventors: Sureshkumar Govindaraj, Jose L. Flores
  • Patent number: 8941437
    Abstract: A bias circuit includes: a reference current generation circuit that has a first reference-current element disposed in a first current path and has a second reference-current element disposed in a second current path; a first current mirror circuit that has a first transistor connected in series with the first reference-current element and has a second transistor connected in series with the second reference-current element; a third reference-current element disposed in a third current path disposed between the power supply terminal and the reference-current element; a third transistor connected in series with the third reference-current element; a bypass capacitor connected between the power supply terminal and a second node connected to a control terminal of the third transistor; an activation circuit connected to the first node; and a first switch connected between the first node and the second node.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: January 27, 2015
    Assignee: Fujitsu Limited
    Inventor: Hiroyuki Nakamoto
  • Patent number: 8935117
    Abstract: A testing circuit in an integrated circuit indirectly measures a voltage at a node of other circuitry in the integrated circuit. The testing circuit includes a transistor having a control electrode, a first conducting electrode coupled to a first pad, a second conducting electrode coupled to a terminal of a power supply, and one or more switches for selectively coupling the control electrode to one of the node and a second pad. A method includes determining a relationship between drain current and gate voltage of the transistor when the control electrode is coupled to the second pad. A voltage at the node is determined by relating the current through the first conducting electrode of the transistor when control electrode is coupled to the node.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Walter Luis Tercariol, Richard T. L. Saez, Fernando Zampronho Neto, Ivan Carlos Ribeiro Nascimento
  • Publication number: 20150002219
    Abstract: A semiconductor device containing a terminal, a power supply voltage dropping circuit that generates a constant voltage, a switch circuit to periodically apply a constant voltage to a terminal in response to a first clock, a current-controlled oscillator circuit, and a counter, and in which the power supply voltage dropping circuit supplies a first current to the switch circuit, the current-controlled oscillator circuit generates a second clock whose frequency changes in response to the value of the first current, and the counter counts the number of second clocks within the counting time.
    Type: Application
    Filed: May 27, 2014
    Publication date: January 1, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Masahiro ARAKI
  • Patent number: 8922273
    Abstract: A semiconductor device is capable of generating an internal voltage having a voltage level that is dependent on an external power supply voltage. The semiconductor device includes an internal voltage generation unit configured to generate a plurality of internal voltages having different voltage levels by using an external power supply voltage, a voltage level detection unit configured to detect a voltage level of the external power supply voltage, and a selection unit configured to selectively output one of the internal voltages in response to a detection result of the voltage level detection unit.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyoung-Jun Na, Kyung-Whan Kim
  • Publication number: 20140361828
    Abstract: An integrated circuit including a global supply bus, a gated supply bus, a functional circuit coupled to the gated supply bus, a programmable device that stores a programmed control parameter, and a digital power gating system. The digital power gating system includes gating devices and a power gating control system. Each gating device is coupled between the global and gated supply buses and each has a control terminal. The power gating control system controls a digital control value to control activation of the gating devices. The power gating control system is configured to perform a power gating operation by adjusting the digital control value to control a voltage of the gated supply bus relative to the voltage of the global supply bus. The power gating operation may be adjusted using the programmed control parameter. The programmable device may be a fuse array or a memory programmed with programmed control parameter.
    Type: Application
    Filed: March 10, 2014
    Publication date: December 11, 2014
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: James R. Lundberg
  • Patent number: 8907719
    Abstract: The present invention relates to an IC circuit. In an embodiment, an IC circuit includes: an RT terminal connected to an external; a current mirroring unit conducting a channel current between internal voltage power and the RT terminal and generating an internal reference current mirrored with the channel current; a negative feedback unit receiving the internal reference current, equalizing voltages of an RT terminal connection terminal and an internal reference current output terminal of the current mirroring unit to make the internal reference current constant, and providing the internal reference current inside the IC circuit; and an IC state indicating unit having a transistor, which operates complementarily with the current mirroring unit, connected between the RT terminal and a ground and providing the state of an IC or a system to the RT terminal by being linked with the complementary operation of the current mirroring unit.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: December 9, 2014
    Assignees: Samsung Electro-Mechanics Co., Ltd., University of Seoul Industry Cooperation Foundation
    Inventors: Joon Youp Sung, Jae Shin Lee, Joong Ho Choi, Yong Seong Roh, Ho Joon Jang, Chang Sik Yoo, Jung Sun Kwon, Young Jin Moon
  • Publication number: 20140340122
    Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.
    Type: Application
    Filed: May 16, 2013
    Publication date: November 20, 2014
    Applicant: ARM LIMITED
    Inventors: Parameshwarappa Anand Kumar SAVANTH, James Edward MYERS, David Walter FLYNN, Bal S. SANDHU
  • Patent number: 8890606
    Abstract: A voltage switching circuitry comprises a switching arrangement with a given number N of switches in series between a first terminal receiving a first voltage and a second terminal receiving a second voltage. The first voltage level is higher than the second voltage level, and N is at least equal to 2. A voltage-by-N divider, having N?1 output taps, is arranged to divide the first voltage by N to a scaled down version of the first voltage having a voltage level below voltage max ratings of the switches. The N?1 output taps of the divider are arranged to respectively output N?1 third voltages having respective levels staged below the first voltage level. N?1 max voltage generators generate N?1 fourth voltages, respectively equal to the maximum of the second voltage and of each of the N?1 third voltages. A switch control unit generates N control signals using the N?1 fourth voltages. These N control signals have respective voltage levels staged between the first voltage level and the second voltage level.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: November 18, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jerome Enjalbert, Marianne Maleyran
  • Publication number: 20140333371
    Abstract: A microelectronic package includes a microelectronic element operable to output a discrete-value logic signal indicating an imminent increase in demand for current by at least some portion of the microelectronic element. An active power delivery element within the package is operable by the logic signal to increase current delivery to the microelectronic element.
    Type: Application
    Filed: April 4, 2014
    Publication date: November 13, 2014
    Applicant: Tessera, Inc.
    Inventors: Richard Dewitt Crisp, Michael C. Parris, Mark Kroot
  • Patent number: 8884686
    Abstract: When the conduction state of at least one MOS transistor of a PMOS transistor (P1) and NMOS transistor (N2) is switched to an off state, current which would be applied to the MOS transistor with a conduction state in the off state due to the conduction state becoming the off state is bypassed to a resistor (R3, R4). Due to this, an MOS transistor with a conduction state in the off state being supplied with direct current power as it is can be avoided and the withstand voltage of that MOS transistor does not have to be raised. For this reason, the manufacturing costs of the direct current voltage output circuit (54a) can be kept down. At the same time, the circuit size of the direct current voltage output circuit (54a) can be made smaller.
    Type: Grant
    Filed: July 4, 2012
    Date of Patent: November 11, 2014
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Akihiko Nogi
  • Patent number: 8878601
    Abstract: A circuit includes a gate node, and a bias circuit coupled to the gate node. The bias circuit is configured to, in response to a change in a gate voltage on the gate node, provide a positive feedback to the gate voltage. A power circuit is coupled to the gate node, wherein the power circuit includes a power Metal-Oxide-Semiconductor (MOS) transistor. The power circuit is configured to, in response to a change in the gate voltage, provide a negative feedback to the gate voltage. An output node is coupled to the power circuit.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhy-Jyi Sze, Biay-Cheng Hseih, Shou-Gwo Wuu
  • Patent number: 8872575
    Abstract: The present invention discloses a semiconductor device and relates to the semiconductor field. The semiconductor device comprises: a PMOS transistor for processing a input signal, the PMOS transistor comprising a gate and a source, the source being connected to a first voltage source; and a restoring circuit connected to the PMOS transistor for preventing degradation of the PMOS transistor, wherein the restoring circuit makes the gate voltage of the PMOS transistor to be higher than the voltage of the first voltage source, when the input signal is at a high level. According to the semiconductor device of the present invention, a positive bias voltage is applied on the gate of the PMOS transistor through the restoring circuit when the PMOS transistor is turned off, which can accelerate electric parameter recovery for PMOS transistors and therefore improve the performance of PMOS transistors.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 28, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Zhenghao Gan, Junhong Feng
  • Patent number: 8872496
    Abstract: A DC-DC converter includes a drive circuit configured to drive a first switching element, and a second switching element coupled between a low potential power terminal of the drive circuit and a first node corresponding to the input voltage or the output voltage. A current detecting section detects a load current flowing in the output terminal. A control circuit turns on a third switching element, which is coupled between the low potential power terminal of the drive circuit and a second node having a potential lower than both the input voltage and the output voltage, in a case where a difference between the input voltage and the output voltage is lower than a threshold. The control circuit controls the second and third switching elements based on a detection result of the current detecting section in a case where the difference is equal to or greater than the threshold.
    Type: Grant
    Filed: December 15, 2012
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Toru Miyamae
  • Patent number: 8872579
    Abstract: Systems and methods are provided for power control. In some implementations, a power control system includes a first transistor having a drain coupled to a first conductor (e.g., first pair of wires of an Ethernet cable), a second transistor having a drain coupled to a second conductor (e.g., second pair of wires of the Ethernet cable), a current sensor coupled to sources of the first and second transistors, and a current management circuit. The current management circuit may detect drain voltages of the first transistor and the second transistor, and adjust gate voltages of the first transistor and the second transistor to keep the drain voltages of the first transistor and the second transistor approximately equal. The current management circuit may detect a current through the current sensor, and adjust the gate voltages of the first transistor and the second transistor to limit the detected current to a current limit.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: October 28, 2014
    Assignee: Broadcom Corporation
    Inventors: Marius Vladan, Sesha Panguluri
  • Publication number: 20140312963
    Abstract: a switchable current source in which a reference voltage value to be used in driving the gate of an output transistor is sampled and stored. The reference voltage is derived using a reference current source which feeds a current sensing transistor. The current sensing transistor is turned off when the output transistor is turned off, so that the reference current source then does not consume power. A large reference current Iref can then be used for a short time.
    Type: Application
    Filed: March 7, 2014
    Publication date: October 23, 2014
    Applicant: NXP B.V.
    Inventor: Marco Berkhout
  • Patent number: 8866540
    Abstract: Biasing circuit for providing a supply voltage (Vdd) for an inverter based circuit. The biasing circuit is provided on a same die as the inverter based circuit, and includes a first shorted inverter circuit (T1, T2) and a second shorted inverter circuit (T3, T4). The first shorted inverter circuit (T1, T2) is connected in parallel to a series configuration of the second shorted inverter circuit (T3, T4) and a reference impedance (R). The first shorted inverter circuit (T1, T2) and second shorted inverter circuit (T3, T4) have different transistor geometries. A control circuit (T5-T11) is connected to the first shorted inverter circuit (T1, T2) and the second shorted inverter circuit (T3, T4), and supplied with a main supply voltage (Vdd). The control circuit (T5-T11) is arranged such that an equal current flows through the first shorted inverter circuit (T1, T2) and second shorted inverter circuit (T3, T4).
    Type: Grant
    Filed: May 30, 2011
    Date of Patent: October 21, 2014
    Assignee: GreenPeak Technologies B.V.
    Inventors: Richard Jan Engel Jansen, Jan Hendrik Haanstra
  • Publication number: 20140306752
    Abstract: A DC-DC converter for generating an output voltage from input voltage, includes: an output stage for outputting the output voltage; an error amplifier having an input and a reference input for receiving a feedback voltage at the input in accordance with the output voltage and for receiving a reference voltage at the reference input, the error amplifier generating an amplified voltage for driving the output stage, the amplifier voltage corresponding to the difference between the feedback voltage and the reference voltage; a phase compensation unit for generating a phase compensation component to the feedback voltage; and a phase compensation controller for controlling the phase of the phase compensation unit; wherein the feedback voltage determined by the output voltage plus said phase compensation component.
    Type: Application
    Filed: December 20, 2013
    Publication date: October 16, 2014
    Applicant: Spansion LLC
    Inventor: Hideta OKI
  • Publication number: 20140266414
    Abstract: A voltage generator of a contactless integrated circuit (IC) card includes a regulator configured to generate a first internal voltage based on an input voltage and a first reference voltage, the input voltage being received through an antenna of the contactless IC card. The voltage generator includes an internal voltage generator configured to generate a second internal voltage, the second internal voltage being used to operate an internal circuit of the contactless IC card. The voltage generator includes a reference voltage generator configured to generate a second reference voltage based on the first internal voltage, the second reference voltage being generated without regard to a fluctuation component of the first internal voltage. The voltage generator includes a switching unit configured to provide one of the first and second internal voltages as the first reference voltage in response to first and second switching control signals.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 18, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Ho KIM, Il-Jong SONG, Jong-Pil CHO
  • Publication number: 20140254051
    Abstract: A device includes a snapback clamp circuit configured to clamp a supply voltage in response to the supply voltage exceeding a trigger voltage level. In at least one embodiment, the snapback clamp circuit includes a clamp transistor and a programmable resistance portion that is responsive to a control signal to calibrate the trigger voltage level. Alternatively or in addition, the snapback clamp circuit may include a programmable bias device configured to calibrate the trigger voltage level by biasing a gate terminal of the clamp transistor. In another particular embodiment, a method of calibrating a snapback clamp circuit is disclosed. In another particular embodiment, a method of operating an integrated circuit is disclosed.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Ankit Srivastava, Matthew David Sienko, Eugene Robert Worley
  • Patent number: 8829983
    Abstract: An embodiment of an apparatus is disclosed. For this embodiment, an output driver and a bias voltage controller are included. The bias voltage controller is coupled to provide first and second bias voltages to the output driver. The bias voltage controller comprises a bias generator coupled to a first voltage supply, a second voltage supply, and a ground node. The bias generator has a first bias node for sourcing the first bias voltage. The first voltage supply is configured to provide a higher voltage level than the second voltage supply. A resistor-divider network is coupled to the first voltage supply and the ground node. A watch dog circuit is coupled to the resistor-divider network, bias generator, and the ground node. A comparison circuit is coupled to the bias generator and the second voltage supply. The comparison circuit has a second bias node for sourcing the second bias voltage.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: September 9, 2014
    Assignee: Xilinx, Inc.
    Inventor: Krishna Chaitanya Potluri
  • Patent number: 8823446
    Abstract: A current mirror with immunity for the variation of threshold voltage includes raising the voltage difference between the gate and the source of a MOS in the current source, and increasing the channel length of the MOS for limiting the generated reference current.
    Type: Grant
    Filed: May 24, 2009
    Date of Patent: September 2, 2014
    Assignee: Etron Technology, Inc.
    Inventors: Chun Shiah, Hao-Jan Yang, Ho-Yin Chen, Kuo-Chen Lai
  • Publication number: 20140225662
    Abstract: An approach is provided for a low-voltage, high-accuracy current mirror circuit. In one example, a current mirror circuit includes an input circuit configured to receive an input reference current. The input circuit includes a feedback channel for comparing and substantially matching the input reference current with an output current. The feedback channel is not configured for matching an input voltage with an output voltage. The input circuit does not include a comparator having an operational amplifier to compare the input reference current with the output current. The current mirror circuit also includes an output circuit coupled to the input circuit. The output circuit is configured to send the output current to one or more components of a circuit block.
    Type: Application
    Filed: February 11, 2013
    Publication date: August 14, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: Yoshinori NISHI
  • Patent number: 8791686
    Abstract: The voltage reference circuit includes: a first MOS transistor; a second MOS transistor including a gate terminal connected to a gate terminal of the first MOS transistor and having an absolute value of a threshold value and a K value higher than an absolute value of a threshold value and a K value of the first MOS transistor; a current mirror circuit flowing a current based on a difference between the absolute values of the threshold values of the first MOS transistor and the second MOS transistor; a third MOS transistor flowing the current; and a fourth MOS transistor having an absolute value of a threshold value and a K value higher than an absolute value of a threshold value of the third MOS transistor and flowing the current.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: July 29, 2014
    Assignee: Seiko Instruments Inc.
    Inventors: Taro Yamasaki, Fumiyasu Utsunomiya
  • Patent number: 8786360
    Abstract: The present invention discloses a fast switching current mirror circuit and method for generating fast switching current. The circuit and method for fast switching of a current mirror with large MOSFET size will save space and current consumption.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: July 22, 2014
    Assignee: STMicroelectronics Asia Pacific PTE, Ltd.
    Inventor: Justin Ang
  • Patent number: 8786266
    Abstract: A high voltage switching regulator has significantly reduced current sensing delay between measurement of input current and generation of sensed current values, while maintaining good accuracy of the current through a power transistor using current replication and a current conveyor. High sensing accuracy of the input current ensures good load regulation, and low sensing delay ensures fixed duty cycle over a wide range of output currents and high input to output voltage ratios. A current conveyor is used to transfer high side current values to low side control circuits, e.g., pulse width modulation (PWM) control. The current conveyor is always on, e.g., some current flow is always present, thus minimizing any current measurement delay. This is accomplished by dynamically biasing the current conveyor by draining to ground a current equal to the sensed current. Wherein balancing of the current conveyor is ensured and offset at the input of the current conveyor is minimized.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: July 22, 2014
    Assignee: Microchip Technology Incorporated
    Inventors: Philippe Deval, Philippe Gimmel, Marius Budaes, Daniel Leonescu, Terry Cleveland, Scott Dearborn
  • Publication number: 20140199948
    Abstract: A single-ended comparator is disclosed herein. The comparator may be implemented with low-voltage semiconductor devices that are capable of operating with high-voltage signals at an input. The single-ended comparator may be integrated in a larger circuit to receive and detect information provided on the input at voltage levels higher than the levels supported by the rest of the circuit, and transfer the information in the received signal for use by the rest of the circuit.
    Type: Application
    Filed: January 14, 2013
    Publication date: July 17, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Jan Diffenderfer, Yu Song
  • Publication number: 20140197884
    Abstract: A port current control arrangement, constituted of: a current source arranged to generate a reference current or a predetermined value; an on-chip reference resistor, the generated reference current arranged to produce a reference voltage across the on-chip reference resistor; an on-chip sense resistor, a port current arranged to flow through the on-chip sense resistor and produce a sense voltage across the on-chip sense resistor, wherein the resistance of the on-chip sense resistor exhibits a predetermined relationship with the resistance of the first on-chip reference resistor; and a current control circuit, a first input of the current control circuit arranged to receive the produced reference voltage and a second input of the current control circuit arranged to receive the sense voltage, wherein the current control circuit is arranged to limit the port current to a value responsive to the received reference voltage and the received sense voltage.
    Type: Application
    Filed: December 30, 2013
    Publication date: July 17, 2014
    Applicant: Microsemi Corp. - Analog Mixed Signal Group, Ltd.
    Inventor: Shimon COHEN
  • Publication number: 20140184318
    Abstract: The invention concerns power supply circuitry for controlling a power-up phase of an islet of an integrated circuit, the circuitry having: a switch (102) controlled by a current and coupled between a supply voltage rail (104) and an internal voltage rail (105) of the islet.
    Type: Application
    Filed: December 26, 2013
    Publication date: July 3, 2014
    Applicant: Dolphin Integration
    Inventors: Loïc Sibeud, Grégoire Gimenez
  • Patent number: 8766708
    Abstract: A semiconductor device includes an internal voltage input buffer configured to determine voltage levels of a pull-up driving node and a pull-down driving node as a result of a comparison between a voltage level of an internal voltage node and a voltage level of a reference voltage node such that the pull-up driving node and the pull-down driving node to maintain a voltage level difference, and an internal voltage driving block configured to pull-up drive the internal voltage node in response to the voltage level of the pull-up driving node and pull-down drive the internal voltage node in response to the voltage level of the pull-down driving node.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: July 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Gyu Lee
  • Patent number: 8766709
    Abstract: A semiconductor integrated circuit includes a first internal voltage generator including a PMOS and a first comparator, and a second internal voltage generator including an NMOS, a second comparator, and a voltage pump generator configured to provide a pumping power voltage to the second comparator. A power control circuit switchably enables an output from the first internal voltage generator during a power-on of the semiconductor integrated circuit and enables an output from the second internal voltage generator after the power-on.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: July 1, 2014
    Assignee: Winbond Electronics Corp.
    Inventor: Young Tae Kim
  • Publication number: 20140167839
    Abstract: A negative voltage regulation circuit includes an operational amplifier configured to receive a feedback voltage and an input voltage, a pull-up element configured to pull-up drive a first node based on output voltage of the operational amplifier, a load element coupled between the first node and a negative voltage terminal, a pull-down element configured to pull-down drive a final negative voltage output terminal using a voltage of the negative voltage terminal based on a voltage level of the first node, and a voltage division unit coupled between the final negative voltage output terminal and a pull-up voltage terminal, and configured to generate the feedback voltage by voltage division.
    Type: Application
    Filed: March 14, 2013
    Publication date: June 19, 2014
    Applicant: SK HYNIX INC.
    Inventor: Jae-Kwan KWON
  • Patent number: 8755235
    Abstract: According to one embodiment, a voltage generation circuit includes a first boost circuit, a voltage division circuit, a first detection circuit, a capacitor and a first switch. The first boost circuit outputs a first voltage. The voltage division circuit divides the first voltage. The first detection circuit is configured to detect a first monitor voltage supplied to the first input terminal, based on a reference voltage which is supplied to a second input terminal of the first detection circuit, and to control an operation of the first boost circuit. The capacitor is connected between an output terminal of the first boost circuit and the first input terminal of the first detection circuit. The first switch cuts off a connection between the capacitor and the first detection circuit, based on an output signal of the first detection circuit, until the first voltage is output from the first boost circuit.
    Type: Grant
    Filed: September 18, 2011
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuro Midorikawa, Masami Masuda
  • Publication number: 20140152382
    Abstract: A configurable-voltage converter circuit that may be CMOS and an integrated circuit chip including the converter circuit and method of operating the IC chip and circuit. A transistor totem, e.g., of 6 or more field effect transistors, PFETs and NFETs, connected (PNPNPN) between a first supply (Vin) line and a supply return line. A first switching capacitor is connected between first and second pairs of totem PN FETs pair of transistors. A second switching capacitor is connected between the second and a third pair of totem FETs. A configuration control selectively switches both third FETs off to float the connected end of the second capacitor, thereby switching voltage converter modes.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 5, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
  • Patent number: 8742800
    Abstract: An integrated circuit with precision current source includes a first MOSFET, a second MOSFET, an op-amp and a resistor formed on a common semiconductor substrate. The first MOSFET is characterized by a first multiplier (xM1) and the second MOSFET is characterized by a second multiplier (xM2) where a ratio of xM2 to xM1 is greater than one. An inverting input of the op-amp is coupled to a drain of the first MOSFET and an output of the op-amp is coupled to a gate of the first MOSFET.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: June 3, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Gabriel E. Tanase
  • Patent number: 8736358
    Abstract: A current source providing an output current with a fixed current range includes a bias circuit, a resistor, a current mirror, and a controller. The bias circuit provides a first voltage weighted with a first tunable coefficient and a second voltage weighted with a second tunable coefficient. The resistor has a tunable resistance for determining a bias current according to a voltage difference between the first and the second voltages and the tunable resistance. The current mirror generates the output current according to the bias current. The controller adjusts the tunable resistance and one of the first and the second tunable coefficients to achieve a voltage-current coefficient with different values, while the bias current and the output current are kept within a fixed current range.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: May 27, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Chung-Kuang Chen, Han-Sung Chen, Chun-Hsiung Hung
  • Publication number: 20140132338
    Abstract: Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.
    Type: Application
    Filed: January 21, 2014
    Publication date: May 15, 2014
    Applicant: STMicroelectronics SA
    Inventor: Frédéric Hasbani
  • Publication number: 20140128013
    Abstract: Aspects of the present disclosure relate to a current multiplier that can generate an output current with high linearity and/or high temperature compensation. Such current multipliers can be implemented by complementary metal oxide semiconductor (CMOS) circuit elements. In one embodiment, the current multiplier can include a current divider and a core current multiplier. The current divider can generate a divided current by dividing an input current by an adjustable division ratio. The division ratio can be adjusted, for example, based on a comparison of the input current with a reference current. The core current multiplier can generate the output current based on multiplying the divided current and a different current. According to certain embodiments, the output current can be maintained within a predetermined range as the input current to the current divider varies within a relatively wide range.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 8, 2014
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventors: Hui Liu, Duane A. Green, David Anthony Sawatzky
  • Patent number: 8710915
    Abstract: An apparatus, includes a plurality of circuits each of which operates with a reference voltage, a constant current generator which generates a substantially constant current, and distributes the substantially constant current to each of the circuits, and a plurality of converters, each of the converters respectively corresponding to each of the circuits, each of which converts the substantially constant current to the reference voltage and respectively provides the reference voltage to each of the circuits.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: April 29, 2014
    Assignee: NEC Corporation
    Inventor: Hiroshi Ibuka
  • Patent number: 8704591
    Abstract: A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias signals. Magnitudes the first and second bias signals are configured to control a reference signal generated by the reference circuit such that when the reference signal is near a quiescent value of the reference signal, a current in the reference circuit is below a first level, and when the reference signal is outside of the prescribed limits, the current in the reference circuit increases nonlinearly.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: April 22, 2014
    Assignee: LSI Corporation
    Inventors: Pankaj Kumar, Pramod Parameswaran, Vani Deshpande, Makeshwar Kothandaraman
  • Publication number: 20140097889
    Abstract: An interface circuit includes a receiver, a first terminal resistor, a second terminal resistor, a common mode capacitor, a first switch, a second switch, and a common mode potential adjustment circuit. The receiver includes a first channel for receiving a first channel voltage, and a second channel for receiving a second channel voltage. The common mode capacitor provides a common mode potential. The first switch electrically connects the first terminal resistor to the common mode capacitor, and the second switch electrically connects the second terminal resistor to the common mode capacitor. The common mode potential adjustment circuit is coupled to the first switch, the second switch and the common mode capacitor, and adjusts the common mode potential according to the first channel voltage and the second channel voltage.
    Type: Application
    Filed: March 6, 2013
    Publication date: April 10, 2014
    Applicant: NOVATEK MICROELECTRONICS CORP.
    Inventors: Tse-Hung WU, Chao-Kai Tu
  • Patent number: 8692611
    Abstract: A microelectronic package includes a microelectronic element operable to output a discrete-value logic signal indicating an imminent increase in demand for current by at least some portion of the microelectronic element. An active power delivery element within the package is operable by the logic signal to increase current delivery to the microelectronic element.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: April 8, 2014
    Assignee: Tessera, Inc.
    Inventors: Richard Dewitt Crisp, Michael C. Parris, Mark Kroot