Abstract: An integrated circuit including a global supply bus, a gated supply bus, a functional circuit coupled to the gated supply bus, a programmable device that stores a programmed control parameter, and a digital power gating system. The digital power gating system includes gating devices and a power gating control system. Each gating device is coupled between the global and gated supply buses and each has a control terminal. The power gating control system controls a digital control value to control activation of the gating devices. The power gating control system is configured to perform a power gating operation by adjusting the digital control value to control a voltage of the gated supply bus relative to the voltage of the global supply bus. The power gating operation may be adjusted using the programmed control parameter. The programmable device may be a fuse array or a memory programmed with programmed control parameter.

Abstract: The present invention relates to an IC circuit. In an embodiment, an IC circuit includes: an RT terminal connected to an external; a current mirroring unit conducting a channel current between internal voltage power and the RT terminal and generating an internal reference current mirrored with the channel current; a negative feedback unit receiving the internal reference current, equalizing voltages of an RT terminal connection terminal and an internal reference current output terminal of the current mirroring unit to make the internal reference current constant, and providing the internal reference current inside the IC circuit; and an IC state indicating unit having a transistor, which operates complementarily with the current mirroring unit, connected between the RT terminal and a ground and providing the state of an IC or a system to the RT terminal by being linked with the complementary operation of the current mirroring unit.

Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

Abstract: A voltage switching circuitry comprises a switching arrangement with a given number N of switches in series between a first terminal receiving a first voltage and a second terminal receiving a second voltage. The first voltage level is higher than the second voltage level, and N is at least equal to 2. A voltage-by-N divider, having N?1 output taps, is arranged to divide the first voltage by N to a scaled down version of the first voltage having a voltage level below voltage max ratings of the switches. The N?1 output taps of the divider are arranged to respectively output N?1 third voltages having respective levels staged below the first voltage level. N?1 max voltage generators generate N?1 fourth voltages, respectively equal to the maximum of the second voltage and of each of the N?1 third voltages. A switch control unit generates N control signals using the N?1 fourth voltages. These N control signals have respective voltage levels staged between the first voltage level and the second voltage level.

Abstract: A microelectronic package includes a microelectronic element operable to output a discrete-value logic signal indicating an imminent increase in demand for current by at least some portion of the microelectronic element. An active power delivery element within the package is operable by the logic signal to increase current delivery to the microelectronic element.

Abstract: When the conduction state of at least one MOS transistor of a PMOS transistor (P1) and NMOS transistor (N2) is switched to an off state, current which would be applied to the MOS transistor with a conduction state in the off state due to the conduction state becoming the off state is bypassed to a resistor (R3, R4). Due to this, an MOS transistor with a conduction state in the off state being supplied with direct current power as it is can be avoided and the withstand voltage of that MOS transistor does not have to be raised. For this reason, the manufacturing costs of the direct current voltage output circuit (54a) can be kept down. At the same time, the circuit size of the direct current voltage output circuit (54a) can be made smaller.

Abstract: A circuit includes a gate node, and a bias circuit coupled to the gate node. The bias circuit is configured to, in response to a change in a gate voltage on the gate node, provide a positive feedback to the gate voltage. A power circuit is coupled to the gate node, wherein the power circuit includes a power Metal-Oxide-Semiconductor (MOS) transistor. The power circuit is configured to, in response to a change in the gate voltage, provide a negative feedback to the gate voltage. An output node is coupled to the power circuit.

Abstract: Systems and methods are provided for power control. In some implementations, a power control system includes a first transistor having a drain coupled to a first conductor (e.g., first pair of wires of an Ethernet cable), a second transistor having a drain coupled to a second conductor (e.g., second pair of wires of the Ethernet cable), a current sensor coupled to sources of the first and second transistors, and a current management circuit. The current management circuit may detect drain voltages of the first transistor and the second transistor, and adjust gate voltages of the first transistor and the second transistor to keep the drain voltages of the first transistor and the second transistor approximately equal. The current management circuit may detect a current through the current sensor, and adjust the gate voltages of the first transistor and the second transistor to limit the detected current to a current limit.

Abstract: A DC-DC converter includes a drive circuit configured to drive a first switching element, and a second switching element coupled between a low potential power terminal of the drive circuit and a first node corresponding to the input voltage or the output voltage. A current detecting section detects a load current flowing in the output terminal. A control circuit turns on a third switching element, which is coupled between the low potential power terminal of the drive circuit and a second node having a potential lower than both the input voltage and the output voltage, in a case where a difference between the input voltage and the output voltage is lower than a threshold. The control circuit controls the second and third switching elements based on a detection result of the current detecting section in a case where the difference is equal to or greater than the threshold.

Abstract: The present invention discloses a semiconductor device and relates to the semiconductor field. The semiconductor device comprises: a PMOS transistor for processing a input signal, the PMOS transistor comprising a gate and a source, the source being connected to a first voltage source; and a restoring circuit connected to the PMOS transistor for preventing degradation of the PMOS transistor, wherein the restoring circuit makes the gate voltage of the PMOS transistor to be higher than the voltage of the first voltage source, when the input signal is at a high level. According to the semiconductor device of the present invention, a positive bias voltage is applied on the gate of the PMOS transistor through the restoring circuit when the PMOS transistor is turned off, which can accelerate electric parameter recovery for PMOS transistors and therefore improve the performance of PMOS transistors.

Abstract: a switchable current source in which a reference voltage value to be used in driving the gate of an output transistor is sampled and stored. The reference voltage is derived using a reference current source which feeds a current sensing transistor. The current sensing transistor is turned off when the output transistor is turned off, so that the reference current source then does not consume power. A large reference current Iref can then be used for a short time.

Abstract: Biasing circuit for providing a supply voltage (Vdd) for an inverter based circuit. The biasing circuit is provided on a same die as the inverter based circuit, and includes a first shorted inverter circuit (T1, T2) and a second shorted inverter circuit (T3, T4). The first shorted inverter circuit (T1, T2) is connected in parallel to a series configuration of the second shorted inverter circuit (T3, T4) and a reference impedance (R). The first shorted inverter circuit (T1, T2) and second shorted inverter circuit (T3, T4) have different transistor geometries. A control circuit (T5-T11) is connected to the first shorted inverter circuit (T1, T2) and the second shorted inverter circuit (T3, T4), and supplied with a main supply voltage (Vdd). The control circuit (T5-T11) is arranged such that an equal current flows through the first shorted inverter circuit (T1, T2) and second shorted inverter circuit (T3, T4).

Abstract: A DC-DC converter for generating an output voltage from input voltage, includes: an output stage for outputting the output voltage; an error amplifier having an input and a reference input for receiving a feedback voltage at the input in accordance with the output voltage and for receiving a reference voltage at the reference input, the error amplifier generating an amplified voltage for driving the output stage, the amplifier voltage corresponding to the difference between the feedback voltage and the reference voltage; a phase compensation unit for generating a phase compensation component to the feedback voltage; and a phase compensation controller for controlling the phase of the phase compensation unit; wherein the feedback voltage determined by the output voltage plus said phase compensation component.

Abstract: A voltage generator of a contactless integrated circuit (IC) card includes a regulator configured to generate a first internal voltage based on an input voltage and a first reference voltage, the input voltage being received through an antenna of the contactless IC card. The voltage generator includes an internal voltage generator configured to generate a second internal voltage, the second internal voltage being used to operate an internal circuit of the contactless IC card. The voltage generator includes a reference voltage generator configured to generate a second reference voltage based on the first internal voltage, the second reference voltage being generated without regard to a fluctuation component of the first internal voltage. The voltage generator includes a switching unit configured to provide one of the first and second internal voltages as the first reference voltage in response to first and second switching control signals.

Abstract: A device includes a snapback clamp circuit configured to clamp a supply voltage in response to the supply voltage exceeding a trigger voltage level. In at least one embodiment, the snapback clamp circuit includes a clamp transistor and a programmable resistance portion that is responsive to a control signal to calibrate the trigger voltage level. Alternatively or in addition, the snapback clamp circuit may include a programmable bias device configured to calibrate the trigger voltage level by biasing a gate terminal of the clamp transistor. In another particular embodiment, a method of calibrating a snapback clamp circuit is disclosed. In another particular embodiment, a method of operating an integrated circuit is disclosed.

Abstract: An embodiment of an apparatus is disclosed. For this embodiment, an output driver and a bias voltage controller are included. The bias voltage controller is coupled to provide first and second bias voltages to the output driver. The bias voltage controller comprises a bias generator coupled to a first voltage supply, a second voltage supply, and a ground node. The bias generator has a first bias node for sourcing the first bias voltage. The first voltage supply is configured to provide a higher voltage level than the second voltage supply. A resistor-divider network is coupled to the first voltage supply and the ground node. A watch dog circuit is coupled to the resistor-divider network, bias generator, and the ground node. A comparison circuit is coupled to the bias generator and the second voltage supply. The comparison circuit has a second bias node for sourcing the second bias voltage.

Abstract: A current mirror with immunity for the variation of threshold voltage includes raising the voltage difference between the gate and the source of a MOS in the current source, and increasing the channel length of the MOS for limiting the generated reference current.

Abstract: An approach is provided for a low-voltage, high-accuracy current mirror circuit. In one example, a current mirror circuit includes an input circuit configured to receive an input reference current. The input circuit includes a feedback channel for comparing and substantially matching the input reference current with an output current. The feedback channel is not configured for matching an input voltage with an output voltage. The input circuit does not include a comparator having an operational amplifier to compare the input reference current with the output current. The current mirror circuit also includes an output circuit coupled to the input circuit. The output circuit is configured to send the output current to one or more components of a circuit block.

Abstract: The voltage reference circuit includes: a first MOS transistor; a second MOS transistor including a gate terminal connected to a gate terminal of the first MOS transistor and having an absolute value of a threshold value and a K value higher than an absolute value of a threshold value and a K value of the first MOS transistor; a current mirror circuit flowing a current based on a difference between the absolute values of the threshold values of the first MOS transistor and the second MOS transistor; a third MOS transistor flowing the current; and a fourth MOS transistor having an absolute value of a threshold value and a K value higher than an absolute value of a threshold value of the third MOS transistor and flowing the current.

Abstract: A high voltage switching regulator has significantly reduced current sensing delay between measurement of input current and generation of sensed current values, while maintaining good accuracy of the current through a power transistor using current replication and a current conveyor. High sensing accuracy of the input current ensures good load regulation, and low sensing delay ensures fixed duty cycle over a wide range of output currents and high input to output voltage ratios. A current conveyor is used to transfer high side current values to low side control circuits, e.g., pulse width modulation (PWM) control. The current conveyor is always on, e.g., some current flow is always present, thus minimizing any current measurement delay. This is accomplished by dynamically biasing the current conveyor by draining to ground a current equal to the sensed current. Wherein balancing of the current conveyor is ensured and offset at the input of the current conveyor is minimized.

Abstract: The present invention discloses a fast switching current mirror circuit and method for generating fast switching current. The circuit and method for fast switching of a current mirror with large MOSFET size will save space and current consumption.

Abstract: A single-ended comparator is disclosed herein. The comparator may be implemented with low-voltage semiconductor devices that are capable of operating with high-voltage signals at an input. The single-ended comparator may be integrated in a larger circuit to receive and detect information provided on the input at voltage levels higher than the levels supported by the rest of the circuit, and transfer the information in the received signal for use by the rest of the circuit.

Abstract: A port current control arrangement, constituted of: a current source arranged to generate a reference current or a predetermined value; an on-chip reference resistor, the generated reference current arranged to produce a reference voltage across the on-chip reference resistor; an on-chip sense resistor, a port current arranged to flow through the on-chip sense resistor and produce a sense voltage across the on-chip sense resistor, wherein the resistance of the on-chip sense resistor exhibits a predetermined relationship with the resistance of the first on-chip reference resistor; and a current control circuit, a first input of the current control circuit arranged to receive the produced reference voltage and a second input of the current control circuit arranged to receive the sense voltage, wherein the current control circuit is arranged to limit the port current to a value responsive to the received reference voltage and the received sense voltage.

Abstract: The invention concerns power supply circuitry for controlling a power-up phase of an islet of an integrated circuit, the circuitry having: a switch (102) controlled by a current and coupled between a supply voltage rail (104) and an internal voltage rail (105) of the islet.

Abstract: A semiconductor integrated circuit includes a first internal voltage generator including a PMOS and a first comparator, and a second internal voltage generator including an NMOS, a second comparator, and a voltage pump generator configured to provide a pumping power voltage to the second comparator. A power control circuit switchably enables an output from the first internal voltage generator during a power-on of the semiconductor integrated circuit and enables an output from the second internal voltage generator after the power-on.

Abstract: A semiconductor device includes an internal voltage input buffer configured to determine voltage levels of a pull-up driving node and a pull-down driving node as a result of a comparison between a voltage level of an internal voltage node and a voltage level of a reference voltage node such that the pull-up driving node and the pull-down driving node to maintain a voltage level difference, and an internal voltage driving block configured to pull-up drive the internal voltage node in response to the voltage level of the pull-up driving node and pull-down drive the internal voltage node in response to the voltage level of the pull-down driving node.

Abstract: A negative voltage regulation circuit includes an operational amplifier configured to receive a feedback voltage and an input voltage, a pull-up element configured to pull-up drive a first node based on output voltage of the operational amplifier, a load element coupled between the first node and a negative voltage terminal, a pull-down element configured to pull-down drive a final negative voltage output terminal using a voltage of the negative voltage terminal based on a voltage level of the first node, and a voltage division unit coupled between the final negative voltage output terminal and a pull-up voltage terminal, and configured to generate the feedback voltage by voltage division.

Abstract: According to one embodiment, a voltage generation circuit includes a first boost circuit, a voltage division circuit, a first detection circuit, a capacitor and a first switch. The first boost circuit outputs a first voltage. The voltage division circuit divides the first voltage. The first detection circuit is configured to detect a first monitor voltage supplied to the first input terminal, based on a reference voltage which is supplied to a second input terminal of the first detection circuit, and to control an operation of the first boost circuit. The capacitor is connected between an output terminal of the first boost circuit and the first input terminal of the first detection circuit. The first switch cuts off a connection between the capacitor and the first detection circuit, based on an output signal of the first detection circuit, until the first voltage is output from the first boost circuit.

Abstract: A configurable-voltage converter circuit that may be CMOS and an integrated circuit chip including the converter circuit and method of operating the IC chip and circuit. A transistor totem, e.g., of 6 or more field effect transistors, PFETs and NFETs, connected (PNPNPN) between a first supply (Vin) line and a supply return line. A first switching capacitor is connected between first and second pairs of totem PN FETs pair of transistors. A second switching capacitor is connected between the second and a third pair of totem FETs. A configuration control selectively switches both third FETs off to float the connected end of the second capacitor, thereby switching voltage converter modes.

Abstract: An integrated circuit with precision current source includes a first MOSFET, a second MOSFET, an op-amp and a resistor formed on a common semiconductor substrate. The first MOSFET is characterized by a first multiplier (xM1) and the second MOSFET is characterized by a second multiplier (xM2) where a ratio of xM2 to xM1 is greater than one. An inverting input of the op-amp is coupled to a drain of the first MOSFET and an output of the op-amp is coupled to a gate of the first MOSFET.

Abstract: A current source providing an output current with a fixed current range includes a bias circuit, a resistor, a current mirror, and a controller. The bias circuit provides a first voltage weighted with a first tunable coefficient and a second voltage weighted with a second tunable coefficient. The resistor has a tunable resistance for determining a bias current according to a voltage difference between the first and the second voltages and the tunable resistance. The current mirror generates the output current according to the bias current. The controller adjusts the tunable resistance and one of the first and the second tunable coefficients to achieve a voltage-current coefficient with different values, while the bias current and the output current are kept within a fixed current range.

Abstract: Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.

Abstract: Aspects of the present disclosure relate to a current multiplier that can generate an output current with high linearity and/or high temperature compensation. Such current multipliers can be implemented by complementary metal oxide semiconductor (CMOS) circuit elements. In one embodiment, the current multiplier can include a current divider and a core current multiplier. The current divider can generate a divided current by dividing an input current by an adjustable division ratio. The division ratio can be adjusted, for example, based on a comparison of the input current with a reference current. The core current multiplier can generate the output current based on multiplying the divided current and a different current. According to certain embodiments, the output current can be maintained within a predetermined range as the input current to the current divider varies within a relatively wide range.

Abstract: An apparatus, includes a plurality of circuits each of which operates with a reference voltage, a constant current generator which generates a substantially constant current, and distributes the substantially constant current to each of the circuits, and a plurality of converters, each of the converters respectively corresponding to each of the circuits, each of which converts the substantially constant current to the reference voltage and respectively provides the reference voltage to each of the circuits.

Abstract: A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias signals. Magnitudes the first and second bias signals are configured to control a reference signal generated by the reference circuit such that when the reference signal is near a quiescent value of the reference signal, a current in the reference circuit is below a first level, and when the reference signal is outside of the prescribed limits, the current in the reference circuit increases nonlinearly.

Abstract: An interface circuit includes a receiver, a first terminal resistor, a second terminal resistor, a common mode capacitor, a first switch, a second switch, and a common mode potential adjustment circuit. The receiver includes a first channel for receiving a first channel voltage, and a second channel for receiving a second channel voltage. The common mode capacitor provides a common mode potential. The first switch electrically connects the first terminal resistor to the common mode capacitor, and the second switch electrically connects the second terminal resistor to the common mode capacitor. The common mode potential adjustment circuit is coupled to the first switch, the second switch and the common mode capacitor, and adjusts the common mode potential according to the first channel voltage and the second channel voltage.

Abstract: A microelectronic package includes a microelectronic element operable to output a discrete-value logic signal indicating an imminent increase in demand for current by at least some portion of the microelectronic element. An active power delivery element within the package is operable by the logic signal to increase current delivery to the microelectronic element.

Abstract: An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of an RF signal input. The detection transistors are configured with a size and for a current such that the transistors are biased in subthreshold regions of operation. The ED core is configured to variably control a bias current through the detection transistors, where the bias current is varied according to a voltage amplitude of the RF signal input to enhance a linear range of the ED while detection transistors continue to operate in subthreshold regions. A linearizer circuit may be configured to control the bias current based on feedback inputs from ED outputs. Several gain-programmable voltage amplifiers, which may include a final specialized class-AB amplifier, precede the ED core, to adapt a transmitter output voltage to an input range of the ED core, which extends the linear range of the ED.

Abstract: Circuitry (10-2) for limiting the maximum amount of current (IREF) flowing through a first electrode (DRAIN) of a first transistor (T1) includes an amplifier (14) having an output coupled by a conductor (19) to a control electrode of the first transistor and limiting circuitry (17) including reference current sensing circuitry (22, TSENSE) having a reference current source (IREF—SENSE). A reference current sensing transistor (TSENSE) has a control electrode coupled to the control electrode of the first transistor, a first electrode coupled to a terminal (20) of the reference current source, and a second electrode (SOURCE) coupled to a second electrode of the first transistor. A buffer (T2) has an input coupled to the terminal of the reference current source. The maximum amount is limited in accordance with the reference current source to prevent an increase in magnitude of voltage applied by the amplifier to the first transistor.

Abstract: A controlled current source comprises a signal input to receive a control input bus signal (D0, . . . , D[n?1]), a mapping unit (MU) with an input coupled to the signal input and an output to provide an internal control bus signal (d0, . . . , dn, Hc), a reference generator (RG) with an input coupled to the output of the mapping unit (MU) and with a low reference output to provide a low reference potential (Vgl) and with a high reference output to provide a high reference potential (Vgh), a current generating unit (CG) with a first input coupled to the output of the mapping unit (MU), a second input coupled to the output of the reference generator (RG) and an output to provide an output current (Iout) controlled by the control input bus signal (D0, . . . , D[n?1]) and the low and high reference potentials (Vgh, Vgl). Furthermore, a method for sourcing a current is provided.

Abstract: A connection device for connecting a load to a power supply, comprising at least first and second current control devices arranged in parallel between the power supply and the load, and a controller arranged to switch the current control devices on in sequence for temporally overlapping on periods.

Abstract: System and method system for regulating voltage in a portion of an integrated circuit. An integrated circuit has a voltage input and at least a portion that is less than all of the integrated circuit, which requires a local voltage level. A voltage selector establishes a target voltage for the portion. A first comparator compares the target voltage to the local voltage and generates a pull up control signal when the local voltage is below the target voltage. A second comparator compares the target voltage to the local voltage and generates a pull down control signal when the local voltage is above the target voltage. A pull up device, responsive to the pull up control signal, increases the local voltage according to the pull up control signal. A pull down device, responsive to the pull down control signal, decreases the local voltage level according to the pull down control signal.

Abstract: A semiconductor device includes: a plurality of circuit parts; a global power source; a plurality of power source supply circuits; and a plurality of local power source control circuits provided in correspondence to the plurality of circuit parts, wherein each of the plurality of power source supply circuits includes a plurality of discrete supply switches, each of the plurality of local power source control circuits includes: a delay monitor circuit having a delay path whose amount of delay changes in accordance with a change in the voltage value of the local power source, and whose output logical value changes in accordance with the amount of delay of the delay path; and a switch control circuit configured to control the number of the plurality of discrete supply switches based on the output logical value of the delay monitor circuit.

Abstract: A semiconductor device includes: a plurality of circuit parts; a global power source; a plurality of power source supply circuits; and a plurality of local power source control circuits provided in correspondence to the plurality of circuit parts, wherein each of the plurality of power source supply circuits includes a plurality of discrete supply switches, each of the plurality of local power source control circuits includes: a voltage monitor circuit; a storage circuit storing an output target characteristic value of the voltage monitor circuit; a comparator configured to compare the output characteristic value of the voltage monitor circuit and the target characteristic value; and a switch control circuit configured to control the number of the plurality of turned-on discrete supply switches based on the comparison result of the comparator.

Abstract: A reference voltage is maintained stable against disturbance noise and self-noise of an internal circuit. A reference voltage stabilizer circuit for stabilizing the reference voltage to be supplied through at least one of first or second signal lines includes a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and a subsequent-stage circuit including a resistive path connected between the first and second signal lines, and a resistive circuit inserted, between the capacitive path and the resistive path, into one of the first or second signal lines through which the reference voltage is supplied.

Abstract: Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line.

Abstract: A clamp circuit for an RFID tag includes a power supply node, a dynamic clamp coupled between the power supply node and ground, and an active clamp coupled between the power supply and ground, having a shunt combined effect for providing a clamped power supply node VDDR voltage. The dynamic clamp includes a capacitor divider circuit, a resistor coupled to the capacitor divider circuit, and an N-channel transistor coupled to the capacitor divider circuit. The active clamp includes a differential amplifier having a first input coupled to a resistor divider, a second input for receiving a reference voltage, and an output coupled to a P-channel transistor for the clamped VDDR voltage.

Abstract: A multi-hysteresis voltage controlled current source system having a variety of multi-hysteresis characteristics is provided. In the multi-hysteresis voltage controlled current source system, single-hysteresis voltage controlled current source circuits 21, 22, . . . 2N as fundamental components are connected in parallel, and a differential input voltage vid is applied to the single-hysteresis voltage controlled current source circuits 21, 22, . . . 2N, so that a plurality of discrete values of current can be output based on the single-hysteresis voltage controlled current source circuits 21, 22, . . . 2N.

Abstract: A semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a voltage generator configured to generate a test voltage, a graphene transistor configured to receive a gate-source voltage based on the test voltage, and a detector configured to detect whether the gate-source voltage is a Dirac voltage of the graphene transistor, and output a feedback signal applied to the voltage generator indicating whether the gate-source voltage is the Dirac voltage.

Abstract: In one implementation, an apparatus may include a first negative channel metal oxide semiconductor (NMOS) transistor circuit coupled to a first voltage source, a second NMOS transistor circuit coupled to the first voltage source, the second NMOS transistor circuit having a smaller channel width to channel length ratio than the first NMOS transistor circuit, a first positive channel metal oxide semiconductor (PMOS) transistor circuit coupled to a second voltage source and coupled to the second NMOS transistor circuit, and a second PMOS transistor circuit coupled to the second voltage source, the second PMOS transistor circuit having a larger channel width to channel length ratio than the first PMOS transistor circuit.