With Field-effect Transistor Patents (Class 327/546)
  • Patent number: 10734994
    Abstract: A gate control circuit includes: a transition time detection circuit configured to detect a transition time of a drain voltage of a switching transistor that is turned ON or OFF by a gate voltage corresponding to a first pulse signal and a second pulse signal; an error detection circuit configured to output an error voltage representing a difference between the transition time and a target transition time being predetermined; and a transition time control circuit configured to generate the second pulse signal on the basis of the error voltage and the first pulse signal corresponding to an input signal that instructs ON or OFF of the switching transistor.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: August 4, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Takeshi Ueno
  • Patent number: 10700678
    Abstract: A voltage driver shifts a voltage on a gate as a control terminal of a power semiconductor element in response to an ON command or an OFF command. A gate voltage detector generates a detection signal of a gate-emitter voltage. A delay signal generator generates a delay signal obtained by adding a delay time to the detection signal. A subtractor generates a voltage difference signal between the detection signal and the delay signal. When the voltage difference signal exceeds a reference voltage during an operation of turning on the power semiconductor element, a short-circuit state detector detects a hard-switching fault.
    Type: Grant
    Filed: May 30, 2016
    Date of Patent: June 30, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takeshi Horiguchi, Yasushi Nakayama
  • Patent number: 10547301
    Abstract: An inverter driver includes: a switching device; a drive circuit driving the switching device; a current detection device generating a voltage signal corresponding to a current flowing through the switching device; a noise filter removing noise superposed on the voltage signal; an excess current detection circuit outputting an excess current detection signal when the voltage signal input via the noise filter exceeds a first threshold value; and a short circuit detection circuit outputting an error signal when the excess current detection signal is input or the voltage signal input by bypassing the noise filter exceeds a second threshold value.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: January 28, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hisashi Oda, Shinji Sakai
  • Patent number: 10466732
    Abstract: A switching regulator includes a power stage circuit and a control circuit. The power stage circuit operates a high-side switch and a low-side switch therein according to a high-side signal and a low-side signal respectively to generate an inductor current flowing through an inductor therein. The adjustment signal generation circuit in the control circuit generates an adjustment level according to the high-side signal, the low-side signal, and/or the inductor current, wherein the adjustment level is switched between a reverse recovery level and an anti-latch-up level, and is electrically connected to a low-side isolation region of the low-side switch. The reverse recovery level is lower than the input voltage. The anti-latch-up level is higher than the reverse recovery level to avoid a latch-up effect.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: November 5, 2019
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chien-Yu Chen, Tsung-Yi Huang, Ting-Wei Liao
  • Patent number: 10256625
    Abstract: An input protection circuit changes the voltage of a signal to be input to an input circuit to a predetermined voltage or less and outputs the signal. The input protection circuit includes a first NMOS transistor and a second NMOS transistor. The the first NMOS transistor includes a source to which an input signal is input, a gate to which a voltage based on a first voltage is applied, and a drain that outputs the signal to the input circuit based on the input signal and the gate voltage. The second NMOS transistor includes a source and a gate to each of which the voltage based on the first voltage is applied, and a drain that outputs a second voltage to the input circuit.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: April 9, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Hidehiko Yajima, Satoru Kodaira
  • Patent number: 9601477
    Abstract: Aspects of the disclosure include an integrated circuit that includes a plurality of functional circuit cells and a plurality of inactive spare functional circuit cells. Ones of the functional circuit cells respectively includes a set of first electrically interconnected transistors that define a first logic component and a first power rail configured to carry a first supply voltage. Ones of the inactive spare functional circuit cells respectively includes a set of second electrically interconnected transistors configured to define a second logic component and a second power rail configured to carry the first supply voltage. The set of electrically interconnected transistors is interconnected through a second set of conductive lines formed in the first conductive layer. The set of second electrically interconnected transistors is electrically disconnected from the second power rail.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: March 21, 2017
    Assignee: Marvell World Trade Ltd.
    Inventors: Carol Pincu, Rami Rozenzvaig
  • Patent number: 9535102
    Abstract: A test signal supplying device includes a first external terminal, a second external terminal being applied with a predetermined electric potential, an internal load, a first terminal that is connected to the first external terminal through the internal load, a second terminal that is connected to the first external terminal without passing through the internal load, a test signal generating section that generates a test signal and supplies the test signal to the second terminal, a detecting section that detects an amplitude of the test signal, and a controlling section that measures an impedance of an external load connected to the first and second external terminals based on the detected amplitude of the test signal.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: January 3, 2017
    Assignee: Yamaha Corporation
    Inventors: Kunito Takahashi, Akihiko Toda, Tatsuya Kishii
  • Patent number: 9329649
    Abstract: A dual input single output (DISO) regulator, includes a comparator configured to receive a first and second power supply signal and to provide a first compared signal; a first switch configured to couple the first power supply source to an intermediate node, and a second switch configured to couple the second power supply source to the intermediate node; a control logic circuit, coupled to the first comparator, to the first switch, and to the second switch, and configured to receive the compared signal to control the first and the second switch in a first and second operating condition based on the compared signal. The intermediate node being biased by an intermediate power supply signal correlated to the first or second power supply signal. The DISO regulator includes a low-dropout regulator, configured to provide a regulated power supply signal based on the intermediate power supply signal.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: May 3, 2016
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Gasparini, Andrea Donadel, Stefano Ramorini
  • Patent number: 9318548
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first electrode, and a first insulating film. The semiconductor layer is provided on the semiconductor substrate. The semiconductor layer includes first-fifth regions. The first region includes a first portion and a second portion arranged with the first portion. The second region is provided in a surface of the first portion. The third region is provided between the second portion and the second region in the surface of the first portion. The fourth region is provided between the second portion and the third region in the surface of the first portion. The fifth region is provided in a surface of the fourth region. The first electrode is provided between the fifth region and the second portion on the semiconductor layer. The first insulating film is provided between the semiconductor layer and the first electrode.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: April 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasunori Iwatsu, Masahiro Inohara
  • Patent number: 9024682
    Abstract: A current generator includes first and second current generators and an output current generator. The first current generator has an output for providing a first current, the first current proportional to a difference between a first power supply voltage and a first gate-to-source voltage. The second current generator has an output for providing a second current, the second current proportional to a second gate-to-source voltage. The second gate-to-source voltage is approximately equal to the first gate-to-source voltage. The output current generator provides an output current proportional to a sum of said first current and said second current.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: May 5, 2015
    Assignee: ATI Technologies, ULC
    Inventors: Boris Krnic, James Lin
  • Patent number: 8975923
    Abstract: Apparatus and methods for a protective multiplexer, among other things, are provided. In an example, a protective multiplexer circuit can include a first switch that in a first state can be configured to couple an input of a power supply to at least one of first or second signal nodes of a passgate when a first voltage of the at least one of the first or second signal nodes is below a first limit voltage.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: March 10, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Nickole Gagne, Kenneth P. Snowdon
  • Patent number: 8866489
    Abstract: A test apparatus that tests a device under test, including a power supply section that supplies the device under test with power, a comparing section that detects a characteristic value indicating a state of the device under test and compares the characteristic value to a predetermined threshold value, a cutoff section that cuts off the power supplied from the power supply section to the device under test, based on a result of the comparison by the comparing section, and a control section that changes at least one of the threshold value of the comparing section and a detection timing at which the characteristic value is detected.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: October 21, 2014
    Assignee: Advantest Corporation
    Inventor: Shinichi Hashimoto
  • Patent number: 8786360
    Abstract: The present invention discloses a fast switching current mirror circuit and method for generating fast switching current. The circuit and method for fast switching of a current mirror with large MOSFET size will save space and current consumption.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: July 22, 2014
    Assignee: STMicroelectronics Asia Pacific PTE, Ltd.
    Inventor: Justin Ang
  • Patent number: 8766711
    Abstract: A switching circuit device has a first transistor which has a drain coupled to a high-potential terminal, a source coupled to a low-potential power supply, and, a driving circuit, which outputs, to a gate of the first transistor in response to an input control signal, a pulse having a potential higher than a threshold voltage of the first transistor and a potential of the low-potential power supply, wherein the driving circuit has a first inverter including a second transistor provided between the gate and the source of the first transistor, wherein when the first transistor changes from on to off due to the pulse, the second transistor conducts and short-circuits the gate and the source of the first transistor.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: July 1, 2014
    Assignee: Transphorm Japan, Inc.
    Inventor: Yoshihiro Takemae
  • Patent number: 8745411
    Abstract: A data processing apparatus includes a volatile memory, a random number generator adapted for generating random numbers from which one or more keys are generated, and a memory encryption unit (MEU). The MEU is configured to receive an N-bit block of data and to divide the N-bit block of data into two more sub-blocks of data, where each sub-block contains fewer than N-bits. The MEU is further configured to encrypt each sub-block of data using the one more keys, to combine the encrypted sub-blocks into an N-bit block of encrypted data, and to write the encrypted N-bit block of data to the volatile memory.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: June 3, 2014
    Assignee: Broadcom Corporation
    Inventors: Love Kothari, Lawrence J. Madar, III
  • Patent number: 8665008
    Abstract: Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: March 4, 2014
    Assignee: Elpida Memory, Inc.
    Inventors: Hideyuki Yokou, Isao Nakamura, Manabu Ishimatsu
  • Patent number: 8653597
    Abstract: Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hayden C. Cranford, Jr., Terence B. Hook
  • Patent number: 8614599
    Abstract: One embodiment of an integrated circuit includes a local circuit block, a first power supply for supplying power to a first terminal of the local circuit block, a second power supply for supplying power to a second terminal of the local circuit block, a first transmission gate coupled between the second terminal of the local circuit block and a current path from the second power supply, and a second transmission gate coupled between the current path from the second power supply and a gate of a p-type metal-oxide-semiconductor (PMOS) transistor in the first transmission gate, the second transmission gate including a single transistor.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: December 24, 2013
    Assignee: Xilinx, Inc.
    Inventors: Adebabay M. Bekele, Aman Sewani, Xuewen Jiang
  • Patent number: 8421528
    Abstract: A semiconductor integrated circuit includes a first voltage line to which a first ground voltage is applied, a second voltage line to which a second ground voltage is applied, a third voltage line to which a first power supply voltage is applied, and a coupling unit including a MOS transistor having a source coupled to the first voltage line, a drain coupled to the second voltage line, and a gate coupled to the third voltage line.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: April 16, 2013
    Assignee: SK Hynix Inc.
    Inventors: Hyun Seok Kim, Jun Ho Lee, Boo Ho Jung, Sun Ki Cho, Yang Hee Kim, Young Won Kim
  • Patent number: 8416004
    Abstract: A circuit module includes: control object circuits which start operations when a power supply voltage reaches a target value; a current sink circuit which consumes a current supplied thereto; and a power supply activation control unit which increases the current flowing into the current sink circuit at a predetermined rate before starting the operations of the control object circuits and which starts the operations of the control object circuits and simultaneously blocks the supply of the current to the current sink circuit in a case where an amount of the current flowing into the current sink circuit is equivalent to an amount of current to be increased by starting the operations of the control object circuits when the power supply voltage reaches the target value.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: April 9, 2013
    Assignee: Fujitsu Optical Components Limited
    Inventors: Masaru Akizawa, Kazuyoshi Shimizu
  • Patent number: 8416009
    Abstract: Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: April 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Hayden C. Cranford, Jr., Terence B. Hook
  • Patent number: 8193855
    Abstract: A semiconductor device includes an internal circuit; a plurality of power switches arranged in parallel configured to supply a current to the internal circuit; an instruction circuit configured to output a instruction signal for controlling power supply to the internal circuit; a variation detection circuit configured to detect the current and to output a detection result; and a logic circuit configured to control a timing when the plurality of power switches becomes a conducting state in accordance with the detection result and the instruction signal.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: June 5, 2012
    Assignee: Fujitsu Limited
    Inventor: Kenichi Kawasaki
  • Patent number: 8145933
    Abstract: A power control circuit includes an input/output controller hub (ICH), and first to third metal-oxide-semiconductor field effect transistors (MOSFETs). A drain of the first MOSFET is connected to a standby power source through a first resistor. A gate of the first MOSFET is connected to a sleep control terminal of the ICH through a second resistor. A drain of the second MOSFET is connected to the drain of the first MOSFET through a third resistor. A gate of the second MOSFET is connected to a general purpose input/output terminal of the ICH through a fourth resistor. A source of the third MOSFET is connected to the standby power source. A gate of the third MOSFET is connected to the drain of the second MOSFET. A drain of the third MOSFET is connected to a power terminal of an onboard network interface card.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: March 27, 2012
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventor: Chun-Fang Xi
  • Patent number: 8051313
    Abstract: An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: November 1, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Bixia Li, Hugh Mair, Minh Chau, Alice Wang, Uming Ko
  • Patent number: 8026757
    Abstract: A current mirror circuit is provided with a first current mirror including first and second mirror transistors sharing a common control terminal; the first mirror transistor has a conduction terminal for receiving, during a first operating condition, a first reference current, and the second mirror transistor has a respective conduction terminal for providing, during the first operating condition, a mirrored current based on the first reference current. The current mirror circuit is provided with a switching stage operable to connect the control terminal to the conduction terminal of the first mirror transistor during the first operating condition, and to disconnect the control terminal from the same conduction terminal of the first mirror transistor, and either letting it substantially float or connecting it to a reference voltage, during a second operating condition, in particular a condition of stand-by.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: September 27, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ferdinando Bedeschi, Claudio Resta
  • Publication number: 20110227637
    Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.
    Type: Application
    Filed: February 15, 2011
    Publication date: September 22, 2011
    Inventors: Michael A. Stuber, Christopher N. Brindle, Dylan J. Kelly, Clint L. Kemerling, George P. Imthurn, Mark L. Burgener, Alexander Dribinsky, Tae Youn Kim
  • Patent number: 7990208
    Abstract: In a semiconductor integrated circuit device, a circuit block has a first MOS transistor, and a leakage current control circuit having a second MOS transistor and a current source, a source and drain circuit of the second MOS transistor is formed between the power supply line of the circuit block and a voltage point where operating voltage is supplied. This current source is connected to the power supply line and in a first state, the power supply line is driven to a first voltage by the second MOS transistor. In a second state, the power supply line is controlled at a second voltage by current flow in the current source and, the voltage applied across the source and drain of the first MOS transistor in the second state is smaller than the voltage applied across the source and drain of the first MOS transistor in the first state.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: August 2, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Mizuno, Kiyoo Itoh
  • Patent number: 7944267
    Abstract: A leakage current measurement circuit measuring a substrate leakage current and a gate leakage current in response to a variation in the size of an MOS transistor and a leakage current comparison circuit judging which one of the substrate leakage current and the gate leakage current is dominant. The leakage current measurement circuit includes a charge supply, a leakage current generator and a detection signal generator. The leakage current comparison circuit includes a charge supply, a leakage current comparator and a detection signal generator.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: May 17, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Gun-Ok Jung
  • Patent number: 7911259
    Abstract: A voltage switching circuit selects a voltage from among a plurality of input voltages in response to a selection signal and outputs the selected voltage from an output terminal. The voltage switching circuit includes a first PMOS transistor that outputs a power supply voltage for operating a logic circuit of an output terminal. A second PMOS transistor outputs a first voltage higher than the power supply voltage to the output terminal. A third PMOS transistor outputs a second voltage lower than the power supply voltage to the output terminal. A well potential control section controls well voltages of the first and third transistors to be the power supply voltage where the power supply voltage and the second voltage are output to the output terminal, and controls the well voltages of the first and third transistors to be the first voltage where the first voltage is output to the output terminal.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: March 22, 2011
    Assignee: Seiko Instruments Inc.
    Inventor: Tomohiro Oka
  • Patent number: 7911263
    Abstract: A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: March 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jong-Ru Guo, Louis Lu-Chen Hsu, Rajiv Vasant Joshi, Ping-Chuan Wang, Zhijian Yang
  • Patent number: 7886158
    Abstract: A system and method for remote copy of encrypted data where a primary storage system receives data, encrypts the data with a first cryptographic method, and stores the encrypted data. A secondary storage system connected to the primary storage system receives and stores a remote copy of the encrypted data. When a block of the stored encrypted data is converted using a second cryptographic method, the converted block and a pointer containing an address at which the conversion has finished is transferred to the second storage system and stored. The pointer is incremented for each block converted. A backup copy of the first cryptographic method and the second cryptographic method are stored at a backup system remote from the primary storage system. If the primary system fails, the backup system can decrypt the data using the first cryptographic method or the second cryptographic method based on the pointer.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: February 8, 2011
    Assignee: Hitachi, Ltd.
    Inventor: Nobuyuki Osaki
  • Patent number: 7863971
    Abstract: A configurable power controller and method for controlling power of a macro circuit block, such as a memory circuit, in multiple power modes is described to help minimize power consumption of the macro circuit block when the application environment for the macro circuit block is in a lower power mode than during its normal power mode.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: January 4, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventors: Anup Nayak, Sanjay Kumar Sancheti, Shailja Garg
  • Publication number: 20100309743
    Abstract: In step S508, it is determined whether or not a power low signal SRC_LOSS outputted from the data latch is change. Generally Speaking, the power low signal SRC_LOSS outputted from the data latch would be changed according to the state of the power voltage of the power input terminal. When the power voltage of the power input terminal is charged/discharged to the common voltage, the power low signal SRC_LOSS outputted from the data latch may be changed from the logical high voltage to the logical low voltage or from the original logical low voltage to the logical high voltage. Since the mention above is design of selectiveness, the detailed description is omitted. When the determination is positive, the step S509 is performed. When the determination is negative, the step S511 is performed to re-detect.
    Type: Application
    Filed: March 23, 2010
    Publication date: December 9, 2010
    Inventors: Ming-Hung TSAI, Lee HSIN CHOU
  • Patent number: 7847623
    Abstract: A device monitors at least one power switch which is series-mounted with a logic core between a first and a second potential. A connection point between the switch and logic core is carried to a third potential. The switch is biased by a biasing potential. The device includes a feedback control module mounted between first and second potentials which is capable of generating a set potential representative of the third potential variation. A biasing module of the power switch is mounted between the first and second potentials, and generates a biasing potential based on the set potential. The biasing potential linearly varies with the decrease of the third potential.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: December 7, 2010
    Assignee: STMicroelectronics S.A.
    Inventors: Nicolas L'Hostis, Philippe Flatresse
  • Patent number: 7847530
    Abstract: A voltage regulator is disclosed that includes first and second output transistors each outputting a current from the input terminal to the output terminal of the voltage regulator; and a control circuit part controlling the operations of the first and second output transistors to equalize a voltage proportional to an output voltage with a reference voltage. The control circuit part includes first and second error amplifier circuits each amplifying and outputting the difference between the proportional and reference voltages. The second error amplifier circuit consumes a smaller amount of current than the first error amplifier circuit. The control circuit part controls the output voltage by controlling the operations of the first and second output transistors using the first error amplifier circuit or controlling the operation of the second output transistor using the second error amplifier circuit in accordance with a control signal externally input to the control circuit part.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: December 7, 2010
    Assignee: Ricoh Company, Ltd.
    Inventor: Yoshiki Takagi
  • Patent number: 7843256
    Abstract: An internal voltage generator includes a pull-up driver to pull-up drive a supply terminal of an internal voltage, a pull-down driver to pull-down drive the supply terminal of the internal voltage, a pull-up driving control unit to turn on the pull-up driver when a first feedback voltage corresponding to the internal voltage becomes lower than a reference voltage, and a pull-down driving control unit to turn on the pull-down driver when a second feedback voltage becomes higher than the reference voltage, the second feedback voltage having a voltage level corresponding to that of the internal voltage and lower than that of the first feedback voltage.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: November 30, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chang-Ho Do
  • Patent number: 7800418
    Abstract: A first switched capacitor circuit is connected to the source of one MOS transistor of a current mirror pair configured by a pair of MOS transistors and a second switched capacitor circuit is connected to the source of the other MOS transistor. Each of the first and second switched capacitor circuits includes a capacitor and a switch connected in parallel with the capacitor and the switch is on/off-controlled based on a clock signal of a preset cycle. Each of the first and second switched capacitor circuits equivalently functions as a resistor with large resistance and a variation in the output current of the current mirror circuit based on a variation in the threshold voltages of the pair of MOS transistors can be reduced even if the power source voltage is reduced.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: September 21, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigeo Imai
  • Patent number: 7777561
    Abstract: An apparatus comprising an input current source device, a first transistor, a second transistor and a level shifter device. The input current source device may provide a input current source. The first transistor may be configured to operate in saturation for mirroring the input current source to an output current source. The first transistor may have (i) a source node connected to a supply, and (ii) a drain connected to the input current source. The second transistor may also be configured to operate in saturation. The second transistor may have (i) a gate connected to a gate of the first transistor, (ii) a source connected to the supply, and (iii) a drain configured as an output current node. The level shifter device may comprise a third transistor, a first bias current source and a second bias current source.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: August 17, 2010
    Assignee: LSI Corporation
    Inventor: Donghui Wang
  • Patent number: 7750667
    Abstract: A semiconductor integrated circuit includes a MOS logic operating by first and second voltages; a switching transistor unit disposed between a supply terminal of the first voltage or the second voltage and the MOS logic, and turned on or off in response to a control signal so as to control a supply of the first or second voltage to the MOS logic; and a fuse unit disposed between the supply terminal of the first voltage or the second voltage and the switching transistor unit, for cutting off a supply of the first or second voltage to the switching transistor unit by a selective cut based on a test result. Whereby, a product development or production difficulty or a yield decrease based on a performance drop or leakage current increase in a circuit having a power gate or MTCMOS may be improved. In addition, a product development delay caused by a mask revision required at a transistor level may be improved in a revision of an NMOS or PMOS transistor.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: July 6, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jin-Kook Jung
  • Publication number: 20100090756
    Abstract: Provided is a switched capacitor circuit which prevents leakage current by equalizing voltages at nodes where leakage current tends to flow in a sampling mode, and prevents errors in an output signal by minimizing voltage drop caused by leakage current in an integrating mode.
    Type: Application
    Filed: May 20, 2009
    Publication date: April 15, 2010
    Applicants: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventors: Hyung Dong ROH, Hyoung Joong KIM, Jeong Jin ROH, Yi Gyeong KIM, Jong Kee KWON
  • Patent number: 7692908
    Abstract: Circuits and methods for protecting polarity-sensitive components, such as light emitting diodes, electrolytic capacitors or integrated circuits, operating from a DC current source including a DC motor, an inductor or relay having a positive terminal and a negative terminal for receiving current from the current source, a protection diode connected parallel with the positive and negative terminals of the motor in a reverse bias configuration, at least one polarity-sensitive component connected in parallel with the protection diode and the DC motor, and a polarity protection transistor connected either between the nominally positive current source terminal and the positive motor terminal, or between the nominally negative current source terminal and the negative motor terminal.
    Type: Grant
    Filed: January 2, 2008
    Date of Patent: April 6, 2010
    Assignee: GLJ, LLC
    Inventors: Harry Chen, Eric Junkel
  • Patent number: 7694243
    Abstract: A system for protecting a weak device operating in micro-electronic circuit and a design structure including the system embodied in a machine readable medium are disclosed. The system includes a high voltage power supply from high voltage overstressing prevents the weak device from failing during power-up, power-down, and when a low voltage power supply in a multiple power supply system is absent. The system further includes a low voltage power supply detection circuit configured to detect circuit power-up, circuit power-down, and when the low voltage power supply is absent, and generate a control signal upon detection. The system further includes a controlled current mirror device configured to provide a trickle current to maintain a conduction channel in the weak device in response to the control signal received from the low voltage power supply detection circuit during circuit power-up, circuit power-down, and when the low voltage power supply is absent.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: April 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Hibourahima Camara, Louis C. Hsu, James D. Rockrohr, Karl D. Selander, Huihao Xu, Steven J. Zier
  • Patent number: 7661001
    Abstract: In an apparatus for encrypting an information signal into an encryption-resultant signal, a first encryption key peculiar to the present apparatus is generated. Key information is read out from a replaceable recording medium. A decision is made as to whether or not the read-out key information has been generated by an apparatus different from the present apparatus. A second encryption key is generated in response to the read-out key information when it is decided that the read-out key information has been generated by an apparatus different from the present apparatus. One is selected from the first encryption key and the second encryption key as a final encryption key. An information signal is encrypted in response to the final encryption key.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: February 9, 2010
    Assignee: Victor Company of Japan, Ltd.
    Inventor: Seiji Higurashi
  • Patent number: 7649405
    Abstract: A leakage current control circuit with a single low voltage power supply is provided. The circuit includes a first power supply line, a second power supply line, a ground line, a high voltage generating circuit, a power transistor and a control circuit. The high voltage generating circuit generates a voltage in response to an internal sleep signal. The gate electrode of the power transistor is connected to the output of the high-voltage generating circuit such that the power transistor is controlled by the high voltage generating circuit. When the power transistor turns on, the circuit is in operation mode; when the power transistor is off, the circuit is in sleep mode. The control circuit connects to the first power line, the second power line, and the ground line to output the internal sleep signal in response to the sleep signal.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: January 19, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Jinn-Shyan Wang, Hung-Yu Li
  • Patent number: 7649406
    Abstract: A short-circuit charge-sharing technique which allows charge-sharing between two or more circuits with a simple shorting transistor controlled to achieve the desired operating voltage levels. The shorting transistor which can be either a P-channel Metal Oxide Semiconductor (PMOS) or an N-channel Metal Oxide Semiconductor (NMOS) device and can be controlled utilizing the same clock that enables the drive of the signals between which charge-sharing occurs. In operation, the desired operating voltage levels can be regulated by increasing and decreasing the pulse width of the control circuit output to the gate of the shorting transistor.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: January 19, 2010
    Assignees: United Memories, Inc., Sony Corporation
    Inventors: Michael C. Parris, Kim C. Hardee
  • Patent number: 7639068
    Abstract: A semiconductor integrated circuit device comprises: a circuit block, a first MOS transistor, a first power line, a second power line, a third power line, and a drive circuit. The first MOS transistor is connected between the first and second power lines. The circuit block is connected between the second and third power lines. The drive circuit controls a voltage supplied to a gate of the first MOS transistor. The first MOS transistor is off in a standby state and on in an operation state. During a shift from the standby state to the operation state and a shift from the operation state to the standby state, the drive circuit changes the voltage supplied to the gate of the first MOS transistor at a first rate, and then, changes the voltage supplied to the gate of the first MOS transistor at a second rate faster than the first rate.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: December 29, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Hiroyuki Mizuno, Kiyoo Itoh
  • Patent number: 7598802
    Abstract: A semiconductor integrated circuit apparatus and an electronic apparatus having a power control function configured from power control MOS transistors such that leakage current and on-resistance at the time of cut-off is sufficiently small in actual use. The semiconductor integrated circuit apparatus includes a CMOS logic circuit, a first pseudo power supply line connected to a high potential side power supply terminal of the CMOS logic circuit, a second pseudo power supply line connected to a low potential side power supply terminal of the CMOS logic circuit, and a power control NchMOS transistor connected across the second pseudo power supply line and a low potential side power supply line, with the substrate and gate of the power control NchMOS transistor being electrically connected. The gate and the substrate may also be connected via a current limiter utilizing a source follower of a depletion type NchMOS transistor.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: October 6, 2009
    Assignee: Panasonic Corporation
    Inventor: Minoru Ito
  • Publication number: 20090243714
    Abstract: A power noise immunity circuit includes a unidirectional device and a switch both connected between a power input terminal and a power output terminal, and a noise detector to control the switch. The power input terminal is for being connected to an external voltage source, and the power output terminal is for being connected to the circuit of an IC. The switch is normally closed and is opened by the noise detector if the noise detector detects power noise at the power input terminal. The power noise immunity circuit thus prevents the IC from power breakdown and provides a stable voltage thereto.
    Type: Application
    Filed: March 24, 2009
    Publication date: October 1, 2009
    Inventors: Ming-Chun Chou, Chun-Chung Huang
  • Publication number: 20090174470
    Abstract: A latch-up protection device is provided. The latch-up protection device includes a first transistor, a detection module, and a processing module. The first transistor includes a first source/drain coupled to a pad, a body and a second source/drain coupled to a first voltage, and a gate. The detection module is adapted for detecting a terminal voltage between the first source/drain and the second source/drain of the first transistor, and generating a first signal when the terminal voltage is greater than a trigger voltage. The processing module is coupled between the detection module and the gate of the first transistor, for conducting a logic processing to the first signal, and generating an enable signal to the gate of the first transistor to conduct the first transistor.
    Type: Application
    Filed: January 9, 2008
    Publication date: July 9, 2009
    Applicant: WINBOND ELECTRONICS CORP.
    Inventor: Jen-Chou Tseng
  • Patent number: RE42494
    Abstract: A voltage level shifting circuit (FIG. 4) has a plurality of PMOS transistors M1, M2, M3 connected in parallel for respectively driving a capacitive load CL with a selected different voltage level V1, V2 or V3. Transistors M1, M2, M3 are controlled so that one of them is placed in the ON condition, with the others in the OFF condition, to connect one of the voltages V1, V2 or V3 to charge the load CL. The largest voltage transistor M3 has its body connected to its source. The lower voltage transistors M1, M2 have their bodies respectively connected to switches S1, S2, which connect the bodies to the sources when the transistors are placed in the ON condition and connect the bodies to the highest voltage V3 when the transistors are placed in the OFF condition.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: June 28, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Ross E. Teggatz