Abstract: A transmission line has a first conductor layer extending in a first direction, a second conductor layer disposed on a side of a first surface of the first conductor layer via a first dielectric layer, the second conductor layer extending in the first direction, and a third conductor layer disposed on a side of a second surface of the first conductor layer opposite to the first surface, via a second dielectric layer, the third conductor layer extending in the first direction, wherein a width, in a second direction intersecting the first direction, of each of the second conductor layer and the third conductor layer is different at a plurality of locations in the first direction, and the first conductor layer, the second conductor layer, and the third conductor layer at least partially overlap each other in a plan view from a normal direction of the first surface.

Abstract: A transmission line has a first conductor layer extending in a first direction, a second conductor layer disposed on a side of a first surface of the first conductor layer via a first dielectric layer, the second conductor layer extending in the first direction, and a third conductor layer disposed on a side of a second surface of the first conductor layer opposite to the first surface, via a second dielectric layer, the third conductor layer extending in the first direction, wherein a width, in a second direction intersecting the first direction, of each of the second conductor layer and the third conductor layer is different at a plurality of locations in the first direction, and the first conductor layer, the second conductor layer, and the third conductor layer at least partially overlap each other in a plan view from a normal direction of the first surface.

Abstract: An apparatus includes a power semiconductor switch, a driver circuit configured to drive a control terminal of the power semiconductor switch, and a control circuit configured to apply a control signal to the driver circuit responsive to a comparison of a reference voltage to a voltage at the control terminal of the semiconductor switch. In some embodiments, the power semiconductor switch may include a field effect transistor (FET), such as a wide bandgap silicon carbide (SiC) MOSFET. The control terminal may include a gate terminal of the FET, and the voltage at the control terminal may include a gate voltage.

Abstract: Methods, systems, and devices for back-bias optimization are described. An apparatus, such as an electronic apparatus, may include a first substrate region and a second substrate region. The apparatus may also include a voltage generator that is disposed on the first substrate region and that includes an output terminal coupled with a conductive path. The apparatus may also include a set of clamp circuits disposed on the second substrate region. The set of clamp circuits may be configured selectively couple the conductive path with a voltage supply.

Abstract: Systems, methods, circuits, devices, and apparatus including computer-readable mediums for managing startups of bandgap reference circuits in memory systems, e.g., non-volatile memory systems.

Abstract: The invention relates to a method for operating a multiphase electrical machine (2) in the event of a fault, wherein the electrical machine (2) is driven with the aid of a driver circuit (3), wherein the driver circuit (3) has half-bridge circuits (31), each associated with a phase (U, V, W), and bridge paths (32) for connecting or disconnecting predetermined voltage potentials to/from the respective phases (U, V, W) of the electrical machine (2), wherein one or more of the bridge paths (32) are operated according to a first fault operating mode if a fault is detected, wherein, in the first fault operating mode, the one or more bridge paths (32) are controlled in such a manner that said paths connect a first of the predetermined voltage potentials to the phase (U, V, W) via a predetermined electrical resistor.

Abstract: A semiconductor memory device, which can reduce consuming power and perform a power-off operation correctly, is provided. A flash memory of the invention includes: a low-power-voltage detection circuit detecting that a supply voltage drops to a given voltage; a high-accuracy voltage detection circuit detecting that the supply voltage drops to the given voltage; and a controller selecting the high-accuracy voltage detection circuit when an internal circuit is in an operation state, selecting the low-power-voltage detection circuit when the internal circuit is in a standby state, and performing a power-off operation in response to a detection result of the low-power-voltage detection circuit or the high-accuracy voltage detection circuit.

Abstract: A gate control circuit includes: a transition time detection circuit configured to detect a transition time of a drain voltage of a switching transistor that is turned ON or OFF by a gate voltage corresponding to a first pulse signal and a second pulse signal; an error detection circuit configured to output an error voltage representing a difference between the transition time and a target transition time being predetermined; and a transition time control circuit configured to generate the second pulse signal on the basis of the error voltage and the first pulse signal corresponding to an input signal that instructs ON or OFF of the switching transistor.

Abstract: A voltage driver shifts a voltage on a gate as a control terminal of a power semiconductor element in response to an ON command or an OFF command. A gate voltage detector generates a detection signal of a gate-emitter voltage. A delay signal generator generates a delay signal obtained by adding a delay time to the detection signal. A subtractor generates a voltage difference signal between the detection signal and the delay signal. When the voltage difference signal exceeds a reference voltage during an operation of turning on the power semiconductor element, a short-circuit state detector detects a hard-switching fault.

Abstract: An inverter driver includes: a switching device; a drive circuit driving the switching device; a current detection device generating a voltage signal corresponding to a current flowing through the switching device; a noise filter removing noise superposed on the voltage signal; an excess current detection circuit outputting an excess current detection signal when the voltage signal input via the noise filter exceeds a first threshold value; and a short circuit detection circuit outputting an error signal when the excess current detection signal is input or the voltage signal input by bypassing the noise filter exceeds a second threshold value.

Abstract: A switching regulator includes a power stage circuit and a control circuit. The power stage circuit operates a high-side switch and a low-side switch therein according to a high-side signal and a low-side signal respectively to generate an inductor current flowing through an inductor therein. The adjustment signal generation circuit in the control circuit generates an adjustment level according to the high-side signal, the low-side signal, and/or the inductor current, wherein the adjustment level is switched between a reverse recovery level and an anti-latch-up level, and is electrically connected to a low-side isolation region of the low-side switch. The reverse recovery level is lower than the input voltage. The anti-latch-up level is higher than the reverse recovery level to avoid a latch-up effect.

Abstract: An input protection circuit changes the voltage of a signal to be input to an input circuit to a predetermined voltage or less and outputs the signal. The input protection circuit includes a first NMOS transistor and a second NMOS transistor. The the first NMOS transistor includes a source to which an input signal is input, a gate to which a voltage based on a first voltage is applied, and a drain that outputs the signal to the input circuit based on the input signal and the gate voltage. The second NMOS transistor includes a source and a gate to each of which the voltage based on the first voltage is applied, and a drain that outputs a second voltage to the input circuit.

Abstract: Aspects of the disclosure include an integrated circuit that includes a plurality of functional circuit cells and a plurality of inactive spare functional circuit cells. Ones of the functional circuit cells respectively includes a set of first electrically interconnected transistors that define a first logic component and a first power rail configured to carry a first supply voltage. Ones of the inactive spare functional circuit cells respectively includes a set of second electrically interconnected transistors configured to define a second logic component and a second power rail configured to carry the first supply voltage. The set of electrically interconnected transistors is interconnected through a second set of conductive lines formed in the first conductive layer. The set of second electrically interconnected transistors is electrically disconnected from the second power rail.

Abstract: A test signal supplying device includes a first external terminal, a second external terminal being applied with a predetermined electric potential, an internal load, a first terminal that is connected to the first external terminal through the internal load, a second terminal that is connected to the first external terminal without passing through the internal load, a test signal generating section that generates a test signal and supplies the test signal to the second terminal, a detecting section that detects an amplitude of the test signal, and a controlling section that measures an impedance of an external load connected to the first and second external terminals based on the detected amplitude of the test signal.

Abstract: A dual input single output (DISO) regulator, includes a comparator configured to receive a first and second power supply signal and to provide a first compared signal; a first switch configured to couple the first power supply source to an intermediate node, and a second switch configured to couple the second power supply source to the intermediate node; a control logic circuit, coupled to the first comparator, to the first switch, and to the second switch, and configured to receive the compared signal to control the first and the second switch in a first and second operating condition based on the compared signal. The intermediate node being biased by an intermediate power supply signal correlated to the first or second power supply signal. The DISO regulator includes a low-dropout regulator, configured to provide a regulated power supply signal based on the intermediate power supply signal.

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first electrode, and a first insulating film. The semiconductor layer is provided on the semiconductor substrate. The semiconductor layer includes first-fifth regions. The first region includes a first portion and a second portion arranged with the first portion. The second region is provided in a surface of the first portion. The third region is provided between the second portion and the second region in the surface of the first portion. The fourth region is provided between the second portion and the third region in the surface of the first portion. The fifth region is provided in a surface of the fourth region. The first electrode is provided between the fifth region and the second portion on the semiconductor layer. The first insulating film is provided between the semiconductor layer and the first electrode.

Abstract: A current generator includes first and second current generators and an output current generator. The first current generator has an output for providing a first current, the first current proportional to a difference between a first power supply voltage and a first gate-to-source voltage. The second current generator has an output for providing a second current, the second current proportional to a second gate-to-source voltage. The second gate-to-source voltage is approximately equal to the first gate-to-source voltage. The output current generator provides an output current proportional to a sum of said first current and said second current.

Abstract: Apparatus and methods for a protective multiplexer, among other things, are provided. In an example, a protective multiplexer circuit can include a first switch that in a first state can be configured to couple an input of a power supply to at least one of first or second signal nodes of a passgate when a first voltage of the at least one of the first or second signal nodes is below a first limit voltage.

Abstract: A test apparatus that tests a device under test, including a power supply section that supplies the device under test with power, a comparing section that detects a characteristic value indicating a state of the device under test and compares the characteristic value to a predetermined threshold value, a cutoff section that cuts off the power supplied from the power supply section to the device under test, based on a result of the comparison by the comparing section, and a control section that changes at least one of the threshold value of the comparing section and a detection timing at which the characteristic value is detected.

Abstract: The present invention discloses a fast switching current mirror circuit and method for generating fast switching current. The circuit and method for fast switching of a current mirror with large MOSFET size will save space and current consumption.

Abstract: A switching circuit device has a first transistor which has a drain coupled to a high-potential terminal, a source coupled to a low-potential power supply, and, a driving circuit, which outputs, to a gate of the first transistor in response to an input control signal, a pulse having a potential higher than a threshold voltage of the first transistor and a potential of the low-potential power supply, wherein the driving circuit has a first inverter including a second transistor provided between the gate and the source of the first transistor, wherein when the first transistor changes from on to off due to the pulse, the second transistor conducts and short-circuits the gate and the source of the first transistor.

Abstract: A data processing apparatus includes a volatile memory, a random number generator adapted for generating random numbers from which one or more keys are generated, and a memory encryption unit (MEU). The MEU is configured to receive an N-bit block of data and to divide the N-bit block of data into two more sub-blocks of data, where each sub-block contains fewer than N-bits. The MEU is further configured to encrypt each sub-block of data using the one more keys, to combine the encrypted sub-blocks into an N-bit block of encrypted data, and to write the encrypted N-bit block of data to the volatile memory.

Abstract: Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line.

Abstract: Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.

Abstract: One embodiment of an integrated circuit includes a local circuit block, a first power supply for supplying power to a first terminal of the local circuit block, a second power supply for supplying power to a second terminal of the local circuit block, a first transmission gate coupled between the second terminal of the local circuit block and a current path from the second power supply, and a second transmission gate coupled between the current path from the second power supply and a gate of a p-type metal-oxide-semiconductor (PMOS) transistor in the first transmission gate, the second transmission gate including a single transistor.

Abstract: A semiconductor integrated circuit includes a first voltage line to which a first ground voltage is applied, a second voltage line to which a second ground voltage is applied, a third voltage line to which a first power supply voltage is applied, and a coupling unit including a MOS transistor having a source coupled to the first voltage line, a drain coupled to the second voltage line, and a gate coupled to the third voltage line.

Abstract: Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.

Abstract: A circuit module includes: control object circuits which start operations when a power supply voltage reaches a target value; a current sink circuit which consumes a current supplied thereto; and a power supply activation control unit which increases the current flowing into the current sink circuit at a predetermined rate before starting the operations of the control object circuits and which starts the operations of the control object circuits and simultaneously blocks the supply of the current to the current sink circuit in a case where an amount of the current flowing into the current sink circuit is equivalent to an amount of current to be increased by starting the operations of the control object circuits when the power supply voltage reaches the target value.

Abstract: A semiconductor device includes an internal circuit; a plurality of power switches arranged in parallel configured to supply a current to the internal circuit; an instruction circuit configured to output a instruction signal for controlling power supply to the internal circuit; a variation detection circuit configured to detect the current and to output a detection result; and a logic circuit configured to control a timing when the plurality of power switches becomes a conducting state in accordance with the detection result and the instruction signal.

Abstract: A power control circuit includes an input/output controller hub (ICH), and first to third metal-oxide-semiconductor field effect transistors (MOSFETs). A drain of the first MOSFET is connected to a standby power source through a first resistor. A gate of the first MOSFET is connected to a sleep control terminal of the ICH through a second resistor. A drain of the second MOSFET is connected to the drain of the first MOSFET through a third resistor. A gate of the second MOSFET is connected to a general purpose input/output terminal of the ICH through a fourth resistor. A source of the third MOSFET is connected to the standby power source. A gate of the third MOSFET is connected to the drain of the second MOSFET. A drain of the third MOSFET is connected to a power terminal of an onboard network interface card.

Abstract: An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.

Abstract: A current mirror circuit is provided with a first current mirror including first and second mirror transistors sharing a common control terminal; the first mirror transistor has a conduction terminal for receiving, during a first operating condition, a first reference current, and the second mirror transistor has a respective conduction terminal for providing, during the first operating condition, a mirrored current based on the first reference current. The current mirror circuit is provided with a switching stage operable to connect the control terminal to the conduction terminal of the first mirror transistor during the first operating condition, and to disconnect the control terminal from the same conduction terminal of the first mirror transistor, and either letting it substantially float or connecting it to a reference voltage, during a second operating condition, in particular a condition of stand-by.

Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.

Abstract: In a semiconductor integrated circuit device, a circuit block has a first MOS transistor, and a leakage current control circuit having a second MOS transistor and a current source, a source and drain circuit of the second MOS transistor is formed between the power supply line of the circuit block and a voltage point where operating voltage is supplied. This current source is connected to the power supply line and in a first state, the power supply line is driven to a first voltage by the second MOS transistor. In a second state, the power supply line is controlled at a second voltage by current flow in the current source and, the voltage applied across the source and drain of the first MOS transistor in the second state is smaller than the voltage applied across the source and drain of the first MOS transistor in the first state.

Abstract: A leakage current measurement circuit measuring a substrate leakage current and a gate leakage current in response to a variation in the size of an MOS transistor and a leakage current comparison circuit judging which one of the substrate leakage current and the gate leakage current is dominant. The leakage current measurement circuit includes a charge supply, a leakage current generator and a detection signal generator. The leakage current comparison circuit includes a charge supply, a leakage current comparator and a detection signal generator.

Abstract: A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels.

Abstract: A voltage switching circuit selects a voltage from among a plurality of input voltages in response to a selection signal and outputs the selected voltage from an output terminal. The voltage switching circuit includes a first PMOS transistor that outputs a power supply voltage for operating a logic circuit of an output terminal. A second PMOS transistor outputs a first voltage higher than the power supply voltage to the output terminal. A third PMOS transistor outputs a second voltage lower than the power supply voltage to the output terminal. A well potential control section controls well voltages of the first and third transistors to be the power supply voltage where the power supply voltage and the second voltage are output to the output terminal, and controls the well voltages of the first and third transistors to be the first voltage where the first voltage is output to the output terminal.

Abstract: A system and method for remote copy of encrypted data where a primary storage system receives data, encrypts the data with a first cryptographic method, and stores the encrypted data. A secondary storage system connected to the primary storage system receives and stores a remote copy of the encrypted data. When a block of the stored encrypted data is converted using a second cryptographic method, the converted block and a pointer containing an address at which the conversion has finished is transferred to the second storage system and stored. The pointer is incremented for each block converted. A backup copy of the first cryptographic method and the second cryptographic method are stored at a backup system remote from the primary storage system. If the primary system fails, the backup system can decrypt the data using the first cryptographic method or the second cryptographic method based on the pointer.

Abstract: A configurable power controller and method for controlling power of a macro circuit block, such as a memory circuit, in multiple power modes is described to help minimize power consumption of the macro circuit block when the application environment for the macro circuit block is in a lower power mode than during its normal power mode.

Abstract: In step S508, it is determined whether or not a power low signal SRC_LOSS outputted from the data latch is change. Generally Speaking, the power low signal SRC_LOSS outputted from the data latch would be changed according to the state of the power voltage of the power input terminal. When the power voltage of the power input terminal is charged/discharged to the common voltage, the power low signal SRC_LOSS outputted from the data latch may be changed from the logical high voltage to the logical low voltage or from the original logical low voltage to the logical high voltage. Since the mention above is design of selectiveness, the detailed description is omitted. When the determination is positive, the step S509 is performed. When the determination is negative, the step S511 is performed to re-detect.

Abstract: A device monitors at least one power switch which is series-mounted with a logic core between a first and a second potential. A connection point between the switch and logic core is carried to a third potential. The switch is biased by a biasing potential. The device includes a feedback control module mounted between first and second potentials which is capable of generating a set potential representative of the third potential variation. A biasing module of the power switch is mounted between the first and second potentials, and generates a biasing potential based on the set potential. The biasing potential linearly varies with the decrease of the third potential.

Abstract: A voltage regulator is disclosed that includes first and second output transistors each outputting a current from the input terminal to the output terminal of the voltage regulator; and a control circuit part controlling the operations of the first and second output transistors to equalize a voltage proportional to an output voltage with a reference voltage. The control circuit part includes first and second error amplifier circuits each amplifying and outputting the difference between the proportional and reference voltages. The second error amplifier circuit consumes a smaller amount of current than the first error amplifier circuit. The control circuit part controls the output voltage by controlling the operations of the first and second output transistors using the first error amplifier circuit or controlling the operation of the second output transistor using the second error amplifier circuit in accordance with a control signal externally input to the control circuit part.

Abstract: An internal voltage generator includes a pull-up driver to pull-up drive a supply terminal of an internal voltage, a pull-down driver to pull-down drive the supply terminal of the internal voltage, a pull-up driving control unit to turn on the pull-up driver when a first feedback voltage corresponding to the internal voltage becomes lower than a reference voltage, and a pull-down driving control unit to turn on the pull-down driver when a second feedback voltage becomes higher than the reference voltage, the second feedback voltage having a voltage level corresponding to that of the internal voltage and lower than that of the first feedback voltage.

Abstract: A first switched capacitor circuit is connected to the source of one MOS transistor of a current mirror pair configured by a pair of MOS transistors and a second switched capacitor circuit is connected to the source of the other MOS transistor. Each of the first and second switched capacitor circuits includes a capacitor and a switch connected in parallel with the capacitor and the switch is on/off-controlled based on a clock signal of a preset cycle. Each of the first and second switched capacitor circuits equivalently functions as a resistor with large resistance and a variation in the output current of the current mirror circuit based on a variation in the threshold voltages of the pair of MOS transistors can be reduced even if the power source voltage is reduced.

Abstract: An apparatus comprising an input current source device, a first transistor, a second transistor and a level shifter device. The input current source device may provide a input current source. The first transistor may be configured to operate in saturation for mirroring the input current source to an output current source. The first transistor may have (i) a source node connected to a supply, and (ii) a drain connected to the input current source. The second transistor may also be configured to operate in saturation. The second transistor may have (i) a gate connected to a gate of the first transistor, (ii) a source connected to the supply, and (iii) a drain configured as an output current node. The level shifter device may comprise a third transistor, a first bias current source and a second bias current source.

Abstract: A semiconductor integrated circuit includes a MOS logic operating by first and second voltages; a switching transistor unit disposed between a supply terminal of the first voltage or the second voltage and the MOS logic, and turned on or off in response to a control signal so as to control a supply of the first or second voltage to the MOS logic; and a fuse unit disposed between the supply terminal of the first voltage or the second voltage and the switching transistor unit, for cutting off a supply of the first or second voltage to the switching transistor unit by a selective cut based on a test result. Whereby, a product development or production difficulty or a yield decrease based on a performance drop or leakage current increase in a circuit having a power gate or MTCMOS may be improved. In addition, a product development delay caused by a mask revision required at a transistor level may be improved in a revision of an NMOS or PMOS transistor.

Abstract: Provided is a switched capacitor circuit which prevents leakage current by equalizing voltages at nodes where leakage current tends to flow in a sampling mode, and prevents errors in an output signal by minimizing voltage drop caused by leakage current in an integrating mode.

Abstract: Circuits and methods for protecting polarity-sensitive components, such as light emitting diodes, electrolytic capacitors or integrated circuits, operating from a DC current source including a DC motor, an inductor or relay having a positive terminal and a negative terminal for receiving current from the current source, a protection diode connected parallel with the positive and negative terminals of the motor in a reverse bias configuration, at least one polarity-sensitive component connected in parallel with the protection diode and the DC motor, and a polarity protection transistor connected either between the nominally positive current source terminal and the positive motor terminal, or between the nominally negative current source terminal and the negative motor terminal.

Abstract: A system for protecting a weak device operating in micro-electronic circuit and a design structure including the system embodied in a machine readable medium are disclosed. The system includes a high voltage power supply from high voltage overstressing prevents the weak device from failing during power-up, power-down, and when a low voltage power supply in a multiple power supply system is absent. The system further includes a low voltage power supply detection circuit configured to detect circuit power-up, circuit power-down, and when the low voltage power supply is absent, and generate a control signal upon detection. The system further includes a controlled current mirror device configured to provide a trickle current to maintain a conduction channel in the weak device in response to the control signal received from the low voltage power supply detection circuit during circuit power-up, circuit power-down, and when the low voltage power supply is absent.

Abstract: A voltage level shifting circuit (FIG. 4) has a plurality of PMOS transistors M1, M2, M3 connected in parallel for respectively driving a capacitive load CL with a selected different voltage level V1, V2 or V3. Transistors M1, M2, M3 are controlled so that one of them is placed in the ON condition, with the others in the OFF condition, to connect one of the voltages V1, V2 or V3 to charge the load CL. The largest voltage transistor M3 has its body connected to its source. The lower voltage transistors M1, M2 have their bodies respectively connected to switches S1, S2, which connect the bodies to the sources when the transistors are placed in the ON condition and connect the bodies to the highest voltage V3 when the transistors are placed in the OFF condition.