Including Signal Protection Or Bias Preservation Patents (Class 327/545)
  • Patent number: 10491255
    Abstract: Provided a wakeup circuit of a battery sampling integrated chip in battery energy storage system. The wakeup circuit includes a power end at a power low-voltage side, an optocoupler, and a switch transistor; wherein a first end of a primary side of the optocoupler is connected with the power end at the low-voltage side, and a second end of the primary side of the optocoupler is connected with a grounding end at the low-voltage side, a secondary side of the optocoupler is connected with a chip-wakeup end at a power high-voltage side, and the chip-wakeup end is connected with a wakeup pin of the battery sampling integrated chip; the switch transistor is connected in series with the primary side of the optocoupler, a control end of the switch transistor is connected with a wakeup signal input end at the low-voltage side.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 26, 2019
    Assignee: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Jiade Li, Gaosong Shen, Fuming Ye
  • Patent number: 10467181
    Abstract: An interface comprises routing circuitry configured to receive data items from a data source device and to route the received data items to a data sink device by either a first data path including a data buffer or a second data path, in response to an indication of a current state of a data sink device; the routing circuitry being configured to route the received data item by the first data path and to initiate a transition of the data sink device to a ready state in response to an indication that the data sink device is in a quiescent mode and currently not ready to receive the data item, the routing circuitry being configured to hold the data item at the buffer and to inhibit the data source device from sending further data items until the routing circuitry receives a subsequent indication that the data sink device is ready to receive the data item; and the routing circuitry being configured to route the received data item by the second data path in response to an indication that the data sink device is cur
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: November 5, 2019
    Assignee: ARM Limited
    Inventors: Peter Czakó, Seow Chuan Lim, Dominic William Brown, Christopher Vincent Severino, Patrick Michael Overs
  • Patent number: 10243480
    Abstract: To provide a multi-cell converter apparatus that is both miniature and low-cost, provided is a multi-cell converter apparatus including a plurality of AC/DC converting cells with AC sides that are connected in series to an AC power supply; and a plurality of isolating components that are connected in cascade and each transmit a potential difference input thereto to a later stage while providing isolation between input and output. Each AC/DC converting cell has a terminal that is at a reference potential inside the AC/DC converting cell connected to a terminal of a corresponding isolating component among the plurality of isolating components.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: March 26, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Satoru Fujita
  • Patent number: 9922709
    Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: March 20, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Perumal Ratnam, Christopher Petti, Tianhong Yan
  • Patent number: 9870481
    Abstract: The techniques presented herein provide for associating a data encryption lockbox backup with a data storage system. A first set of software system stable values (SSV) is derived from data storage system component values unique to the data storage system. A lockbox storing the first set of SSV and a set of encryption keys associated with a corresponding respective set of data storage system drives is created. Access to the lockbox requires providing a first minimum number of SSV that match corresponding SSV in the first set of SSV. A backup copy of the lockbox is created, wherein access to the backup copy requires providing a second minimum number of SSV that match corresponding SSV in the first set of SSV, wherein the minimum number of SSV is equal to a second match value. The backup copy of the lockbox is stored at a remote location.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 16, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Gregory W. Lazar, Peter Puhov, Millard C. Taylor, III, Naizhong Chiu Qui, Thomas N. Dibb
  • Patent number: 9455708
    Abstract: An integrated circuit and a method are provided. An integrated circuit comprises a first circuit, with a first character and at least one external control signal, and a character control unit. The character control unit controls the at least one external control signal and has a second circuit, with a second character essentially proportional to the first character, a character adjuster for adjusting the at least one external control signal, and a character monitor for monitoring the operation behavior of the second circuit to control the character adjuster to adjust the at least one external control signal accordingly.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: September 27, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kuo-Su Hsiao, Chun-Yuan Cheng, Chi-Tien Sun
  • Patent number: 9379534
    Abstract: A device for interrupting a flow of electrical power in an electrical distribution system is provided. The electrical distribution network includes a circuit interrupting device, the circuit interrupting device having a reclose time. The device includes a sensor configured to generate a signal in the event of loss of system power. A switch is coupled to the electrical distribution system and is movable between an open and closed position. A controller is operably coupled to the sensor and the switch, the controller having a processor that initiates a timer in response to the signal and determines a measured reclose time with the timer. The processor is further responsive to actuate the switch in response to the measured reclose time is substantially equal to the reclose time of the at least one circuit interrupting device.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 28, 2016
    Assignee: CONSOLIDATED EDISON COMPANY OF NEW YORK, INC.
    Inventor: John Witte
  • Patent number: 8983789
    Abstract: A bias calibration circuit includes a first current source that can provide a majority biasing current, sufficient to provide most but not all of a desired bias voltage across a sensor. A second current source can provide a remaining amount of biasing current (minority biasing current) to provide a bias voltage across the sensor. In some embodiments, the current sources are programmable and codes are determined for programming the first and second current sources. The codes can be stored in a memory.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: March 17, 2015
    Assignee: Marvell International Ltd.
    Inventor: Thart Fah Voo
  • Patent number: 8975953
    Abstract: A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 10, 2015
    Assignee: Analog Devices Global
    Inventors: Patrick J. Meehan, Mark T. Kelly, Christopher Peter Hurrell, Thomas Anthony Conway, Donal O'Sullivan, Michael Hennessy, William Hunt
  • Patent number: 8975933
    Abstract: Systems and methods are provided for a data storage element. A data input is configured to receive input data to the data storage element. A latching element is configured to hold input data that is received from the data input. A pulse generator is configured to assert a pulse signal based on a clock signal, and a multiplexer is configured to select for output from the data storage element, responsively to the pulse signal, one of the input data that is received from the data input without passing through the latching element and the input data held in the latching element.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: March 10, 2015
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventor: Uri Holzman
  • Patent number: 8963625
    Abstract: A microcomputer includes a first switch coupled between a main power supply terminal and a power supply node, and a second switch coupled between an auxiliary power supply terminal and the power supply node. The microcomputer compares a voltage V1 of the main power supply terminal with a reference voltage VR1. When V1>VR1, the microcomputer turns on the first switch and turns off the second switch, and when V1<VR1, the microcomputer turns off the first switch, and turns on/off the second switch to gradually increase a voltage V3 of the power supply node. Thus, the operation of a clock generation circuit driven by V3 can be stable even when V3 is changed from V1 to V2.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichiro Miwa, Masahiro Kitamura
  • Patent number: 8860502
    Abstract: An apparatus for monitoring timing of a plurality of critical paths of a functional circuit includes a plurality of canary circuits, each configured to be coupled to a critical path of a functional circuit for detecting and outputting critical timing events. Each canary circuit includes an adjustable delay element and an analyzer circuit for receiving a count of the critical timing event output from at least one of the plurality of canary circuits for a predetermined time interval for a plurality of delay values of the adjustable delay elements and for determining a probability distribution of critical timing events of the at least one of the plurality of critical paths for the predetermined time interval for the plurality of delay values.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: October 14, 2014
    Assignee: Stichting IMEC Nederland
    Inventors: Tobias Gemmeke, Mario Konijnenburg
  • Patent number: 8816757
    Abstract: Systems and methods are provided for regulating power in an integrated circuit system. A system includes a processing unit configured to monitor one or more operating parameters in the integrated circuit system. Based on the one or more monitored operating parameters, the processing unit is configured to predict an occurrence of an event that will cause an increased load on the integrated circuit system and further to assert a voltage adjustment command based on the predicted event. A power regulator is coupled to a power supply. The power regulator is configured to supply a regulated output voltage at a nominal voltage level. The power regulator is further configured to receive the voltage adjustment command and to supply the output voltage at an adjusted output level responsively to the voltage adjustment command.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: August 26, 2014
    Assignee: Marvell International Ltd.
    Inventors: Yehoshua Yabbo, Eran Segev
  • Patent number: 8786360
    Abstract: The present invention discloses a fast switching current mirror circuit and method for generating fast switching current. The circuit and method for fast switching of a current mirror with large MOSFET size will save space and current consumption.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: July 22, 2014
    Assignee: STMicroelectronics Asia Pacific PTE, Ltd.
    Inventor: Justin Ang
  • Patent number: 8745411
    Abstract: A data processing apparatus includes a volatile memory, a random number generator adapted for generating random numbers from which one or more keys are generated, and a memory encryption unit (MEU). The MEU is configured to receive an N-bit block of data and to divide the N-bit block of data into two more sub-blocks of data, where each sub-block contains fewer than N-bits. The MEU is further configured to encrypt each sub-block of data using the one more keys, to combine the encrypted sub-blocks into an N-bit block of encrypted data, and to write the encrypted N-bit block of data to the volatile memory.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: June 3, 2014
    Assignee: Broadcom Corporation
    Inventors: Love Kothari, Lawrence J. Madar, III
  • Patent number: 8704591
    Abstract: A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias signals. Magnitudes the first and second bias signals are configured to control a reference signal generated by the reference circuit such that when the reference signal is near a quiescent value of the reference signal, a current in the reference circuit is below a first level, and when the reference signal is outside of the prescribed limits, the current in the reference circuit increases nonlinearly.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: April 22, 2014
    Assignee: LSI Corporation
    Inventors: Pankaj Kumar, Pramod Parameswaran, Vani Deshpande, Makeshwar Kothandaraman
  • Patent number: 8688305
    Abstract: In a method, system and apparatus for managing vehicle energy, the amount of electric power needed for operating a vehicle is calculated, a surplus amount of electric power that is the current amount of battery power less the calculated amount of electric power is sold, or a number of received location information signals according to the current amount of battery power is adjusted.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: April 1, 2014
    Assignee: SK Planet Co., Ltd.
    Inventors: Yoon Jeong Choi, Dae Lim Son, Eun Bok Lee, Jun Yong Jung
  • Patent number: 8683248
    Abstract: An electronic apparatus includes a first power source to generate power from external power; a photovoltaic power generation device to generate power from received light as cell-generated power; a power storage device to store cell-generated power; a second power source to generate power from cell-generated power; a mode switching unit to switch between normal power supply mode and reduced-power mode, in normal power supply mode, power is supplied from the first power source to the electronic apparatus, and in reduced-power mode, power supply from the first power source is stopped and power is supplied from the second power source; a voltage detector to detect voltage of cell-generated power; a memory to store condition-specific threshold voltages to determine conditions of the electronic apparatus; and a power supply controller to control switching between normal power supply mode and reduced-power mode by comparing the voltage of cell-generated power and the condition-specific threshold voltages.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: March 25, 2014
    Assignee: Ricoh Company, Ltd.
    Inventor: Kei Senba
  • Patent number: 8659348
    Abstract: A current mirror comprises first and second sets of transistors. each of the first and second sets is a matched set comprising a first transistor and a second transistor. For each set, the base of the first transistor is directly coupled to the base of the second transistor. For one of the first and second transistors of each set the base is directly coupled to the collector. The collectors of the first and second transistors of the first set are coupled, respectively, to the emitters of the first and second transistors of the second set in series. A current output of the current mirror is coupled between the collector of the second transistor of the first set and the emitter of the second transistor of the second set.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: February 25, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Juan Luis López Rodriguez, Sergio Alejandro López Ramos, Javier González Bruno
  • Patent number: 8653884
    Abstract: A microcomputer includes a first switch coupled between a main power supply terminal and a power supply node, and a second switch coupled between an auxiliary power supply terminal and the power supply node. The microcomputer compares a voltage V1 of the main power supply terminal with a reference voltage VR1. When V1>VR1, the microcomputer turns on the first switch and turns off the second switch, and when V1<VR1, the microcomputer turns off the first switch, and turns on/off the second switch to gradually increase a voltage V3 of the power supply node. Thus, the operation of a clock generation circuit driven by V3 can be stable even when V3 is changed from V1 to V2.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: February 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichiro Miwa, Masahiro Kitamura
  • Patent number: 8653597
    Abstract: Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hayden C. Cranford, Jr., Terence B. Hook
  • Patent number: 8629714
    Abstract: According to one embodiment, there is provided a method of reducing the amount of power consumed by a galvanic isolator. A transmitter transmits a wake-up signal to a receiver located across an isolation medium when the transmitter is ready or preparing to transmit data or power signals to a receiver, which is operably connected to a sensing circuit. The sensing circuit receives the wake-up signal through the isolation medium, which may be operably connected to and powered substantially continuously or intermittently by a first power source. In response to the sensing circuit receiving the wake-up signal, the receiver is powered up from a sleep mode to an operating mode. After a period of time tRDY has passed since the wake-up signal was transmitted, a signature pattern is transmitted from the transmitter to the sensing circuit through the isolation medium. Next, the sensing circuit or the receiver verifies the validity of the signature pattern.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: January 14, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Gek Yong Ng, Peng Siang Seet, Fun Kok Chow
  • Patent number: 8581560
    Abstract: A voltage regulator circuit comprises active and standby amplifiers, first and second transistors, and a capacitor. The active amplifier has a negative input connected to a first reference voltage, and the standby amplifier has a negative input connected to a second reference voltage. The first reference voltage is greater than the second reference voltage. The first transistor has a gate connected to an output of the active amplifier and a drain connected to a voltage regulated output, and the second transistor has a gate connected to an output of the standby amplifier and a drain connected to the voltage regulated output. The capacitor is connected between a chip enable signal and the voltage regulated output.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: November 12, 2013
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Chung-Zen Chen
  • Patent number: 8570097
    Abstract: A semiconductor integrated circuit includes a first pad configured to receive a first voltage, a second pad configured to receive a second voltage, an internal voltage generation circuit configured to generate a third voltage having the same voltage level as the first voltage in response to the second voltage during a test mode, and an internal circuit configured to perform a normal operation using the first voltage and the second voltage during a normal mode and perform a test operation using the second voltage and the third voltage during the test mode.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: October 29, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Sic Yoon
  • Patent number: 8536908
    Abstract: An apparatus and method for testing is provided. An integrated circuit includes a comparison circuit that is arranged to trip based on a power supply signal reaching a trip point. The integrated circuit also includes an analog-to-digital converter that is arranged to convert the power supply signal into a digital signal. The integrated circuit also includes a storage component that stores a digital value associated with the digital signal, and provides the power supply value at an output pin of the integrated circuit. The integrated circuit includes a latch that is coupled between the analog-to-digital converter and the storage component. The latch is arranged to open when the comparison circuit trips, such that, when the comparison circuit trips, the storage component continues to store a digital value such that the digital value corresponds to the voltage associated with the power supply signal when the comparison circuit tripped.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: September 17, 2013
    Assignee: Spansion LLC
    Inventors: Hor Ching-Kooi, Teoh Boon-Weng, Ong Mee-Choo
  • Patent number: 8441305
    Abstract: Low leakage diodes and methods of forming the same are disclosed. In one embodiment an apparatus includes a designed or parasitic bipolar transistor having an emitter, a base and a collector. The bipolar transistor is configured to operate as a diode, the diode having reverse-biased and forward-biased modes of operation. The emitter and base operate as first and second terminals of the diode, respectively. The collector is configured to receive a collector bias voltage, which is controlled relative to a voltage of the emitter to reduce a diffusion leakage current of the diode when the diode is in the reverse-biased mode of operation.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: May 14, 2013
    Assignee: Analog Devices, Inc.
    Inventor: David Hwa Chieh Shih
  • Patent number: 8427887
    Abstract: Methods, devices, and systems are provided for a power generator system. The power generator system may include a control device configured to output a first reference voltage and a second reference voltage that define a dead band range. The control device may be configured to independently adjust the first reference voltage and the second reference voltage. The power generator system may also include a power generator operably coupled to the control device, and the power generator may be configured to receive the first reference voltage and the second reference voltage and to output a voltage that is greater than or substantially equal to the first reference voltage and less than or substantially equal to the second reference voltage.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: April 23, 2013
    Assignee: Micron Technology, Inc.
    Inventors: George F. G. Carey, Brian P. Callaway
  • Patent number: 8416009
    Abstract: Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: April 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Hayden C. Cranford, Jr., Terence B. Hook
  • Patent number: 8378741
    Abstract: A mobile telephone is provided that includes a plurality of circuit blocks and adapted to cut off the supply of power source voltage to any one of the circuit blocks. The mobile telephone also includes an interblock interface circuit provided on a signal path between an elected circuit block and a branch point at which the signal path branches into different branch paths so as to connect to other circuit blocks. The interblock interface circuit includes a signal gate for preventing signal transmission from the elected circuit block to the other circuit blocks, and includes a storage unit for storing a signal right before the power cut-off.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: February 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tadashi Hoshi, Kenji Hirose, Hideaki Abe, Junichi Nishimoto, Midori Nagayama
  • Patent number: 8355258
    Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: January 15, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Osaka, Yutaka Uematsu
  • Patent number: 8178897
    Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: May 15, 2012
    Assignee: Infineon Technologies AG
    Inventors: Krzysztof Domanski, Cornelius Christian Russ, Kai Esmark
  • Patent number: 8081025
    Abstract: A biasing device can supply a bias voltage to bias-able element by coupling a bias circuit to the bias-able element, coupling a state adjusting device to the biasing circuit, configuring the state adjusting device to 1) increase an initial biasing voltage by a first amount when an intermediate voltage threshold exceeds a voltage drop across the bias-able element and 2) increment the increased initial bias voltage by a second amount, where the second amount is a fraction of the first amount, until the voltage drop across the bias-able element substantially equals a predetermined bias voltage. The bias circuit of the biasing device can include a variable resistance, which is controlled by the state adjusting device and configured to vary the biasing voltage, in series with the bias-able element.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: December 20, 2011
    Assignee: Marvell International Ltd.
    Inventor: Kan Li
  • Publication number: 20110291691
    Abstract: According to an example embodiment, a chip includes a plurality of circuit blocks, a power switch unit configured to supply power to the plurality of circuit blocks, and a power switch controller configured to control the power switch unit in response to an external control signal. The external control signal selectively control supply of power to at least one circuit block of the plurality of circuit blocks.
    Type: Application
    Filed: April 29, 2011
    Publication date: December 1, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sunghoon Cho
  • Publication number: 20110291749
    Abstract: Apparatus and methods are disclosed, such as those involving protection of a semiconductor junction of a semiconductor device. One such apparatus includes a bipolar transistor including an emitter, a base, and a collector; a first junction protection device including a first end electrically coupled to the emitter of the bipolar transistor, and a second end electrically coupled to a node; and a second junction protection device including a first end electrically coupled to a voltage reference, and a second electrically coupled to the emitter of the bipolar transistor. Each of the first and second junction protection devices may have a substantially higher leakage current than the leakage current of the base-emitter junction of the bipolar transistor when reverse biased.
    Type: Application
    Filed: May 25, 2010
    Publication date: December 1, 2011
    Applicant: ANALOG DEVICES INC.
    Inventor: Kenneth Lawas
  • Patent number: 8064825
    Abstract: A power-receiving-side control circuit of a power reception device performs intermittent load modulation by causing an NMOS transistor to be turned ON/OFF during normal power transmission. A power-transmission-side control circuit included in a power transmission control device of a power transmission device monitors, an intermittent change in the load of the power reception device during normal power transmission. The power-transmission-side control circuit determines that a foreign object has been inserted between a primary coil and a secondary coil and stops power transmission when an intermittent change in load cannot be detected. The amount of power supplied to the load may be compulsorily reduced when the load state of the load is heavy.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: November 22, 2011
    Assignees: Seiko Epson Corporation, Sony Ericsson Mobile
    Inventors: Kota Onishi, Kentaro Yoda, Takahiro Kamijo, Mikimoto Jin, Haruhiko Sogabe, Yoichiro Kondo, Kuniharu Suzuki, Hiroshi Kato, Katsuya Suzuki, Manabu Yamazaki
  • Patent number: 8054135
    Abstract: An amplifier comprises a power source, a load network comprising a load and a resonance circuit, an input branch having a first end electrically coupled to the power source and a second end electrically coupled to the load network, and an active switch having one terminal electrically coupled to the second end of the input branch. The input branch including at least one parallel-LC-circuit configured to provide an infinitely large impedance at harmonics of a determined order.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: November 8, 2011
    Assignee: General Electric Company
    Inventors: Yingqi Zhang, Jianwu Li, Yunfeng Liu, Wuhua Li
  • Patent number: 8014216
    Abstract: Methods, devices, and systems are provided for a power generator system. The power generator system may include at least one control device including control logic. The at least one control device may be configured to receive at least one control signal and output an upper reference voltage and a lower reference voltage. The at least one control device may be further configured to vary a magnitude of at least one of the upper reference voltage and the lower reference voltage. The power generator system may also include a power generator operably coupled to the at least one control device and configured to receive the upper reference voltage and the lower reference voltage. The power generator may be further configured to output a voltage that is greater than or equal to the lower reference voltage and less than or equal to the upper reference voltage.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: September 6, 2011
    Assignee: Micron Technology, Inc.
    Inventors: George F. G. Carey, Brian P. Callaway
  • Patent number: 7969237
    Abstract: A semiconductor integrated circuit device includes at least one first transistor configured to control conductance between an input power line and an output power line, at least one second transistor configured to control conductance between the input power line and the output power line, a first buffer configured to supply a first control signal for driving the at least one first transistor to a first control line connected to the at least one first transistor, a second buffer configured to generate a second control signal for driving the at least one second transistor upon receipt of the first control signal supplied through the first control line and supply the second control signal to a second control line connected to the at least one second transistor, and at least one capacitor connected between the first control line and the output power line.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: June 28, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Fujita, Yousuke Hagiwara
  • Patent number: 7944267
    Abstract: A leakage current measurement circuit measuring a substrate leakage current and a gate leakage current in response to a variation in the size of an MOS transistor and a leakage current comparison circuit judging which one of the substrate leakage current and the gate leakage current is dominant. The leakage current measurement circuit includes a charge supply, a leakage current generator and a detection signal generator. The leakage current comparison circuit includes a charge supply, a leakage current comparator and a detection signal generator.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: May 17, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Gun-Ok Jung
  • Patent number: 7886158
    Abstract: A system and method for remote copy of encrypted data where a primary storage system receives data, encrypts the data with a first cryptographic method, and stores the encrypted data. A secondary storage system connected to the primary storage system receives and stores a remote copy of the encrypted data. When a block of the stored encrypted data is converted using a second cryptographic method, the converted block and a pointer containing an address at which the conversion has finished is transferred to the second storage system and stored. The pointer is incremented for each block converted. A backup copy of the first cryptographic method and the second cryptographic method are stored at a backup system remote from the primary storage system. If the primary system fails, the backup system can decrypt the data using the first cryptographic method or the second cryptographic method based on the pointer.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: February 8, 2011
    Assignee: Hitachi, Ltd.
    Inventor: Nobuyuki Osaki
  • Patent number: 7852145
    Abstract: A semiconductor device is provided which includes: a first semiconductor integrated circuit; a ground line and a power supply line trough which electric power is supplied to the first semiconductor integrated circuit; and a variable impedance component which is connected between the ground line and the power supply line.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: December 14, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Yutaka Uematsu, Hideki Osaka, Tatusya Saito, Yoji Nishio
  • Patent number: 7821327
    Abstract: A high voltage input receiver using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a comparator circuit and an inverter circuit. The comparator circuit includes a differential input module for generating a control signal by comparing an external voltage and a reference voltage, and a decision module for generating an inverter input signal based on the control signal. In addition, the reference voltage is used to set dc trip point of the input receiver. Moreover, the input receiver includes one or more stress protection modules to protect key components of the input receiver from exceeding their reliability limits.
    Type: Grant
    Filed: August 2, 2008
    Date of Patent: October 26, 2010
    Assignee: LSI Corporation
    Inventors: Pramod Elamannu Parameswaran, Pankaj Kumar
  • Publication number: 20100253422
    Abstract: A semiconductor device includes a substrate on which an electronic circuit is provided. Two or more pads may be present which can connect the electronic circuit to an external device outside the substrate. A current meter is electrically in contact with at least a part of the substrate and/or the pad. The meter can measure a parameter forming a measure for an aggregate amount of a current flowing between the substrate and said pads. A control unit is connected to the current meter and the electronic circuit, for controlling the electronic circuit based on the measured parameter.
    Type: Application
    Filed: November 27, 2008
    Publication date: October 7, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Andreas Roth, Hubert Bode, Andreas Laudenbach, Stephan Lehmann, Engelbert Wittich
  • Patent number: 7802108
    Abstract: Aspects for securely storing program code of an embedded system includes accepting a digitation file from a distribution source into on-chip memory of an adaptive computing engine (ACE). The digitation file is then secured and transferred to off-chip memory.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: September 21, 2010
    Assignee: NVIDIA Corporation
    Inventors: Paul L. Master, Eric Murray, Joseph Mehegan, Robert Thomas Plunkett
  • Patent number: 7741900
    Abstract: A biasing device can supply a bias voltage to bias-able element by coupling a bias circuit to the bias-able element, coupling a state adjusting device to the biasing circuit, configuring the state adjusting device to 1) increase an initial biasing voltage by a first amount when an intermediate voltage threshold exceeds a voltage drop across the bias-able element and 2) increment the increased initial bias voltage by a second amount, where the second amount is a fraction of the first amount, until the voltage drop across the bias-able element substantially equals a predetermined bias voltage. The bias circuit of the biasing device can include a variable resistance, which is controlled by the state adjusting device and configured to vary the biasing voltage, in series with the bias-able element.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 22, 2010
    Assignee: Marvell International Ltd.
    Inventor: Kan Li
  • Patent number: 7661001
    Abstract: In an apparatus for encrypting an information signal into an encryption-resultant signal, a first encryption key peculiar to the present apparatus is generated. Key information is read out from a replaceable recording medium. A decision is made as to whether or not the read-out key information has been generated by an apparatus different from the present apparatus. A second encryption key is generated in response to the read-out key information when it is decided that the read-out key information has been generated by an apparatus different from the present apparatus. One is selected from the first encryption key and the second encryption key as a final encryption key. An information signal is encrypted in response to the final encryption key.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: February 9, 2010
    Assignee: Victor Company of Japan, Ltd.
    Inventor: Seiji Higurashi
  • Publication number: 20100008174
    Abstract: An apparatus includes logic to determine a discharge drop of a capacitor and to adjust an enablement charge level of the capacitor according to the discharge drop.
    Type: Application
    Filed: July 10, 2008
    Publication date: January 14, 2010
    Applicant: AgigA Tech Inc.
    Inventors: Ronald H. Sartore, Yingnan Liu, Lane Hauck
  • Publication number: 20100001789
    Abstract: Methods and circuitry for lowering the capacitance of interconnects, particularly Through Wafer Interconnects (TWIs), using signal level adjustment are disclosed. Embodiments of the invention seek to bias the midpoint voltage level of the signals on the TWIs towards inversion, where at high frequencies capacitance is at its minimum. In one embodiment, reduced swing signals are used for the data states transmitted across the TWIs, in which the reduced swing signals use a midpoint voltage level tending to bias the TWI capacitance towards inversion. In another embodiment, signals are AC coupled to the TWI where they are referenced to an explicit bias voltage directly connected to the TWI. This allows signals to propagate through the TWI while the TWI is biased towards inversion. In a third embodiment, the potential of the substrate is explicitly lowered with respect to the TWI potential.
    Type: Application
    Filed: July 4, 2008
    Publication date: January 7, 2010
    Applicant: Micron Technology, Inc.
    Inventor: Timothy M. Hollis
  • Patent number: 7609113
    Abstract: A constant current bias circuit and associated method is disclosed. The constant current bias circuit comprises an output stage for amplifying a radio frequency (RF) signal, wherein the output stage is operably coupled with a voltage. The constant current bias circuit further comprises a bias circuit operably coupled with the output stage for generating a substantially constant current bias to the output stage. The constant current bias circuit still further comprises a plurality of bias transistors operably coupled with the voltage and the output stage.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: October 27, 2009
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: William H. Davenport
  • Publication number: 20090245309
    Abstract: Improved dispersion compensating circuits for optical transmission systems are disclosed. According to the improved method, there is provided a compensation circuit comprising a varactor diode network. The network is preferably inserted between a source of laser modulating signal and the laser. A low-pass filter or all pass filter constructs the network. The network preferably includes an inductor or inductors and a combined circuit, which includes varactors. The network preferably provides an amplitude dependent delay of the modulating signal applied to the laser or to the optical receiver as post dispersion correction circuitry. In a first embodiment, a fixed capacitor is in series with a varactor and connected to a DC bias through inductor. Additional embodiments, using multiple varactors in different circuit configurations, with particular advantages for various applications identified.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Applicant: GENERAL INSTRUMENT CORPORATION
    Inventors: Ihab Khalouf, Richard Meier, Shutong Zhou