Abstract: A first electronic device, such as a computer, is connected to a second electronic device, such as a printer, over a communication bus. The second electronic device has device specific integrated circuitry for performing the functions of the device, and also has pad driver circuitry. The pad driver circuitry is connected between the communication bus and the device specific integrated circuitry. The first electronic device is powered by a first voltage source, such as AC power through an on/off switch. The second electronic device is powered by a second voltage source, such as AC power through a different on/off switch. In addition to being powered by the second voltage source, the pad driver circuitry is also powered by a third voltage source, isolated from the second voltage source.

Abstract: A sensing circuit for a floating gate memory device is disclosed. The sensing circuit has a first voltage amplifier which generates a first output voltage, and a current amplifier which receives the first output voltage and generates a first output current in response thereto. The first voltage amplifier has a control transistor which generates a first output voltage in response to the memory device being in one state and a second output voltage in response to the memory device being in another state. The circuit also comprises a dummy cell, a second voltage amplifier connected thereto for generating a second output voltage. A second current amplifier receives the second output voltage and generates a second output current in response thereto. A comparator receives the first and second output currents, compares them, and generates an output indicative of the state of the memory device.

Abstract: Reduced manufacturing costs and wafer size, lower power consumption, and increased operating speed are achieved in memory circuits by providing a novel sense amplifier design that is most sensitive to voltages variations around the source voltage (V.sub.dd). The sense amplifier includes two inverters that are regeneratively cross-coupled through a circuit that is controlled by a system clock. The inverters are powered from the bit lines that couple the sense amplifier to a memory cell. Novel applications of the sense amplifier in memory circuits also are described.

Abstract: A bus termination circuit actively switches a terminating resistor from the bus conductor in response to a control signal. A first state of the control signal connects the bus conductor through the terminating resistor to a voltage reference source, while a second state of the control signal isolates the bus conductor from the voltage reference source. Thus, the switchable active bus termination circuit can be permanently installed in computer peripheral devices and activated by the control signal.

Abstract: An IC memory card used in a dual power supply voltage operation system and having a backup function is arranged to prevent destruction of data stored in an internal memory caused by an erroneous access in a non-operation-ensured voltage range between lower and higher operation-ensured voltage ranges. Three voltage levels divided from an external power supply voltage by voltage dividing resistors are compared with a reference voltage from a reference voltage generation circuit to determine whether the external power supply voltage is at the lower or upper limit of the lower operation-ensured voltage range or the lower limit of the higher operation-ensured voltage range. On the basis of outputs from these comparators, a memory protection signal generation circuit generates a memory protection signal to enable the memory to be protected even in the voltage range between the lower and higher operation-ensured voltage ranges.

Abstract: An integrated circuit is disclosed comprising a first field effect transistor having a source connected to a first node and a gate connected to a second node, and a second field effect transistor for protecting the first transistor from voltages applied to the first node and greater than a predetermined nominal voltage. The second transistor includes a drain connected to the second node, a source connected to the first node, and a gate connected to a third node. A constant voltage source is coupled to the third node and supplies a gate voltage to the gate of the second transistor such that a drain-source path of the second transistor does not conduct while voltage applied to the first node is generally less than the gate voltage plus a threshold voltage of the second transistor.

Abstract: A CMOS buffer circuit includes a p-channel MOS transistor having a source terminal connected to an operating voltage source and a substrate terminal connected to a pump voltage source. A first n-channel MOS transistor is connected in series with the p-channel MOS transistor and has a source terminal connected to a reference potential and a drain terminal connected to an output terminal. A second n-channel MOS transistor is connected between and in series with the p-channel MOS transistor and the first n-channel MOS transistor. The second n-channel MOS transistor has a gate terminal connected to the pump voltage source.

Abstract: A power supply voltage level detecting circuit includes a reference voltage generating circuit for generating a constant reference voltage independent of a power supply voltage, a to-be-compared voltage generating circuit for generating a voltage to be compared changing dependent upon the power supply voltage, a current mirror type differentially amplifying circuit for amplifying differentially the reference voltage and the voltage to be compared, and a determining circuit for generating a level detecting signal indicating whether or not the power supply voltage has attained a predetermined level in accordance with an output of the differentially amplifying circuit. The to-be-compared voltage generating circuit generates the voltage to be compared by dropping the power supply voltage using the resistance division or the forward voltage drop of diode.

Abstract: A power-on reset circuit for generating and maintaining a reset signal in an active low state during power-up until a power supply voltage exceeds a predetermined level includes a resetting circuit (12a) and a control logic circuit (12b). The reset circuit is responsive to a monitoring signal, a start-up signal and a reference voltage for generating a reset signal which is initially in the active low state. The reset circuit includes a differential comparator (54) having a first input for receiving the start-up signal, a second input for receiving the reference voltage, and an output for generating the reset signal. The control logic circuit is responsive to the monitoring signal and the reset signal for generating a logic control signal which is initially in a high state. The differential comparator is responsive to the control signal and is activated only after the power supply voltage has exceeded a predetermined level so as to maintain initially the reset signal on its output in the low state.

Abstract: An LSI including a voltage drop circuit for receiving a voltage from an external power source and generating an internal power source voltage, a substrate biasing voltage generator circuit for generating a substrate biasing voltage, and a power on circuit for monitoring a voltage rising rate of the external power source and producing a control signal. The substrate biasing voltage generator circuit operates, in accordance with conditions of the control signal, to generate the substrate bias voltage having a first current capability based on the external power voltage or the substrate bias voltage having a second current capability based on the internal power source voltage. Thus, the LSI eliminates delay of start of operation of the LSI and reduces power consumption by the LSI due to a delay in the increase of the internal power source voltage which operates the substrate biasing voltage generator circuit.

Abstract: An input buffer insensitive to changes in supply voltage, temperature and other operational parameters comprises a decoupling capacitor and receives a reference voltage. In one embodiment, the input buffer comprises a CMOS invertor in which a PMOS transistor is provided to decouple the output signal from a fluctuation of the ground voltage ("ground bounce"). In one embodiment, a band gap type voltage regulator provides the reference voltage of the input buffer.

Abstract: A power-on detecting circuit includes a capacitance for sensing power-on, and a signal generating circuit which responds to the output node potential of capacitance by generating a signal indicative of the power-on. The signal generating circuit includes inverter circuits forming a latch circuit. The power-on detecting circuit includes a control circuit, which adjusts driving capabilities of inverter circuits at the power-on and power-off, or an activation control circuit, which delays the activation timing. The control circuit differentiates the driving capability of the latch circuit formed of inverter circuits at the power-on from that at the power-off. Activation control circuit activates signal generating circuit at the time the potential of the output node ND10 of a sensing circuit rises above the potential of the output node of signal generating circuit.

Abstract: A circuit for switching the well in a CMOS circuit to one of two power supply rails. In, for example, an N-well CMOS process, when an output is driven by a PMOS pull-up transistor, the P+ (drain of the PMOS) to N-well junction may be forward biased if the rail drops to ground. This will cause the output to be pulled to ground. The switching circuit of the present invention avoids the grounding of the output by automatically switching the N-well to the higher power supply rail so that grounding the rail would not cause the output to fall. MOS switches connect the well to either of the power supplies. Therefore, there is no voltage drop from the power supply to the well as in the case of switching circuits using diodes. Also, this circuit connects the well to the highest power supply regardless of which power supply drops to ground. Therefore, it does not require one power supply to be always on for proper operation.

Abstract: A controller for a clock generator. The controller of the present invention enables a clock signal to the internal clocking mechanism of a device. The controller of the present invention includes a detector and a timer. The detector has two input sense levels, such that it is capable of detecting a clock signal at two separate levels, the first level being larger than the second. Initially, the detector only detects when the clock signal is at a level greater than or equal to the larger of the levels. When this occurs, the timer begins counting. When the clock signal has been at or above the greater level for a predetermined time as determined by the timer, the detector enables the clock signal to go to the internal clocking mechanism. Thereafter, the detector only senses when the clock signal falls below the second level. Thus, the detector enables the clock signal to go to the internal clocking mechanism while the level of the clock signal is above the second level.

Abstract: A CMOS power-on reset circuit has a delay capacitor to provide a predetermined delay period. Charging and discharging of the delay capacitor is controlled by the state of a flipflop circuit. An input comparator monitors a power supply input voltage. An invalid input voltage level immediately changes the reset output signal to the invalid state and discharges the capacitor. Even after the input voltage has recovered to a valid level, recharging the capacitor is delayed until the capacitor has substantially discharged, thereby ensuring at least a predetermined delay period after the last fault condition. The delay capacitor is coupled in a feedback configuration so as to lower the threshold voltage when the delay capacitor voltage indicates to the valid state, to allow limited power supply sag, for example due to motor start-up, without resetting the circuit.

Abstract: The CMOS voltage compensating input buffer circuit of the present invention provides a means to stabilize input level trip points and is comprised of a voltage compensating circuit having an input node and an output drive node coupled to an input buffer. The voltage compensating circuit receives its input from a voltage adjusting circuit that follows changes in V.sub.CC while its output drive node is coupled to the series connected CMOS input buffer circuit having an input node and an output node. The buffer's input node receives a signal that VIH/VIL trip points will determine if the output is to be a high or a low and the buffer's output node then couples the resultant level to an output buffer circuit comprised of a CMOS inverter which provides the final output drive. The present invention provides trip point levels corresponding to industry standard VIH/VIL levels to accurately determine the corresponding output with operating voltage supplies (regulated or unregulated) operating between 2 V to 7.5 V.