Lowpass Patents (Class 327/558)
  • Patent number: 11374407
    Abstract: A method for correct operation of the current-angle-based phase-selection method (PSM) is based on a proper dual current controller (DCC) for inverter interfaced sources during unbalanced fault conditions. The fault type is determined in the inverter using voltage-angle-based PSM. Accordingly, fault-type zones' bisectors of the current-angle-based are determined. Consequently, an initial negative-sequence current angle reference is determined to force the relative angle between the negative- and zero-sequence currents in the center of its correct fault-type zone. The initial positive-sequence current angle is determined according to reactive current requirements by grid codes. These initial angles are updated for accurate operation of the PSM and appropriate reactive current injection. Negative- and positive-sequence current references are determined in the stationary frame to comply with the reference angles and inverter's thermal limits. These references are regulated by a proportional-resonance controller.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: June 28, 2022
    Assignee: KING ABDULAZIZ UNIVERSITY
    Inventors: Abdallah Aboelnaga, Hatem Sindi, Maher Azzouz
  • Patent number: 11159146
    Abstract: A reconfigurable analog filter includes a transimpedance amplifier configured to convert a current signal into a voltage signal, an input capacitor configured to form a current-mode low pass filter together with an input impedance of the transimpedance amplifier, a variable load circuit including at least one switch configured to selectively close a circuit path to provide a resistor and/or a capacitor as a load of the transimpedance amplifier according to a control signal, and a low pass filter configured to filter the voltage signal.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: October 26, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jisoo Chang
  • Patent number: 11114854
    Abstract: A method for correct operation of the current-angle-based phase-selection method (PSM) is based on a proper dual current controller (DCC) for inverter interfaced sources during unbalanced fault conditions. The fault type is determined in the inverter using voltage-angle-based PSM. Accordingly, fault-type zones' bisectors of the current-angle-based are determined. Consequently, an initial negative-sequence current angle reference is determined to force the relative angle between the negative- and zero-sequence currents in the center of its correct fault-type zone. The initial positive-sequence current angle is determined according to reactive current requirements by grid codes. These initial angles are updated for accurate operation of the PSM and appropriate reactive current injection. Negative- and positive-sequence current references are determined in the stationary frame to comply with the reference angles and inverter's thermal limits. These references are regulated by a proportional-resonance controller.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: September 7, 2021
    Assignee: King Abdulaziz University
    Inventors: Abdallah Aboelnaga, Hatem Sindi, Maher Azzouz
  • Patent number: 11069282
    Abstract: A system and method for operating a sensing circuit for sensing a pixel current of a pixel of a display panel using correlated double sampling. In some embodiments, the method includes: during a first interval of time, resetting a pixel sensing circuit; during a third interval of time following the first interval of time, operating the pixel sensing circuit in an integration mode; during a fourth interval of time following the third interval of time, operating the pixel sensing circuit in a hold mode; and during a fifth interval of time following the fourth interval of time, operating the pixel sensing circuit in the integration mode.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: July 20, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Amir Amirkhany, Anup P. Jose, Gaurav Malhotra, Younghoon Song, Mohamed Elzeftawi
  • Patent number: 10888242
    Abstract: A method for operating a removable smartphone case is disclosed. The method involves transmitting radio waves below the skin surface of a person, receiving radio waves on a two-dimensional array of receive antennas, the received radio waves including a reflected portion of the transmitted radio waves, generating digital data in response to the received radio waves, wherein the digital data is indicative of a health parameter of the person, and communicating the digital data generated in response to the received radio waves from the removable smartphone case to a smartphone that is connected to the removable smartphone case.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: January 12, 2021
    Assignee: Movano Inc.
    Inventor: Michael A. Leabman
  • Patent number: 10874314
    Abstract: Devices, systems, and methods for multi-band radar sensing are disclosed. A method for operating an IC device involves setting a configuration of the IC device to select from available options of low-band and high-band operational modes, transmitting and receiving RF signals at a low-band frequency when the configuration of the IC device is set to the low-band operational mode, and transmitting and receiving RF signals at a high-band frequency when the configuration of the IC device is set to the high-band operational mode, wherein transmitting RF signals at the high-band frequency comprises upconverting a first signal at the low-band frequency to a second signal at the high-band frequency and wherein receiving RF signals at the high-band frequency comprises downconverting a third signal at the high-band frequency to a fourth signal at the low-band frequency, wherein the upconversion and the downconversion are implemented using a conversion signal at a conversion frequency.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: December 29, 2020
    Assignee: Movano Inc.
    Inventor: Michael A. Leabman
  • Patent number: 10498297
    Abstract: A loop-filter comprising: a first-integrator, and one or more further-integrators. The first-integrator is an active-RC integrator, and comprises a first-integrator-input-terminal configured to receive: (i) an input-signal, and (ii) a feedback-signal; a first-integrator-first-output-terminal configured to provide a first-integrator-first-output-signal; and one or more first-integrator-further-output-terminals. Each of the one or more further-integrators is a Gm-C integrator, and they are connected in series between the first-integrator-first-output-terminal and a loop-filter-output-terminal. For a first further-integrator in the series, the further-integrator-input-terminal is configured to receive the first-integrator-first-output-signal. For any subsequent further-integrators in the series, the further-integrator-input-terminal is configured to receive: (i) the further-integrator-output-signal from the preceding further-integrator in the series; and (ii) one of the first-integrator-further-output-signals.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: December 3, 2019
    Assignee: NXP B. V.
    Inventors: Marco Berkhout, Jokin Segundo Babarro, Paulus Petrus Franciscus Maria Bruin
  • Patent number: 10338541
    Abstract: A machine learning apparatus, which learns a condition associated with a filter unit for filtering an analog input signal, includes a state observer for observing a state variable that includes at least one of a noise component and noise amount of an output signal from the filter unit and a responsivity to the input signal; and a learner for learning the condition associated with the filter unit in accordance with a training data set that includes the state variable.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: July 2, 2019
    Assignee: FANUC CORPORATION
    Inventor: Kunio Tsuchida
  • Patent number: 10014835
    Abstract: A transistor cell can be modeled as a transistor with a collector, a base, and an emitter operating with a current at the collector to produce a minimum transconductance in the transistor cell that increases a current gain and improves at least one operating characteristic of the transistor cell. The operating characteristics include bandwidth, gain, and output power.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: July 3, 2018
    Assignee: Rockwell Collins, Inc.
    Inventors: Russell D. Wyse, Michael L. Hageman
  • Patent number: 9923546
    Abstract: Two types of high-pass filter circuit and a band-pass filter circuit are provided. Both types of high-pass filter circuit include a capacitor configured to input an input signal, a resistor connected between an output terminal of the capacitor and a prescribed bias voltage, and a signal output circuit connected to the output terminal of the capacitor and configured to buffer-amplify the input signal for output. In one of the two types of high-pass filter circuits, the resistor is formed on an SOI semiconductor substrate and includes two PN junction diodes that are inversely connected to each other in parallel. In the other one of the high-pass filter circuits, the resistor is formed on an SOI semiconductor substrate and includes two MOS transistors that are inversely connected to each other in parallel.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: March 20, 2018
    Assignee: RICOH COMPANY, LTD.
    Inventors: Takeshi Nagahisa, Yasukazu Nakatani
  • Patent number: 9658295
    Abstract: There is described a device for removing an offset from a signal, the device comprising (a) a frequency estimation unit (260) for estimating a frequency of the signal, (b) an offset estimation unit (222) for estimating the offset in the signal by applying an adaptive low pass filter to the signal, wherein a cut-off frequency of the adaptive low pass filter is determined based on the frequency of the signal estimated by the frequency estimation unit (260), and (c) a subtraction unit (230) adapted to subtract the offset estimated by the offset estimation unit (222) from the signal. There is also described a filter unit comprising the device. Furthermore, there is described a corresponding method of removing an offset from a signal as well as a computer program and a computer program product for performing the method by means of a computer.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: May 23, 2017
    Assignee: NXP B.V.
    Inventors: Robert Hendrikus Margaretha van Veldhoven, Fabio Sebastiano
  • Patent number: 9517415
    Abstract: A method and system for generating augmented reality with a display of a vehicle is provided. The method comprises recording an image of an environment of the vehicle in the form of image data, determining a virtual space in three dimensions from the image data, and detecting a real object in the image data. The method further comprises determining a first coordinate range of the real object in the three dimensional virtual space, adding a virtual element to the three dimensional virtual space, and controlling the virtual element in the three dimensional virtual space based on a user input. The method further comprises outputting the environment and the controlled virtual element in combined form in an output image, modifying the output image when the first coordinate range of the real object and a second coordinate range of the controlled virtual element form an intersection area, and displaying the output image.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: December 13, 2016
    Assignee: Harman Becker Automotive Systems GmbH
    Inventors: Tobias Muench, Philipp Schmauderer, Christoph Benz, Andreas Koerner
  • Patent number: 9172354
    Abstract: Apparatus and methods for high-frequency low-pass filtering are disclosed. A first resistor is operatively coupled between a first node and a second node. A second resistor is operatively coupled between the second node and a third node. An amplifier circuit has a first input operatively coupled to the third node and a first output operatively coupled to a fourth node. The first output is configured to provide a first output signal. A first complex impedance network is operatively coupled between the fourth node and the third node. A first feedback path is operatively coupled between the fourth node and the second node. The first feedback path is configured to invert at least a portion of the first output signal. The first feedback path is further configured to provide a first feedback capacitance at the second node.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: October 27, 2015
    Assignee: ANALOG DEVICES, INC.
    Inventor: Alexandru Ciubotaru
  • Publication number: 20150137882
    Abstract: Apparatus and methods for high-frequency low-pass filtering are disclosed. A first resistor is operatively coupled between a first node and a second node. A second resistor is operatively coupled between the second node and a third node. An amplifier circuit has a first input operatively coupled to the third node and a first output operatively coupled to a fourth node. The first output is configured to provide a first output signal. A first complex impedance network is operatively coupled between the fourth node and the third node. A first feedback path is operatively coupled between the fourth node and the second node. The first feedback path is configured to invert at least a portion of the first output signal. The first feedback path is further configured to provide a first feedback capacitance at the second node.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicant: ANALOG DEVICES, INC.
    Inventor: Alexandru Ciubotaru
  • Patent number: 9024684
    Abstract: Techniques for reducing noise and power consumption in a loop filter for a phase-locked loop (PLL) are described herein. In one embodiment, a loop filter for a PLL comprises a first proportional capacitor, a second proportional capacitor, an active device, and a plurality of switches. The plurality of switches are configured to alternately couple the first proportional capacitor and the second proportional capacitor to a first charge pump, to alternately couple noise from the active device to the first proportional capacitor and the second proportional capacitor, and to alternately couple the first proportional capacitor and the second proportional capacitor into a feedback circuit, wherein the feedback circuit produces an output voltage of the loop filter.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 5, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Yu Song, Nan Chen
  • Publication number: 20150054772
    Abstract: A bandpass sense amplifier circuit (FIG. 2A) is disclosed. The circuit includes a capacitor (C0) having a first terminal coupled to receive an input signal (Vin) and a second terminal. A current conveyor circuit (200-206,212) has a third terminal (X) coupled to the second terminal of the capacitor and a fourth terminal (Z) arranged to mirror a current into the third terminal. A voltage follower circuit (214) has an input terminal coupled to the fourth terminal of the current conveyor circuit and an output terminal.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 26, 2015
    Applicant: Texas Instruments Incorporated
    Inventors: Karan Singh Jain, Harish Venkataraman
  • Patent number: 8964427
    Abstract: A phase angle detector with a PLL, a power converter, and a method for reducing offsets in an input signal, in which an adaptive offset processor selectively removes a DC offset component from the input signal to generate a modified signal including a fundamental frequency component and higher order harmonics of the input signal with the DC offset component removed, and the PLL provides a phase angle signal at least partially according to the modified signal.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 24, 2015
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Russel J. Kerkman, Ahmed Mohamed Sayed Ahmed, Brian J. Seibel
  • Patent number: 8963629
    Abstract: A programmable variable admittance circuit may be used in a programmable filter or a variable gain amplifier in a number of different applications including tuners and other RF receiver circuits. A variable admittance circuit and operation is described including a number of switchable admittance elements arranged in parallel branches. The variable admittance circuit requires fewer transitions to change between successive admittance values than a binary weighted circuit and fewer branches for implementation then a thermometry admittance circuit.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: February 24, 2015
    Assignee: NXP B.V.
    Inventor: Xavier Pruvost
  • Patent number: 8954026
    Abstract: An electronic device includes an adjustable filter with a first filter element, and a second filter element coupled to the first filter element. The second filter element includes a field effect transistor (FET) including a source terminal, a drain terminal, and a gate terminal. The source terminal and the gate terminal are coupled to a reference voltage. A control circuit is coupled to the drain terminal and is configured to apply a control voltage thereto to vary a capacitance between the source and drain terminals to adjust the adjustable filter.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: February 10, 2015
    Assignee: Harris Corporation
    Inventors: Andrew Mui, Anthony C. Manicone
  • Patent number: 8917138
    Abstract: There are provided a noise filter circuit and an operating method thereof. A noise filter circuit includes a first delay circuit, and a second delay circuit connected to the first delay circuit in series, wherein the first delay circuit and the second delay circuit each include at least one inverter and at least one delay element for generating a predetermined delay, and the first delay circuit and the second delay circuit have different filtering characteristics.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: December 23, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sung Man Pang, Chang Jae Heo
  • Patent number: 8912843
    Abstract: An ultra low cut-off frequency filter. A filter circuit includes a control circuit responsive to an input signal and a feedback signal to generate a control signal. The filter circuit includes a controllable resistor coupled to the control circuit. The controllable resistor is responsive to a reference signal and the control signal to generate the feedback signal. The filter circuit includes a feedback path coupled to the control circuit and the controllable resistor to couple the feedback signal from the controllable resistor to the control circuit, thereby removing noise from at least one of the input signal and the reference signal, and preventing voltage error in the filter circuit.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: December 16, 2014
    Assignee: Cadence AMS Design India Private Limited
    Inventors: Prasun Kali Bhattacharyya, Sumanth Chakkirala, Prakash Easwaran
  • Patent number: 8912844
    Abstract: The present invention provides a semiconductor structure, including a substrate, a first TSV, an inductor and a capacitor. The first TSV is disposed in the substrate and has a first signal. The inductor is disposed in the substrate. The capacitor is electrically connected to the inductor to form an LC circuit to bypass the noise from the first signal. The present invention further provides a method of reducing the signal noise in a semiconductor structure.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: December 16, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Tzung-Lin Li, Chun-Chang Wu, Chih-Yu Tseng
  • Patent number: 8901995
    Abstract: Sallen-Key active low pass filters (LPFs) have been knows for many years; however, these LPFs generally include passive components (i.e., resistors and capacitors) and active components (i.e., amplifiers) that are within the direct signal path that can contribute to the noise at the output of the filter within the pass band. Here, an LPF (which has the same general behavior as a Sallen-Key LPF) has been provided that AC couples passive components and active components to the direct signal path so as to suppress the noise contribution in the pass band.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Adam L. Shook
  • Patent number: 8884689
    Abstract: A low pass filter comprises a filter input node configured to receive a first logic signal, a filter output node configured to supply a second logic signal, a resistive element comprising a first terminal coupled to the input node and a second terminal coupled to the output node, and a capacitive element comprising a first terminal coupled to the output node and a second terminal. The filter further comprises an inverting gate having a first terminal coupled to the input node and a second terminal coupled to the second terminal of the capacitive element.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: November 11, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francois Tailliet, Marc Battista
  • Publication number: 20140312966
    Abstract: Active EMC filter connectable between an electric power source and an electric load, comprising: capacitors (C×N, C×U) connected between active conductors of said power source and a star point electric node; a filter capacitor (Cst, CstU) connected between said star point and ground; a half-bridge comprising two switching devices (T3, T4; T1, T2) connected in cascade between a positive supply voltage and a negative supply voltage; a smoothing circuit (RgN, LgN; RgU, RgU) connected between a common node of said switching devices and said star point; and a control unit (Drive_N, Drive_U) driving said switching devices (T3, T4; T1, T2) digitally either in an ON-state or in an OFF-state, such as to limit a leakage current.
    Type: Application
    Filed: April 15, 2014
    Publication date: October 23, 2014
    Applicant: Schaffner EMV AG
    Inventors: Eckart HOENE, Andre Domurat-Linde, Oleg Zeiter
  • Patent number: 8866542
    Abstract: The low frequency filter for biomedical applications scales down the pole frequency while accomplishing a 5-bit reduction in the cut off frequency. This is made possible through adding a passive resistor in the forward path of the op-amp-based integrator, introducing a difference term of the pole frequency. Moreover, the filter topology is modified to avoid changing the quality factor. An exemplary second-order low pass filter is designed and simulated. Simulation results show that the pole frequency is scaled down from 1.43 MHz to 4.97 kHz, while maintaining tuning of 30% around the nominal value by controlling only one resistor.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: October 21, 2014
    Assignees: King Fahd University of Petroleum and Minerals, King Abdulaziz City for Science and Technology
    Inventors: Yaqub Al-Hussain Mahnashi, Hussain Abdullah Alzaher
  • Patent number: 8830107
    Abstract: A frequency translating analog-to-digital converter for receiving an analog band-pass signal is described. The analog-to-digital converter comprises an adder/input block for receiving the analog band-pass signal and an analog band-pass feedback signal, thereby forming an analog band-pass error signal. The analog-to-digital converter has at least one analog mixer for mixing and down converting the analog band-pass error signal and thus generating a down-converted analog error signal and at least one quantization path for generating at least one digital signal.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: September 9, 2014
    Inventor: Udo Karthaus
  • Patent number: 8823465
    Abstract: A clock generator is disclosed for use with an oscillator device. The clock generator may include a signal conditioning pre-filter and a comparator. The signal conditioner may have an input for a signal from the oscillator device, and may include a high pass filter component and a low pass filter component. The high pass filter component may pass amplitude and frequency components of the input oscillator signal but reject a common mode component of the oscillator signal. Instead, the high pass filter component further may generate its own common mode component locally over which the high frequency components are superimposed. The low pass filter component may generate a second output signal that represents the locally-generated common mode component of the first output signal. The clock generator may have a comparator as an input stage which is coupled to first and second outputs of the filter structure.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: September 2, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Donal Bourke, Dermot O'Keeffe
  • Patent number: 8810308
    Abstract: A filter is provided. The filter receives an input signal and generates an output signal according to the input signal. The filter includes an input network, a high-pass network, and an operational circuit. The first input network provides a first normal path for the input signal to generate a first normal signal. The first high-pass network provides a first high-pass path for the input signal to generate a first high-pass signal. The operational circuit has first and second input terminals. The polarity of the second input terminal is inverse to that of the first input terminal. The operational circuit receives the first normal signal by the first input terminal and the first high-pass signal by the second input terminal such that a subtraction operation is performed on the first normal signal and the first high-pass filter to accomplish a low-pass filtering operation for generating the output signal.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: August 19, 2014
    Assignee: MediaTek Inc.
    Inventors: Yu-Hsin Lin, Hung-Chieh Tsai, Chi-Lun Lo, Chen-Yen Ho
  • Patent number: 8805314
    Abstract: To implement a filter circuit with low noise and a low cutoff frequency in a smaller area, a filter circuit has a first circuit which receives an input signal supplied to an input terminal, amplifies the signal, and outputs the amplified signal to an output terminal, a first differential amplification circuit for receiving the output signal of the first circuit through a first capacitance element, a first resistance element for forming a negative feedback path between the input and output of the first differential amplification circuit, and a second resistance element for forming a negative feedback path between the output of the first differential amplification circuit and the input of the first circuit.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: August 12, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuku Katsube, Takeshi Uchitomi, Yutaka Igarashi
  • Patent number: 8797097
    Abstract: A filtering device, applicable in a transceiver, includes: a capacitive circuit coupled to an amplifying circuit by a first capacitive configuration or by a second capacitive configuration; and a resistive circuit coupled to the amplifying circuit by a first resistive configuration or by a second resistive configuration; wherein when the capacitive circuit is the first capacitive configuration, the filtering device is used to perform a first filtering process upon a receiving signal of the filtering device, and when the capacitive circuit is the second capacitive configuration, the filtering device is used to perform a second filtering process upon a transmitting signal of the filtering device.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: August 5, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventor: Pei-Ju Chiu
  • Patent number: 8791736
    Abstract: This invention provides a loop filter device and a method for IC designers to adjust the pole or zero location of a phase lock loop (PLL) circuit. The pole and zero location are controlled by an amplifier and some on-chip resistor and capacitor components. The effective capacitance is magnified by the gain of the amplifier. The advantage of the loop filter device and the method according to embodiments of the present invention provides a feasible way to achieve a very low bandwidth in the PLL circuit without a huge external surface-mount capacitor.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: July 29, 2014
    Inventor: Yen Dang
  • Patent number: 8779831
    Abstract: An integrator (100) comprises an amplification and phase shifting element (170) with a feedback path (130) forming a loop and comprising a capacitive element (140). An input signal is summed into the loop, and the loop is arranged to oscillate at an oscillation frequency higher than the frequencies of interest in the input signal. The loop includes a filter (160) for attenuating the oscillation signal to ensure that the amplification and phase shifting element (170) can provide amplification for the input signal. The input signal is integrated and the integrated signal perturbs the zero crossings of the oscillation signal.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: July 15, 2014
    Assignee: ST-Ericsson SA
    Inventor: Bas Maria Putter
  • Patent number: 8723567
    Abstract: This invention provides a loop filter device and a method for IC designers to adjust the pole or zero location of a phase lock loop (PLL) circuit. The pole and zero location are controlled by an amplifier and some on-chip resistor and capacitor components. The effective capacitance is magnified by the gain of the amplifier. The advantage of the loop filter device and the method according to embodiments of the present invention provides a feasible way to achieve a very low bandwidth in the PLL circuit without a huge external surface-mount capacitor.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: May 13, 2014
    Inventor: Yen Dang
  • Patent number: 8710921
    Abstract: There is described a continuous time filter of at least a second (or higher) order, comprising one or more first order filter stages of a first type, the or each first order filter stage of the first type comprising a reactive component and an impedance dependent on the difference between the input and output voltages of the filter stage. The filter includes at least one first order filter stage of a second type, the or each second order filter of the second type comprising a reactive component and an impedance dependent on the sum of the input and output voltages of the filter stage. The filter includes a transfer function of the continuous time filter that is obtained comprising complex poles.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: April 29, 2014
    Assignee: ST-Ericsson SA
    Inventors: Matteo Conta, Andrea Baschirotto, Stefano D'Amico
  • Patent number: 8674754
    Abstract: A loop filter includes an input terminal, an output terminal, and a control terminal for a selection signal. At least one low pass filter is disposed between that input terminal and that output terminal. The loop filter is adapted to select a configuration out of a first configuration and at least one second configuration in response to the selection signal. In the first configuration, the loop filter comprises a non-integrating transfer characteristic in operation. In the second configuration, the loop filter comprises an integrating signal transfer characteristic in operation.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: March 18, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Burkhard Neurauter, Harald Pretl, Rastislav Vazny, Thomas Greifeneder
  • Patent number: 8664998
    Abstract: An adaptive filter circuit for sampling a reflected voltage of a transformer of a power converter includes a first switch for receiving the reflected voltage, a resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the first switch, a capacitor coupled to the second terminal of the resistor for holding the reflected voltage, and a second switch coupled to the resistor in parallel, wherein the resistor and the capacitor develop a filter for sampling the reflected voltage which is sampled without filtering by the filter in a first period during a disable period of a switching signal and also sampled with filtering by the filter in a second period during the disable period of the switching signal.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: March 4, 2014
    Assignee: System General Corporation
    Inventors: Ta-Yung Yang, Li Lin, Jung-Sheng Chen, Chih-Hsien Hsieh, Yue-Hong Tang
  • Patent number: 8664987
    Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: March 4, 2014
    Assignee: SK Hynix Inc.
    Inventors: Dae-Han Kwon, Yong-Ju Kim, Taek-Sang Song
  • Patent number: 8648653
    Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: February 11, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: David R. Welland, Donald A. Kerth, Caiyi Wang
  • Publication number: 20140003102
    Abstract: A phase angle detector with a PLL, a power converter, and a method for reducing offsets in an input signal, in which an adaptive offset processor selectively removes a DC offset component from the input signal to generate a modified signal including a fundamental frequency component and higher order harmonics of the input signal with the DC offset component removed, and the PLL provides a phase angle signal at least partially according to the modified signal.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicant: ROCKWELL AUTOMATION TECHNOLOGIES, INC.
    Inventors: Russel J. Kerkman, Ahmed Mohamed Sayed Ahmed, Brian J. Seibel
  • Patent number: 8620251
    Abstract: An electronic device includes an adjustable filter with a first filter element, and a second filter element coupled to the first filter element. The second filter element includes a field effect transistor (FET) including a source terminal, a drain terminal, and a gate terminal. The source terminal and the gate terminal are coupled to a reference voltage. A control circuit is coupled to the drain terminal and is configured to apply a control voltage thereto to vary a capacitance between the source and drain terminals to adjust the adjustable filter.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: December 31, 2013
    Assignee: Harris Corporation
    Inventors: Andrew Mui, Anthony Manicone
  • Patent number: 8593216
    Abstract: A loop filter with noise cancellation includes first and second signal paths, an operational amplifier (op-amp), and a noise cancellation path. The first signal path provides a first transfer function (e.g., a lowpass response) for a first signal. The second signal path provides a second transfer function (e.g., an integration response) for a second signal. The second signal is a scaled version of, and smaller than, the first signal by a factor of alpha, where alpha is greater than one. A capacitor in the second signal path may be scaled smaller by a factor of alpha. The op-amp couples to the first and second signal paths and facilitates summing of signals from the first and second signal paths to generate a control signal having op-amp noise. The noise cancellation path couples to the op-amp and provides a noise cancellation signal used to cancel the op-amp noise in the control signal.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: November 26, 2013
    Assignee: QUALCOMM Incorporated
    Inventor: Gang Zhang
  • Patent number: 8575988
    Abstract: A mixed signal correlator utilizes coherent detection within a capacitance measurement application. In some applications, the mixed signal correlator is used to measure capacitance of a touch screen display. An external capacitor whose capacitance is measured is kept small for improved sensitivity and can be used for a variety of applications having varied integration periods for measurement. The external capacitor is kept small and can be used for varied applications by adjusting the output voltage within a range that is less than the supply voltage, and maintaining a count of the adjustments to later reconstruct an actual output voltage for the integration period. An output is a weighted sum of an analog integrator output and a digital counter output.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: November 5, 2013
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Ozan E. Erdogan, Guozhong Shen, Rajesh Anantharaman, Ajay Taparia, Behrooz Javid, Syed T. Mahmud
  • Patent number: 8570099
    Abstract: A filter including common mode feedback can provide single-ended to differential-ended conversion with minimum loss of performance.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: October 29, 2013
    Assignee: Synopsys, Inc.
    Inventors: Ka Hou Ao Ieong, Seng Pan U
  • Publication number: 20130278330
    Abstract: A low pass filter comprises a filter input node configured to receive a first logic signal, a filter output node configured to supply a second logic signal, a resistive element comprising a first terminal coupled to the input node and a second terminal coupled to the output node, and a capacitive element comprising a first terminal coupled to the output node and a second terminal. The filter further comprises an inverting gate having a first terminal coupled to the input node and a second terminal coupled to the second terminal of the capacitive element.
    Type: Application
    Filed: April 23, 2013
    Publication date: October 24, 2013
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Francois Tailliet, Marc Battista
  • Patent number: 8547170
    Abstract: Techniques are disclosed for radiation sensors that generate current signal to provide flexible placement of one or more integration intervals between resets of an integration capacitor. With flexible timing, an embodiment of the present invention provides several modes of operation including: multiple stray light blanking interval to occur during the integration cycle; range gating for LIDAR applications; time-delay-integration (TDI) with multiple short integration periods between frame resets; and hyper-resolution gating that provides better resolution than is normally possible with a fixed gate width. Numerous variations will be apparent in light of this disclosure.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: October 1, 2013
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: James A Stobie, Harold T Wright
  • Publication number: 20130249625
    Abstract: In order to output an accurate waveform in which quantization noise has been cancelled out, provided is a signal generating apparatus that outputs an output signal corresponding to a waveform data sequence expressing a waveform, the signal generating apparatus comprising a DA converting section that outputs an analog signal by sequentially performing digital/analog conversion on each piece of data included in the waveform data sequence, at a timing of a sampling clock; and a jitter injecting section that injects jitter decreasing a quantization noise component of the output signal, into the sampling clock supplied to the DA converting section.
    Type: Application
    Filed: January 31, 2013
    Publication date: September 26, 2013
    Applicant: ADVANTEST CORPORATION
    Inventor: Kiyotaka ICHIYAMA
  • Publication number: 20130234688
    Abstract: Provided are a low pass filter circuit having a small output voltage shift caused by a substrate leakage current at high temperature, and a voltage regulator using the low pass filter circuit, which has a small output voltage shift at high temperature. In a low pass filter circuit using a PMOS transistor as a resistive element, a back gate terminal of the PMOS transistor is set to have a higher voltage than a source of the PMOS transistor. Further, in a voltage regulator incorporating the low pass filter circuit to an output of a reference voltage circuit, the voltage of the back gate terminal of the PMOS transistor which is higher than that of the source thereof is generated by the reference voltage circuit.
    Type: Application
    Filed: February 27, 2013
    Publication date: September 12, 2013
    Applicant: SEIKO INSTRUMENTS INC.
    Inventor: Kaoru SAKAGUCHI
  • Patent number: 8531237
    Abstract: A low-pass filter that filters an input signal input to a filter input terminal to output a filtered output signal to a filter output terminal includes a capacitor, a first field-effect transistor, a first resistor, and a first current source. The capacitor is connected between the filter output terminal and ground. The first field-effect transistor has a gate terminal, a first conduction terminal connected to the filter input terminal, and a second conduction terminal connected to the filter output terminal. The first resistor is connected between the gate and first conduction terminals of the first transistor. The first current source is connected to the first resistor to supply a first current to the first resistor. The first resistor generates a first voltage thereacross based on the supplied first current for electrically biasing the gate terminal of the first transistor.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: September 10, 2013
    Assignee: Ricoh Company, Ltd.
    Inventor: Katsuhiko Aisu
  • Patent number: 8514012
    Abstract: In one embodiment, a circuit-based apparatus that operates on an input data stream includes delay-line circuitry that characterizes the input data stream, modified over time. A plurality of integrators provide a plurality of integrated signals in response to the delay-line circuitry, and a plurality of weighting amplifiers amplify the plurality of integrated signals by a plurality of respective time-varying weighting factors to provide weighted signals. A signal-combining circuit combines the weighted signals. The circuit-based apparatus also includes a plurality of parallel signal-processing circuit paths that couple the weighted signals to the signal-combining circuit. By combining the weighted signals from the parallel signal-processing circuit paths, the signal-combining circuit provides a signal representative of the input data stream.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: August 20, 2013
    Assignee: NXP B.V.
    Inventors: Mike Hendrikus Splithof, Edwin Schapendonk