Abstract: A driving current flowing through a first output transistor is given to a stator coil of a three-phase motor (first operation), a driving current flowing through the stator coil is output to the ground through a second output transistor (second operation), and no current flows through the stator coil during the off-state of both the first and second output transistors (third operation). Charge remaining in a gate of the first output transistor is rapidly output to the ground through an n-channel transistor for a short time at both the end of the first operation and the start of the second operation. Charge of a high voltage remaining in the stator coil is output to the ground through a voltage clamp circuit as a clamp current during the first and second operations while controlling the clamp current to a low value in a constant current circuit.

Abstract: Voltage level translators are presented, inter alia, for operating an operational amplifier integrated circuit designed for operation with a single ended power supply, to operate with a split level power supply having a center tapped ground. A first polarity power supply terminal of a operational amplifier integrated circuit is coupled to a first polarity of the of the split level power supply, and a second polarity power supply terminal of the operational amplifier integrated circuit is coupled to a second polarity of the power supply, with a positive signal input terminal of the operational amplifier being coupled to a center tapped ground of the split level power supply.

Abstract: A method and apparatus for calibrating a Gm cell using a Gm replica cell. A digital to analog converter receives a Gm setting code and generates a reference current. The Gm replica cell adjusts the tuning voltage until the difference between a pair of drain currents is substantially equal to the reference current. Where this condition is satisfied, the proper tuning voltage has been acquired. This results in proper calibration for the tuning voltage, which then may be utilized by a Gm cell connected with the Gm replica cell.

Abstract: A Veff detector circuit generates input voltages VEP, VEN on the basis of a bias voltage which is fed back so that the difference between these input voltages may be a saturation voltage Veff, and a four-input operational amplifier means receives the input voltages VEP, VEN generated by the Veff detector circuit and generates the bias voltage VB by using reference voltages VERP, VERN which are externally inputted.

Abstract: Level shift circuit includes an operational amplifier, and an input resistor having one end connected to an output terminal of an amplifier circuit and the other end connected to the inverted input terminal of the operational amplifier. The level shift circuit further includes a level-shifting resistor of a resistance value R0 having one end connected to the inverted input terminal of the operational amplifier and the other end connected to a ground, and a feedback resistor of a resistance value R1. Reference voltage Vref is applied to the noninverted input terminal of the operational amplifier. Output signal of the level shift circuit represents the output of the amplifier circuit having been shifted in level by a predetermined amount.

Abstract: An integrated circuit input buffer is provided, which includes a differential buffer, first and second average value circuits and a feedback amplifier. The input buffer is selectively operable in a differential operating mode and a single-ended operating mode. The differential amplifier has first and second buffer inputs and first and second buffer outputs. The first and second average value circuits have inputs coupled to the first and second buffer outputs, respectively. The feedback amplifier has first and second differential inputs coupled to outputs of the first and second average value circuits, respectively, and has an amplifier output. The amplifier output is coupled to the second buffer input when the input buffer is in the single-ended operating mode and is decoupled from the second buffer input when the input buffer is in the differential operating mode.

Abstract: A MOS differential amplifier circuit has a differential pair having first and second MOS transistors. The source electrodes of the first and second MOS transistors are commonly coupled and driven by a current source, which can be adjusted to change the transconductance of the amplifier. The circuit can be provided with a quadri-tall cell or level shifter in order to provide this operation. With these operational characteristics, the MOS differential pair of this type can be used in a voltage adder/subtractor circuit.

Abstract: An output buffer is provided in the form of a voltage follower having a positive input that receives a reference voltage, a negative input and an output coupled together, and a control input that turns the voltage follower on and off. The output is coupled to one side of a load. The output buffer may have one or more additional voltage followers. For example, the output buffer may include three additional voltage followers with all voltage followers arranged as a low voltage differential signal (LVDS) buffer.

Abstract: A differential comparator having offset correction and common mode control for providing stable op amp output that changes only due to the original inputs coming into the comparator. The difference comparator has increased common-mode difference tolerance, and large op-amp offset tolerance, as well as fast decision time.

Abstract: A novel operational amplifier is disclosed which is divided into an input stage, a common mode feedback stage and an output stage. The output of the operational amplifier swings rail to rail, and the input may swing nearly rail to rail. The operational amplifier combines fast response with low power consumption and low supply voltage.

Abstract: An operational amplifier comprises multiple stages. A differential input stage that includes an adaptive high voltage differential pair generates up and down output currents in response to up and down input voltages. The differential input stage includes adaptive common input high voltage (HV) bias. An intermediate stage converts the up and down output currents into a first output voltage signal. The intermediate stage includes a folded cascode arrangement. The intermediate stage is biased by fixed voltage bias signals. The intermediate stage also includes unaffected slew rate stability compensation and a combined split stability compensation. An output stage includes a class AB source follower driver that generates a second output voltage signal in response to the first output voltage signal. The output stage is biased with an adaptive push-pull source follower output HV bias. The output stage includes feed-forward slew rate enhancement.

Abstract: A loop filter in the phase-locked loop includes a capacitor having a specific capacitance value. The loop filter also includes an amplifier coupled to a node of the capacitor. The amplifier amplifies a signal at the node in a way that increases the equivalent capacitance value without physically changing the capacitor.

Abstract: Summarizing, the present invention provides an IVC (100), comprising an operational amplifier (110) with an inverting input (112) and an output (113), and a feedback resistor ladder network (120) coupled between the output (113) and the inverting input (112). The feedback resistor ladder network (120) comprises a main chain (121) composed of a plurality of substantially identical unit resistors (RU) connected in series, and a plurality of branches (124i), each branch (124i) coupling a node (Xi) in the main chain (121) to the inverting input (112) of the operational amplifier (110), each branch (124i) comprising a selectable feedback switch (123i). Further, some of the branches (124i) comprise a non-unit resistor (RNUi) coupled in series with the corresponding selectable feedback switch (123i). Further, the present invention provides a circuit comprising a FIRDAC (20) and a bias block (30) for providing at least one bias current for the FIRDAC (20).

Abstract: A controller that is linearly responsive to an input voltage provides continuously adjustable control of the width of a periodically repeating digital pulse, thereby achieving a linear voltage to duty-cycle ratio transfer function. The circuit of the present invention includes a master clock input, a ratio control voltage input, a controlled duty cycle clock output, a high gain amplifier configured as an integrator having differential inputs, each equipped with a low pass filter, a controlled current source, a resettable timing capacitor, a threshold detector and a reference pulse generator.

Abstract: A current sense amplifier including a transconductance amplifier to measure a current passing through a sense resistor and generate a reference current indicative of the measured current. A current mirror circuit is connected to the transconductance amplifier and receives the reference current for amplification to generate an amplified output current. A cascode circuit is connected serially to the current mirror circuit to boost an output impedance for the amplifier at the output of the generated amplified output current. The current mirror circuit and cascode circuit of the current sense amplifier are each formed from a pair of transistors sharing a common control node, with the transistors realized using with bipolar or MOS technology.

Abstract: A CMOS programmable gain amplifier (10) is disclosed which provides exponential gain using a single gain element (19) which may be implemented in either bipolar or CMOS technology. An embodiment of the present invention includes a first and second sampling impedance (12, 14), a first and second feedback impedance (16, 18) and a gain element (19). The gain element (19) having an inverting input, a non-inverting input and an output. The inverting input connects to the first sampling impedance (12). The non-inverting input connects to the second sampling impedance (14). The first feedback impedance (16) connects between the inverting input and the output. The second feedback impedance (18) connects between the non-inverting input and the output.

Abstract: An output buffer is provided in the form of a voltage follower having a positive input that receives a reference voltage, a negative input and an output coupled together, and a control input that turns the voltage follower on and off. The output is coupled to one side of a load. The output buffer may have one or more additional voltage followers. For example, the output buffer may include three additional voltage followers with all voltage followers arranged as a low voltage differential signal (LVDS) buffer.

Abstract: A method for coupling a differential signal generated by a digital processing unit includes high-pass filtering the differential signal. The filtered output of the high-pass filter is then provided to an input of a differential amplifier, the output of which is fed back to the input of the differential amplifier.

Abstract: Digitally-operated analog buffer amplifiers which are characterized by small circuits, no offset voltage, high speed and low power consumption. Circuit means are provided so that when the value of the output voltage of the buffer amplifier nears the approximate value (set voltage value) of the input voltage value, the input terminal and output terminal short-circuit so that the output voltage and the input voltage are made equal, thereby preventing the generation of offset voltage. Power consumption is reduced because the circuit completes the operation in a digital operation state.

Abstract: A ring inhibiting charging and discharging circuit (100) for use with an amplification circuit (102) that drives a load (108) is responsive to an input (104) and is capable of generating an output (106) corresponding to the input (104). The ring inhibiting charging and discharging circuit (100) includes a charge element (120) that is responsive to the output (112) from the amplification circuit (102). The charge element (120) is capable of charging the load when the input voltage is greater than a preselected multiple of the output voltage. A discharge circuit (130) is responsive to the output (106) from the amplification circuit (102) and includes a feedback circuit (132) and a staging circuit (134). The feedback circuit (132) asserts a difference signal when the output voltage is less than the preselected multiple of the input voltage.

Abstract: A transimpedance circuit adapted for use in a subscriber line interface circuit includes sense resistors installed in closed loop, negative feedback paths of respective sense amplifiers. Voltage drops across the sense resistors are applied to first and second differential coupling circuits for applying differential currents to complementary polarity inputs of an operational amplifier. The inputs of the amplifier are also coupled to a linearity compensator, that is configured to provide sufficient overhead voltages in the presence of worst case voltage swing conditions. The compensator has a differential amplifier configuration, that closes a negative feedback loop from the output of the amplifier and one of its inputs, relative to a reference voltage balancing path coupled to the amplifier's other (complementary) input.

Abstract: Eight resistors having resistance values of R×2i (i=0 to 7) (&OHgr;) are serially connected while eight switches exhibiting parasitic resistance values of r×2i (&OHgr;) in ON states are connected in parallel with the resistors respectively, for changing a resistance value by turning on/off the switches. The resistors are connected between an inversion input terminal of an operational amplifier and a terminal, and a non-inversion input terminal receives a prescribed reference voltage. Between the inversion input terminal and an output terminal of the operational amplifier, a resistor and a switch of a variable resistance circuit forming a negative feedback loop are connected to the output terminal while another resistor and another switch are connected to the inversion input terminal.

Abstract: A low power reference buffer includes a new amplifier design with very large transconductance and high frequency non-dominant poles and a triple bonding scheme to a large off-chip capacitor that avoids the problems related to the lead wire inductance.

Abstract: The present invention relates to an input buffer for a switched emitterfollower-like track-and-hold amplifier comprising an input stage with an input transistor (Q1), a first diode (Q2, Q2b), a cathode side of which first diode (Q2, Q2b) is connected to an emitter of the input transistor (Q1), a first current source (4) between on the one hand the junction between the cathode of the first diode (Q2, Q2b) and the emitter of the input transistor (Q1) and on the other hand a first supply voltage line (2), an anode of the first diode (Q2, Q2b) being connected to a track-and-hold controlled emitterfollower (6). The first current source (4) is a non-switched constant current source, and a second current source (M1) is connected between a collector of the input transistor (Q1) and a second supply voltage (3).

Abstract: A semiconductor integrated circuit comprises an amplifier circuit including a current output amplifier, a load resistor having one end connected to an output terminal of the current output amplifier and a voltage control circuit having an input terminal connected to the one end of the load resistor and an output terminal connected to an other end of the load resistor. The input terminal of the amplifier circuit serves as an input terminal of the current output amplifier, and the output terminals of the amplifier circuit serve as the individual ends of the load resistor.

Abstract: A signal level monitoring circuit for outputting either voltage or current corresponding to an input signal level, includes a variable gain unit for obtaining a predetermined output level without being dependent on a gain, when the input signal level is a predetermined reference input level; and an offset adding unit for outputting a predetermined reference output level by adding an offset level to the output level of the variable gain means, when the input signal level is the predetermined reference input level. According to the present invention, it is possible to adjust precisely and surely the gain and the offset voltage based on simple adjusting steps in a short time and only once.

Abstract: A method and system for calibrating analog integrated circuits. Initially, a single calibration circuit is formed integral with a group of analog integrated circuits. A control signal and a calibration signal are generated from the calibration circuit. Next, the control signal and the calibration signal are selectively coupled to an input of a particular analog integrated circuit among the group of analog integrated circuits. The particular analog integrated circuit is then selected for calibration via the control signal.

Abstract: A low power pulse amplifier with low duty cycle errors. The amplifier provides several differential amplifier stages with a biasing and canceling network. To minimize duty cycle errors for large input signals, cascode transistors are added between the drains of the differential amplifiers and the outputs. The result is an amplifier having a duty cycle error of less than 5% at amplitude input ranges from 5 millivolts to the supply voltage.

Abstract: The present application discloses an innovative improved circuit, in which the long transient at write-to-read transitions is avoided by using a shorting switch to short the inputs of the first amplifier stage together when the read amplifier is activated. This speeds up write-to-read transition. Moreover, since read mode can now be entered more quickly after a power-down condition, this circuit also permits the use of other power-saving tricks to idle the read amplifier momentarily.

Abstract: A method and circuitry are disclosed for enhancing the operational bandwidth of a signal amplification circuitry system; for example, comprising providing an amplification circuit for amplifying the electrical signal, providing buffer circuitry adapted to negate capacitive loading effects between amplifier stages, and coupling said buffer circuitry between the amplification circuitry and collateral circuitry such that the buffer circuitry isolates the amplification circuitry from the effects of capacitive loading originating from the collateral circuitry. Enhancement in the operational bandwidth of the amplification circuit results. A plurality of buffer circuit elements 162 and 352 are coupled within amplifier stages 100, 200, and 300 negating the transitive effects of capacitive loading between the amplifier stages.

Abstract: A method and apparatus for adjusting the resistance across a slave transistor to follow a master resistor network are disclosed. A tuning circuit is disclosed which is used to control the effective resistance of a slave transistor for use in high speed integrated automatic gain control, equalizer, filter or equivalent types of circuits where low parasitic capacitance is desired. The invention provides a way to replace a resistor network and its associated high parasitic capacitance with an equivalent resistance having low parasitic capacitance. The invention replaces the resistor network, having large parasitic capacitance, with a slave transistor exhibiting an equivalent resistance, having low parasitic capacitance. An automatic tuning circuit containing a resistor network is located remotely to a circuit containing a slave transistor. The tuning circuit is then used to adjust the effective resistance of the slave transistor.

Abstract: An interface circuit for interfacing a data bus with a current sinking sensor or a current sourcing sensor. An input terminal is connected between a cathode of a first diode and an anode of a second diode. The anode of the first diode is connected to a first input terminal of a comparator, such as a differential amplifier. The cathode of the second diode is connected to a second input of the comparator. Two pairs of in-series resistors are connected between a voltage supply. The anode of the first diode is connected between two resistors of the first pair of resistors. The cathode of the second diode is connected between two resistors of the other pair of resistors. An output of the comparator is connected to an output terminal. The interface circuit of this invention can be connected between an input circuit and an output circuit, to interface a sensor parameter and the corresponding input current or signal to the data bus and a corresponding output current or signal.

Abstract: To achieve a constant control range in an integrator-filter circuit for filtering a push-pull signal, having at least two integrator elements (1) this second control current being having resistors (11, 12) arranged at its inputs, a subsequent current multiplier (13) having two signal inputs (14, 15) and preceding a push-pull amplifier (18) with an inverting input (20) and a non-inverting input (19), having inverting output (21) fed back to the non-inverting input (19) and a non-inverting output (23) fed back to the inverting input (20) via capacitances (22, 24), the current multiplier (13) receiving, at two control inputs (37, 38), a first and a second control current (I.sub.1, I.sub.2) for adjusting the integration time constant of the integrator element (1) is adjustable and from which the second control current (I.sub.2) flows in substantially two halves through the signal inputs (14, 15) of the current multiplier (13), an associated third control current (I.sub.

Abstract: An OTA having a completely linear transconductance characteristic or a squarer having an accurate square-law characteristic is provided, which is comprised of first and second differential circuits. The first differential circuit has a first differential pair of first and second MOSFETs whose sources are coupled together and a third MOSFET serving as a bypass transistor for the first differential pair. The first differential pair is driven by a first constant tail current. The second MOSFET is driven by a first constant driving current. The second differential circuit has a second differential pair of fourth and fifth MOSFETs whose sources are coupled together and a sixth MOSFET serving as a bypass transistor for the second differential pair. The second differential pair is driven by a second constant tail current. The fifth MOSFET is driven by a second constant driving current.

Abstract: A differential output amplifier arrangement (DOA) including two operational amplifiers (OA1,OA2), each having a feedback resistor (R2,R20), and which are coupled by a first resistor (R1) between similar polarity type input terminals, further includes a pair of output resistors (R3,R30), coupled between respective output terminals (OUT1,OUT2), of each respective operational amplifier, and corresponding respective output terminals (ZOUT1,ZOUT2) of said arrangement, and a pair of resistors (R4,R40), each of which is cross-coupled between a respective output terminal of said arrangement (ZOUT1,ZOUT2) and one of the two similar polarity type, by the first resistor coupled, input terminals (INN2,INN1) of the respective cross-coupled operational amplifier. A method for adapting the output impedance of a differential output amplifier arrangement is described as well.

Abstract: A low power reference buffer includes a new amplifier design with very large transconductance and high frequency non-dominant poles and a triple bonding scheme to a large off-chip capacitor that avoids the problems related to the lead wire inductance.

Abstract: A variable transconductance method and circuit is disclosed along with a filter and an amplifier using the same. An output transconductance is set by selectively adding at least two transconductances which are set according to a select signal for variably selecting an output transconductance.

Abstract: A shock sensor circuitry (26) is provided for processing an input signal generated by a shock sensor (28) in response to the shock sensor (28) detecting a force or shock. The shock sensor circuitry (26) includes a leakage tolerant input amplifier (38) for receiving the input signal, and any leakage currents that may also be provided, and amplifying the input signal to generate an amplified input signal. The leakage tolerant input amplifier (38) provides an ac gain of ten and a dc gain of zero. The shock sensor circuitry (26) also includes a filter and amplification circuit and a window comparator. The filter and amplification circuit filters the amplified input signal and amplifies select frequencies of the amplified input signal to generate a summed signal that is provided to the window comparator and compared to a reference value.

Abstract: A low leakage solid state switch for range-changing uses a pair of low leakage diodes switched to a reference voltage to block leakage through the switch when it is in the "off" state.

Abstract: A wide-band, high-order, programmable video filter is implemented using transimpedance-based active integrators. An input voltage which may for instance represent a composite video signal is converted to a current in a linear manner using resistors and provided to a current amplifier at low impedance virtual ground nodes. The current is multiplied by a gain factor .beta..sub.R within the current amplifier and supplied to integrating capacitors connected in a feedback configuration around a high input impedance differential amplifier to establish an integrated differential voltage output. The transimpedance-based active integrators may be interconnected to realize wide-band, high-order video filters suitable for use in accordance with CCIR 601 standards. Input voltage swings are not restricted by a transistor's limited range of linear operation or voltage swing limitations of internal nodes but rather may allowed to swing as long as the bias currents sustain input current excursions.

Abstract: A semiconductor sensor device using a semiconductor material for the sensor and having a circuit configuration in which the operational amplifier of the final amplification stage forms an inverting amplifier circuit, and a pull-up resistance is connected to the output terminal of the operational amplifier, includes a saturation circuit for saturating the output voltage of the operational amplifier when the voltage of the inverting input terminal of the operational amplifier of the final amplification stage drops below a voltage value .alpha. at which the output voltage from the output terminal is saturated.

Abstract: A CMOS analog divider/multiplier/ratiometry circuit that provides a ratiometric output of two or more inputs, where the output is insensitive to process parameters and temperature variations effecting the circuit. The analog divider/multiplier/ratiometry circuit includes a multiplier portion made up of six FET devices. The six FET devices are electrically connected together so that first and second current outputs from the multiplier portion are insensitive to process parameter and temperature variations effecting the circuit. A first input current is applied to a gate terminal of one of the FET devices and a second input current is applied to a gate terminal of the FET devices in the multiplier portion of the circuit. The first and second input currents are based on currents generated by first and second linear voltage-to-current converter input circuits that are responsive to first and second input voltage, respectively, whose ratio or product is to be determined at the output of the circuit.

Abstract: An operational amplification circuit having no crossover distortion includes a pair of differential amplification circuits, a pair of level shift circuits, a pair of current source circuits, and an output circuit. Each of the differential amplification circuits includes two MOS transistors having gates connected to a respective pair of input terminals. The differential amplification circuits generate first and second signals. The level shift circuits connected to the differential amplification circuits shift the level of the first and second signals. Each of the level shift circuits includes complementary MOS transistors. The current source circuits supply a predetermined current to one of the transistors of the level shift circuits. The output circuit is connected to the level shift circuits for generating an output signal.

Abstract: A high-speed/high-slew-rate tri-modal all bipolar buffer/switch includes a unity-gain amplifier, a voltage source, and a maximum level detector and a minimum level detector adjusting a current source to sink or source current as required to quickly make the output voltage of the switch equal to the input voltage of the switch. The maximum level detector and the minimum level detector compare the output voltage to the input voltage. If the output voltage does not equal the input voltage, the current source acts as either a sink or source to make the output voltage equal the input voltage. In addition, the voltage switch holds a constant d.c. voltage at the output of the switch when the switch is powered down.

Abstract: An amplification circuit is composed of a differential operational amplifier internally containing a current source circuit and having an inverted input connected to an output thereof through a parallel circuit composed of a first switch and a first capacitor. The inverted input is connected to one end of a second capacitor having the other end connected to a signal input terminal through a second switch. A non-inverted input of the differential operational amplifier is connected to a first reference voltage, and the other end of second capacitor is connected through a third switch to a second reference voltage.

Abstract: An amplifier circuit for analog-signal processing has an operational amplifier having an output, an inverting input, and supply inputs for accepting a single supply potential and a reference potential. The operational amplifier has a noninverting input capable of accepting a signal voltage of a varying analog signal input thereto which has a positive value range and a negative value range relative to the reference potential. The output is fed back to the inverting input and the operational amplifier has a differential amplifier having first and second field-effect transistors. The first field-effect transistor has a gate connected to the noninverting input of the operational amplifier and the second field-effect transistor has a gate connected to the inverting input.

Abstract: An integrating circuit includes an operational amplifier and an integrating capacitor which is decoupled from the output of the operational amplifier and precharged to a positive reference voltage before each integration cycle. During each integration cycle the operational amplifier output decreases from the reference voltage toward but not below ground. This allows the operational amplifier to be included as a front-end integrator to a delta-sigma analog-to-digital converter that is powered only by a single power supply. In the described embodiment, the output is coupled to an input of an auto-zeroing stage which provides negative feedback to stabilize the operational amplifier when the integrating capacitor is disconnected during precharging and a bandwidth control input which couples a larger compensation capacitance to reduce the bandwidth during integration to reduce RMS noise.

Abstract: Low quiescent power, high output power, rail-to-rail output stage circuits and methods are provided. The output stages are capable of providing output voltages that are substantially equal to the supply voltages (i.e., within one V.sub.CE SAT of both supply voltages) without a substantial increase in output circuit complexity and without a substantial increase in quiescent current. The output stages operate by providing a direct path for the drive signal to the output sinking transistor, and an additional, separate path for the drive signal to the output sourcing transistor. The sinking and sourcing paths are separated by a PNP transistor that gradually turns off during sinking to isolate that portion of the circuit so that the drive current to the sinking transistor is not reduced. Additional embodiments are provided where additional components are utilized to further increase the maximum sink and source currents without a significant increase in quiescent current or reduction in output swing.

Abstract: An operational amplifier with improved operational speed, as well as low power consumption, arranges a current mirror made of the pMOS transistors PT.sub.17 and PT.sub.18 in the stage after the initial-stage differential amplifier, supplies the output of the initial-stage differential amplifier to the gate of the nMOS transistor NT.sub.14, supplies the current flowing through the current mirror to the output stage side by a current mirror made of the pMOS transistors PT.sub.15 and PT.sub.16, and lastly a pMOS transistor PT.sub.19 is connected as a constant-current source between the supply line for the power supply voltage V.sub.DD and the node ND.sub.12, and makes the idling current I.sub.19 flow in the node ND.sub.12. Due to this, stabilization of DC operations during normal states and when shifting its states can be designed without considering the characteristics in the vicinity of the threshold voltage of pMOS transistor PT.sub.

Abstract: In an integrated-circuit capacitive coupling circuit, first and second diodes are slightly forward-biased to develop bias voltages at their cathode terminals. Input voltages are respectively applied through first and second capacitors to the cathode terminals of the diodes. A differential amplifier is formed by first and second transistors having their bases respectively connected to the cathode terminals of the diodes for receiving the bias voltages via the diodes and the input voltages via the capacitors for developing a differential output voltage. A fast charging circuit is additionally connected to the cathode terminals of the first and second diodes to supply charging currents to the capacitors for a short period in response to a control signal.