With Specific Layout Or Layout Interconnections Patents (Class 327/565)
  • Patent number: 11277949
    Abstract: Disclosed is an electronic device. The electronic device includes a printed circuit board on which one or more circuit components are disposed, and an interposer surrounding at least some circuit components of the one or more circuit components and including an inner surface adjacent to the at least some circuit components and an outer surface facing away from the inner surface and having a plurality of through holes. The interposer is disposed on the printed circuit board such that one or more through holes of the plurality of through holes are electrically connected with a ground of the printed circuit board.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: March 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyelim Yun, Bongkyu Min, Dohoon Kim, Taewoo Kim, Jinyong Park, Jungje Bang, Hyeongju Lee
  • Patent number: 10979087
    Abstract: A radio frequency module includes a module board including a first principal surface and a second principal surface on opposite sides thereof; a transmission power amplifier; a control circuit configured to control the transmission power amplifier; a first transmission filter and a second transmission filter; and a first switch configured to switch connection of an output terminal of the transmission power amplifier between the first transmission filter and the second transmission filter. The control circuit is disposed on the first principal surface, and the first switch is disposed on the second principal surface.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: April 13, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takayuki Shinozaki, Yukiya Yamaguchi, Morio Takeuchi, Yoichi Sawada
  • Patent number: 10776327
    Abstract: A method includes generating a plurality of blocks of a block chain wherein the plurality of blocks is associated with components of a storage device. The plurality of blocks is generated by a device other than the storage device when the components are manufactured. The method further includes storing a copy of a ledger associated with the generated blocks on the storage device when the storage device comprises computing power sufficient to generate blocks of a block chain. The method also includes generating additional blocks of the block chain. The additional blocks of the block chain are associated with additional components of the storage device when the additional components are manufactured. The additional blocks are generated independently by the device and by the storage device and wherein respective ledgers are updated.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 15, 2020
    Assignee: Seagate Technology LLC
    Inventors: David R. Kaiser, Timothy John Courtney
  • Patent number: 10690717
    Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: June 23, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Lee D. Whetsel, Richard L. Antley
  • Patent number: 10651111
    Abstract: A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface of the substrate, and forming a plurality of first-side metal bumps on the first surface of the substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the substrate, and the first surface and the second surface are opposite of each other. The method includes forming a plurality of second-side metal bumps on the second surface of the substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: You-Hua Chou, Yi-Jen Lai, Chun-Jen Chen, Perre Kao
  • Patent number: 10608633
    Abstract: An electronic device includes a die stack having a plurality of die. The die stack includes a die parity path spanning the plurality of die and configured to alternatingly identify each die as a first type or a second type. The die stack further includes an inter-die signal path spanning the plurality of die and configured to propagate an inter-die signal through the plurality of die, wherein the inter-die signal path is configured to invert a logic state of the inter-die signal between each die. Each die of the plurality of die includes signal formatting logic configured to selectively invert a logic state of the inter-die signal before providing it to other circuitry of the die responsive to whether the die is designated as the first type or the second type.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 31, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Russell Schreiber
  • Patent number: 10587195
    Abstract: A system that includes multiple integrated circuits is disclosed. A first integrated circuit of the system includes a plurality of circuit blocks, and a first circuit block of the plurality of circuit blocks includes a first power terminal. A second integrated circuit of the system includes multiple voltage regulation circuits, a second power terminal coupled to an output of a given voltage regulation circuit, and a third power terminal coupled to an input of the given voltage regulation circuit. A substrate, included in the system, includes a plurality of conductive paths, each of which includes a plurality of wires fabricated on a plurality of conductive layers. The system further includes a power management unit that may be configured to generate a power supply voltage at a fourth power terminal that is coupled to the third power terminal via a first conductive path of the plurality of conductive paths.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 10, 2020
    Assignee: Apple Inc.
    Inventors: Shawn Searles, Vidhya Ramachandran
  • Patent number: 10115818
    Abstract: An illustrative bidirectional MOSFET switch includes a body region, a buried layer, a gate terminal, a first configuration switch, and a second configuration switch. The body region is a semiconductor of a first type separating a source region and a drain region that are a semiconductor of a second type. The buried layer is a semiconductor of the second type separating the body region from a substrate that is a semiconductor of the first type. The gate terminal is drivable to form a channel in the body region, thereby enabling conduction between the source terminal and the drain terminal. The first configuration switch disconnects the body terminal from the source terminal when the source terminal voltage exceeds the drain terminal voltage; and the second configuration switch connects the body terminal to the buried layer terminal when the source terminal voltage exceeds the drain terminal voltage.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: October 30, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jean-Paul Eggermont, Johan Camiel Julia Janssens
  • Patent number: 10002653
    Abstract: The dies of a stacked die integrated circuit (IC) employ the address bus to indicate the particular die, or set of dies, targeted by data on a data bus. During manufacture of the stacked die IC, the IC is programmed with information indicating a width of the address bus. During operation, each die addresses the other dies with addresses having the corresponding width based on this programmed information.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: June 19, 2018
    Assignee: NXP USA, Inc.
    Inventors: Perry H. Pelley, Michael B. McShane, Tim V. Pham
  • Patent number: 9978862
    Abstract: A semiconductor die includes a semiconductor substrate having a first region and a second region isolated from the first region. A power transistor disposed in the first region of the semiconductor substrate has a gate, a source and a drain. A gate driver transistor disposed in the second region of the semiconductor substrate has a gate, a source and a drain. The gate driver transistor is electrically connected to the gate of the power transistor and operable to turn the power transistor off or on responsive to an externally-generated control signal applied to the gate of the gate driver transistor. A first contact pad is electrically connected to the source of the power transistor, and a second contact pad is electrically connected to the drain of the power transistor. A third contact pad is electrically connected to the gate of the gate driver transistor for receiving the externally-generated control signal.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: May 22, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Vielemeyer, Walter Rieger, Martin Pölzl, Gerhard Nöbauer
  • Patent number: 9973183
    Abstract: A lateral semiconductor field-effect transistor (FET) device fabricated on a substrate includes a high-voltage main FET having interdigitated, elongated source and drain electrode fingers each of which is electrically connected to a respective interdigitated, elongated source and drain region disposed in the substrate. The FET device further includes first and second sense FETs each having a drain region in common with the high-voltage main FET. The sense FETS also include respective first and second elongated source electrode fingers each of which is electrically connected to respective first and second elongated source regions of the first and second sense FETs, respectively. The first and second elongated source electrode fingers are disposed length-wise adjacent to one of the elongated drain electrode fingers. The first elongated source finger has a first length, and the second elongated source finger has a second length, the second length being less than the first length.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: May 15, 2018
    Assignee: Power Integrations, Inc.
    Inventors: Lin Zhu, Kamal Raj Varadarajan, Yury Gaknoki
  • Patent number: 9952273
    Abstract: A device includes a compound semiconductor chip having a control electrode, a first load electrode and a second load electrode. A first lead is electrically coupled to the control electrode, a second lead is electrically coupled to the first load electrode, and a third lead is electrically coupled to the first load electrode. The third lead is configured to provide a sensing signal from the first load electrode, the sensing signal being based on a physical parameter of the compound semiconductor chip. The control electrode is configured to receive a control signal based on the sensing signal. A fourth lead is electrically coupled to the second load electrode.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: April 24, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess
  • Patent number: 9941192
    Abstract: A semiconductor device having a repairable penetration electrode is provided. The semiconductor device having the repairable penetration electrode includes first and second signal transfer regions including main penetration electrodes penetrating a substrate, and a repair region including a spare penetration electrode penetrating the substrate. The first and second signal transfer regions are spaced apart from each other. The repair region is disposed between the first and second signal transfer regions. The first and second signal transfer regions share the repair region such that the spare penetration electrode of the repair region is substituted for a defective main penetration electrode of the first and second signal transfer regions.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: April 10, 2018
    Assignee: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS
    Inventors: Sanghyeon Baeg, Sungsoo Chung
  • Patent number: 9754854
    Abstract: A semiconductor package includes a power semiconductor chip having a control electrode, a first load electrode and a second load electrode. The package also includes a first terminal conductor electrically coupled to the control electrode, a second terminal conductor electrically coupled to the first load electrode and a third terminal conductor electrically coupled to the second load electrode. Further, the package includes a temperature sensor electrically coupled to at least two of the first, second and third terminal conductor.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: September 5, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Ralf Otremba, Marco Seibt
  • Patent number: 9584124
    Abstract: A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. The first channel and the second channel may receive and output calibration-related signals from and to each other through bonding, and may share calibration start signals. The calibration start signal may be respectively generated in the first channel and the second channel.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 28, 2017
    Assignee: SK hynix Inc.
    Inventors: Won Kyung Chung, Saeng Hwan Kim
  • Patent number: 9461647
    Abstract: A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. The first channel and the second channel may receive and output calibration-related signals from and to each other through bonding, and may share calibration start signals. The calibration start signal may be respectively generated in the first channel and the second channel.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: October 4, 2016
    Assignee: SK HYNIX INC.
    Inventors: Won Kyung Chung, Saeng Hwan Kim
  • Patent number: 9397626
    Abstract: A charge-sensitive amplifier is disclosed for use in amplifying signals from a particle detector. This includes a field effect transistor having a gate, source and drain, the gate being connectable, using a gate pad, to the particle detector, for the receipt of said signals. Also included is an amplifier having an input connected to the drain or source of the field effect transistor and an output connected through a feedback capacitor to the gate of the field effect transistor. The gate pad of the field effect transistor is made to be integral with the feedback capacitor so as to reduce the capacitance of the device.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: July 19, 2016
    Assignee: Oxford Instrument Nanotechnology Tools Limited
    Inventor: Tawfic Nashashibi
  • Patent number: 9390944
    Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: July 12, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Donald J. Desbiens, Gary D. Polhemus, Robert T. Carroll
  • Patent number: 9373384
    Abstract: An embodiment is directed to an integrated circuit device having programmable input capacitance. For example, a programmable register of a memory device may store a value representative of an adjustment to the input capacitance value of a control pin. An embodiment is directed to controlling the skew of a synchronous memory system by allowing programmability of the lighter loaded pins in order to increase their load to match the more heavily loaded pins. By matching lighter loaded pins to more heavily loaded pins, the system exhibits improved synchronization of propagation delays of the control and address pins. In addition, an embodiment provides the ability to vary the loading depending on how many ranks are on the device.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: June 21, 2016
    Assignee: Rambus Inc.
    Inventors: Ravindranath Kollipara, Lei Luo, Ian Shaeffer
  • Patent number: 9299683
    Abstract: An abutment structure comprises a power rail, a ground rail parallel to the power rail, first cells and second cells. An area is defined between the power and the ground rails. A portion of each first and second cell overlaps the power and the ground rails, and another portion thereof is within the area. The first cells are within the abutment structure with original patterns thereof. The second cells respectively has an original pattern and a base pattern being a flip pattern of the original pattern, and are within the area with alternate of the original and the base patterns. The first and the second cells are within the area alternately without overlapping. Alternatively, the first and the second cells may also be within different areas, and the second cells are within different areas respectively with the base pattern and a flip pattern of the base pattern thereof.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: March 29, 2016
    Assignee: GLOBAL UNICHIP CORPORATION
    Inventor: Jye-Yuan Lee
  • Patent number: 9093150
    Abstract: A multi-chip packaged integrated circuit part for mounting to a printed circuit board of a memory module. The multi-chip packaged integrated circuit part comprises an integrated circuit package including a slave memory controller (SMC) die; and pairs of a spacer under the slave memory controller die, and a flash memory die under the spacer. In each pair, the flash memory die may be larger than the spacer so that an opening is provided into a perimeter of the flash memory die to allow electrical connections to be made. A plurality of conductors may be used to electrically couple the slave memory controller die and the flash memory die to one or more pads of a pin-out of the integrated circuit package.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: July 28, 2015
    Assignee: Virident Systems, Inc.
    Inventors: Vijay Karamcheti, Kumar Ganapathy
  • Patent number: 9070700
    Abstract: An integrated circuit assembly is provided that includes an integrated circuit (IC) package substrate including a package ground rail that is divided into a plurality of segments that are electrically isolated from each other. An IC die is disposed on the IC package substrate, the IC die including a plurality of circuit blocks and an IC ground rail. The IC ground rail is divided into a plurality of segments, where each segment of the IC ground rail is coupled to another segment of the IC ground rail by one or more diodes. The plurality of circuit blocks have corresponding ground nodes electrically connected to corresponding segments of the IC ground rail. The segments of the IC ground rail are electrically coupled to corresponding segments of the package ground rail by corresponding first connections.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: June 30, 2015
    Assignee: Broadcom Corporation
    Inventors: Nikolaos Haralabidis, Ioannis Kokolakis
  • Patent number: 9062482
    Abstract: The invention relates to an electromagnetic doorlock with shock detection and power saving device comprises an electromagnet assembly and a corresponding attraction assembly. The electromagnet assembly is connected to a shock detection module and the attraction assembly has a pressing unit to press the shock detection module. When the door is opened, the electromagnet assembly does not supply power; when the door is closed, the electromagnet assembly with electromagnetic attraction attracts the attraction assembly and the pressing unit presses the shock detection module. That is, the electromagnetic doorlock usually stays in a low-energy attraction state; however, when a shock detection module is triggered, the electromagnetic doorlock returns to normal lock state for achieving power saving effect and control of the external force detection.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: June 23, 2015
    Inventor: Li-Shih Liao
  • Publication number: 20150137866
    Abstract: Apparatuses and methods are described that include a plurality of drivers corresponding to a single via. A number of drivers can be selected to operate individually or together to drive a signal through a single via. Additional apparatus and methods are described.
    Type: Application
    Filed: September 15, 2014
    Publication date: May 21, 2015
    Inventor: Feng Lin
  • Publication number: 20150130534
    Abstract: Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.
    Type: Application
    Filed: January 16, 2015
    Publication date: May 14, 2015
    Inventors: Guido Droege, Niklas Linkewitsch, Andre Schaefer
  • Patent number: 9030253
    Abstract: Integrated circuit (IC) packages with multiple clock sources are disclosed. A disclosed IC package includes a first die having a first clock source and a first clock tree and a second die having a second clock source and a second clock tree. The first clock source and the second clock source may be coupled to the second clock tree and the first clock tree, respectively, through a plurality of interconnects to form a clock tree network on the IC package. The clock tree network may be operable to be driven by either the first clock source or the second clock source.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: May 12, 2015
    Assignee: Altera Corporation
    Inventor: Tony Ngai
  • Patent number: 9026977
    Abstract: A method includes electrically connecting a plurality of cells of a standard cell library to a power rail. A contact area is deposited to connect a first active area and a second active area of a cell of a plurality cells. The first area and the second area are located on opposite sides of the rail and electrically connected to different drains. The contact area is electrically connected to the power rail using a via. The contact area is masked to remove a portion of the contact area to electrically separate the first active are from the second active area.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: May 5, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Marc Tarabbia, Norman Chen, Jian Liu, Nader Magdy Hindawy, Tuhin Guha Neogi, Mahbub Rashed, Anurag Mittal
  • Patent number: 9013235
    Abstract: Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods are disclosed. The present disclosure provides a 3D integrated circuit (IC) (3DIC) that has a flop spread across at least two tiers of the 3DIC. The flop is split across tiers with transistor partitioning in such a way that keeps all the clock related devices at the same tier, thus potentially giving better setup, hold and clock-to-q margin. In particular, a first tier of the 3DIC has the master latch, slave latch, and clock circuit. A second tier has the input circuit and the output circuit.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: April 21, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Pratyush Kamal, Yang Du
  • Patent number: 9000823
    Abstract: An integrated circuit includes a clock source tier and at least two clock tree tiers disposed in a vertical stack with the clock source tier. The clock source tier includes a clock circuit, and each of the at least two clock tree tiers includes a clock tree circuit. The clock circuit is disposed in the clock source tier is coupled to the clock tree circuits disposed in the at least two clock tree tiers by at least one inter-layer via.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Mu-Shan Lin
  • Publication number: 20150095871
    Abstract: A circuit design support method includes obtaining layout data that indicates positions of a plurality of clock receivers disposed in a circuit and positions of first clock wires disposed in the circuit; and calculating, by a computer, a value corresponding to lengths of wires respectively connecting the clock receivers to second clock wires on the basis of the obtained layout data, the value being calculated for each of a plurality of combinations of a count of the second clock wires and positions of the second clock wires, the second clock wires being disposed in a wiring layer of the circuit and being perpendicular to the first clock wires.
    Type: Application
    Filed: September 26, 2014
    Publication date: April 2, 2015
    Applicant: Fujitsu Optical Components Limited
    Inventor: Tomoyasu Kitaura
  • Publication number: 20150084689
    Abstract: A stacked package including: a semiconductor substrate, a circuit layer formed over the semiconductor substrate, a bump formed over the circuit layer, a spare bump formed correspondingly to the bump and over the circuit layer, and configured for replacing the bump with the spare bump, a through electrode configuring to pass through the semiconductor substrate on a same line as the bump and electrically coupled the bump or the spare bump in response to a selection signal, and a spare through electrode configured to pass through the semiconductor substrate on a same line as the spare bump and electrically coupled with the bump or the spare bump in response to a selection signal. When a bump has failed, a vertical input/output line of the semiconductor chips is established by a spare bump corresponding to the failed bump through the selective signal routing.
    Type: Application
    Filed: February 13, 2014
    Publication date: March 26, 2015
    Applicant: SK hynix Inc.
    Inventors: Sang Eun LEE, Chang Il KIM
  • Patent number: 8981842
    Abstract: Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a buffer chain coupling a first cell of the integrated circuit to a second cell of the integrated circuit. An electrical pathway coupling a first inverter of the buffer chain with a second inverter of the buffer chain extends through a first set of metal layers and is routed to form a pulse-like shape having an apex at a top layer of the first set.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Lin Chuang, Chien-Hui Chen, Wei-Pin Changchien, Chin-Her Chien, Nan-Hsin Tseng
  • Patent number: 8963622
    Abstract: High voltage rated isolation capacitors of inductors are formed on a face of a primary integrated circuit die. The isolation capacitors or inductors AC couple the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitors or inductors DC isolate the primary integrated circuit from the second integrated circuit die. Isolated power transfer from the first voltage domain to the second voltage domain is provided through the high voltage rated isolation capacitors or inductors with an AC oscillator or PWM generator. The AC oscillator voltage amplitude may be increased for an increase in power through the high voltage rated isolation capacitors or inductors.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: February 24, 2015
    Assignee: Microchip Technology Incorporated
    Inventors: Thomas Youbok Lee, Rudy Jaramillo, Patrick Kelly Richards, Lee Furey
  • Publication number: 20150028940
    Abstract: An integrated circuit has a semiconductor layer, at least one metal layer, a plurality of functional circuit blocks formed on the semiconductor layer, and a power mesh formed on the at least one metal layer. The power mesh has a specific area corresponding to a specific functional circuit block of the functional circuit blocks. The specific area at least has a first power trunk of a first power source and a second power trunk of a second power source distributed therein.
    Type: Application
    Filed: July 7, 2014
    Publication date: January 29, 2015
    Inventors: You-Ming Tsao, Kin Lam Tong, Chun-Fang Peng
  • Publication number: 20150022262
    Abstract: Embodiments disclosed in the detailed description include a complete system-on-chip (SOC) solution using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) integration technology. The present disclosure includes example of the ability to customize layers within a monolithic 3DIC and the accompanying short interconnections possible between tiers through monolithic intertier vias (MIV) to create a system on a chip. In particular, different tiers of the 3DIC are constructed to support different functionality and comply with differing design criteria. Thus, the 3DIC can have an analog layer, layers with higher voltage threshold, layers with lower leakage current, layers of different material to implement components that need different base materials and the like. Unlike the stacked dies, the upper layers may be the same size as the lower layers because no external wiring connections are required.
    Type: Application
    Filed: August 29, 2013
    Publication date: January 22, 2015
    Applicant: QUALCOMM Incorporated
    Inventor: Yang Du
  • Patent number: 8933747
    Abstract: A semiconductor chip package eliminates and minimizes a power noise generated from a voltage generation circuit in the semiconductor chip package includes an integrated circuit chip with a voltage generation circuit that receives an external voltage to generate a supply voltage to be used in an internal circuit and a connection terminal connected to an output node of the voltage generation circuit, and a mounting substrate including a noise eliminator electrically connected to the connection terminal to reduce a power noise of the supply voltage and a mounting substrate to mount the integrated circuit chip to package the integrated circuit chip as the semiconductor chip package.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: January 13, 2015
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: SunWon Kang, Chiwook Kim, Hyun jeong Woo, Sangjoon Hwang
  • Patent number: 8933748
    Abstract: An active pen IC includes a plurality of pads coupled to receive a plurality of receive (RX) signals induced from a mobile device, the received RX signals constituting an original group of RX signals. The active pen IC also includes a permuting unit configured to permute the pads such that the received RX signals corresponding to the permuted pads constitute a generated group of RX signals.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: January 13, 2015
    Assignee: Himax Technologies Limited
    Inventors: Guan-Ying Huang, Yaw-Guang Chang
  • Publication number: 20150008979
    Abstract: An active pen IC includes a plurality of pads coupled to receive a plurality of receive (RX) signals induced from a mobile device, the received RX signals constituting an original group of RX signals. The active pen IC also includes a permuting unit configured to permute the pads such that the received RX signals corresponding to the permuted pads constitute a generated group of RX signals.
    Type: Application
    Filed: July 5, 2013
    Publication date: January 8, 2015
    Inventors: Guan-Ying Huang, YAW-GUANG CHANG
  • Publication number: 20150008954
    Abstract: An apparatus for a monolithic integrated circuit die is disclosed. In this apparatus, the monolithic integrated circuit die has a plurality of modular die regions. The modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions. Each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines.
    Type: Application
    Filed: July 3, 2013
    Publication date: January 8, 2015
    Inventor: Rafael C. Camarota
  • Patent number: 8928399
    Abstract: According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for transmitting at least first and second address signals, these chips are stacked to be electrically connected via the first and second vias. The first selection circuit is provided in each chip, includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of operating the first and second address signals to the subsequent chip.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masaru Koyanagi
  • Patent number: 8922053
    Abstract: A semiconductor chip includes: a data output buffer that outputs a data signal; a first power-supply pad that supplies a first power-supply potential to the data output buffer; a power-supply wiring that is connected to the first power-supply pad; a strobe output buffer that outputs a strobe signal; and a second power-supply pad that supplies a second power-supply potential to the strobe output buffer. The power-supply wiring and the second power-supply pad are electrically independent of each other. Therefore, the power-supply noise associated with the switching of the data output buffer does not spread to the strobe output buffer. Thus, it is possible to improve the quality of the strobe signal.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: December 30, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Hiromasa Takeda, Hiroki Fujisawa
  • Patent number: 8907720
    Abstract: A capacitive switch includes: a first conductive cantilever, a second conductive cantilever, a substrate, a coplanar waveguide arranged on the substrate, the coplanar waveguide includes a first conductor configured to transmit an electrical signal, a second conductor and a third conductor are arranged as ground wires on two sides of the first conductor; an insulation medium layer is arranged on the first conductor, a conducting layer is arranged on the insulation medium layer; the first conductive cantilever is connected to the second conductor by using a first fixed end, the second conductive cantilever is connected to the third conductor by using a second fixed end; when a direct-current signal is transmitted on the capacitive switch, a first free end of the first conductive cantilever and a second free end of the second conductive cantilever contact the conducting layer.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: December 9, 2014
    Assignee: Huawei Device Co., Ltd.
    Inventors: Xiong Yang, Bocheng Cao, Lei Wang
  • Patent number: 8901956
    Abstract: An IC with configuration context switchers is provided. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: December 2, 2014
    Assignee: Tabula, Inc.
    Inventors: Trevis Chandler, Jason Redgrave, Martin Voogel
  • Patent number: 8890607
    Abstract: A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: IPEnval Consultant Inc.
    Inventors: Chao-Yuan Huang, Yueh-Feng Ho, Ming-Sheng Yang, Hwi-Huang Chen
  • Patent number: 8890570
    Abstract: A switch block circuit in a field programmable gate array is provided. The switch block circuit includes a configuration memory unit including first group memories and second group memories and a switching unit including first group switching transistors and second group switching transistors. The switch block circuit further includes a selection unit for correspondingly connecting the second group memories with the second group switching transistors depending on an operation mode. The switch block is efficiently reconfigurable depending on the intended use, and configuration memories unused in a specific operation mode may be applied to other purposes.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 18, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Han Jin Cho, Young Hwan Bae
  • Patent number: 8890600
    Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of IO pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the IO pads to each other.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: November 18, 2014
    Assignee: Cypress Semicondductor Corporation
    Inventors: Timothy J. Williams, Harold Kutz, David G. Wright, Eashwar Thiagarajan, Warren S. Snyder, Mark E. Hastings
  • Publication number: 20140320203
    Abstract: A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x?1 switch circuits to connect x?1 data circuits to through silicon vias 1 to x?1 in the group of n adjacent through silicon vias, activating n-x switch circuits to connect n-x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.
    Type: Application
    Filed: July 8, 2014
    Publication date: October 30, 2014
    Inventors: Kayoko Shibata, Hitoshi Miwa, Yoshihiko Inoue
  • Publication number: 20140312878
    Abstract: Indexing a plurality of die obtainable from a material wafer comprising a plurality of stacked material layers. Each die is obtained in a respective position of the wafer. A manufacturing stage comprises at least two steps for treating a respective superficial portion of the material wafer that corresponds to a subset of said plurality of dies using the at least one lithographic mask through the exposition to the proper radiation in temporal succession. The method may include providing a die index on each die which is indicative of the position of the respective die by forming an external index indicative of the position of the superficial portion of the material wafer corresponding to the subset of the plurality of dies including said die and may comprise a plurality of electronic components electrically coupled to each other by means of a respective common control line.
    Type: Application
    Filed: July 2, 2014
    Publication date: October 23, 2014
    Inventors: Daniele Alfredo BRAMBILLA, Fausto REDIGOLO
  • Patent number: 8866543
    Abstract: Provided is an integrated circuit (IC) having a stacked structure. The IC includes: a first IC having a power input terminal to which a power supply voltage is applied; and a second IC having a power input terminal connected to a ground terminal of the first IC, having a central node formed as the power input terminal of the second IC and the ground terminal of the first IC are connected to each other and to which a voltage is applied, and having a ground terminal connected to a ground source, wherein the power supply voltage is divided into first and second voltages that are respectively applied to the first and second ICs.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: October 21, 2014
    Assignee: Soongsil University Research Consortium Techno-Park
    Inventors: Chang Kun Park, Ho Yong Hwang
  • Patent number: 8866537
    Abstract: An input apparatus includes a touch plate, a film sensor, an electrode portion, and a wire portion. The touch plate has a front side touched by the finger in the finger manipulation. The film sensor is bonded to a rear side of the touch plate. The electrode portion and wire portion are provided on the film sensor and connected to each other. The touch plate is composed of a plurality of different members including at least a first member and a second member. The plurality of different members have respective dielectric constants and being layered and laminated, respectively, in a plate thickness direction of the touch plate. The plurality of different members have different dimension ratios in the plate thickness direction to provide different dielectric constants depending on the electrode portion and the wire portion and provide a uniform plate thickness over a whole of the touch plate.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: October 21, 2014
    Assignee: Denso Corporation
    Inventor: Shinsuke Hisatsugu