Abstract: A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A semiconductor apparatus includes a plurality of pump control units respectively located in a plurality of chips, connected in series through a first TSV, and configured to sequentially delay a period signal, transmit delayed period signals and generate pump control signals based on the period signal or the delayed period signals; and a plurality of voltage pump units respectively located in the plurality of chips, and configured to generate a pumping voltage in response to the pump control signals generated from the plurality of pump control units.

Abstract: A semiconductor device and a method for driving the same rapidly detect failure of a through-semiconductor-chip via and effectively repairing the failure using a latching unit assigned to each through-semiconductor-chip via. The semiconductor device includes a plurality of semiconductor chips that are stacked, and a plurality of through-semiconductor-chip vias to commonly transfer a signal to the plurality of semiconductor chips, wherein each of the semiconductor chips includes a multiplicity of latching units assigned to the through-semiconductor-chip vias and the multiplicity of latching units of each of the semiconductor chips constructs a boundary scan path including the plurality of through-semiconductor-chip vias to sequentially transfer test data.

Abstract: Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection.

Abstract: Various embodiments of a three-dimensional, stacked semiconductor integrated circuit are disclosed. In one exemplary embodiment, the circuit may include a master slice, a plurality of slave slices, and a plurality of through-silicon vias for connecting the master slice to the plurality of slave slices. At least one of the plurality of through-silicon vias may be configured to transmit an operation control signal from the master slice to the plurality of slave slices. The at least one of the plurality of through-silicon vias is configured to be shared by the plurality of slave slices.

Abstract: Examples of the present invention include a metamaterial comprising a plurality of resonators disposed on a substrate, the substrate comprising a dielectric support layer and a relatively thin semiconductor layer, having a Schottky junction between at least one conducting resonator and the semiconductor layer. The properties of the resonator may be adjusted by modifying the physical extent of a depletion region associated with the Schottky junction.

Abstract: An abutment structure comprises a power rail, a ground rail parallel to the power rail, first cells and second cells. An area is defined between the power and the ground rails. A portion of each first and second cell overlaps the power and the ground rails, and another portion thereof is within the area. The first cells are within the abutment structure with original patterns thereof. The second cells respectively has an original pattern and a base pattern being a flip pattern of the original pattern, and are within the area with alternate of the original and the base patterns. The first and the second cells are within the area alternately without overlapping. Alternatively, the first and the second cells may also be within different areas, and the second cells are within different areas respectively with the base pattern and a flip pattern of the base pattern thereof.

Abstract: An electronic device includes an electronic component and a protection circuit configured to protect the component from overvoltages. A control circuit is configured to inhibit a part of the protection circuit in the presence of a test voltage across terminals of the component.

Abstract: According to one embodiment, a three-dimensional semiconductor integrated circuit includes first, second and third chips which are stacked, and a common conductor which connects the first, second and third chips from one another. The first chip includes a first multi-leveling circuit, the second chip includes a second multi-leveling circuit, and the third chip includes a decoding circuit. The first multi-leveling circuit includes a first inverter to which binary first data is input and which outputs one of first and second potentials and a first capacitor which is connected between an output terminal of the first inverter and the common conductor. The second multi-leveling circuit includes a second inverter to which binary second data is input and which outputs one of third and fourth potentials and a second capacitor which is connected between an output terminal of the second inverter and the common conductor.

Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.

Abstract: The invention relates notably to large-sized image sensors or image sensors with a large number of rows. Each column of pixels is organized in P superposed blocks. A row decoder organized as P identical decoders selects one row out of M in each of the P blocks. Each block is linked to one respective column conductor out of P column conductors. P read circuits CL1 to CL4 are placed at the foot of each column of pixels and each is connected to a respective column conductor. The signals from the P rows selected by the decoder can be extracted simultaneously or else they can be selected by a specific decoder which selects one read circuit out of the P read circuits of each column. The matrix can be produced by photolithography, by abutting identical matrix portions, for example P different portions corresponding to P identical regions ZB1 to ZB4.

Abstract: An analog-digital converter includes n comparators arranged in a first direction with a predetermined cell pitch and corresponding respectively to n input voltages, each comparator comparing a voltage value of a reference signal whose voltage value increases or decreases over time with an input voltage corresponding to the comparator. Each of the n comparators includes differential transistors to which the reference signal and the input voltage are given respectively. A differential transistor is formed by p unit transistors connected in series whose gates are given the reference signal, and another differential transistor is formed by p unit transistors connected in series whose gates are given the input voltage.

Abstract: A semiconductor integrated circuit device of the invention can reduce a manufacturing cost and achieve size reduction without degrading performances. The semiconductor integrated circuit device includes an internal circuit and at least one input/output circuit. Each input/output circuit is adapted to feed an input signal from outside to the internal circuit and to output an output signal from the internal circuit to the outside. The semiconductor integrated circuit device also includes at least one first power source terminal. Each first power source terminal is associated with each input/output circuit for supplying a drive voltage to the internal circuit. The semiconductor integrated circuit device also includes at lease one second power source terminal. Each second power source terminal is associated with each input/output circuit for supplying a drive voltage to the associated input/output circuit. The semiconductor integrated circuit device also includes at least one common ground terminal.

Abstract: A semiconductor device includes a first pad, a second pad and a third pad. The first pad and the third pad are electrically connected to each other. The first pad and the second pad are used for bonding. The second pad and the third pad are used for probing. According to this structure, Small size semiconductor device having high reliability even after a probing test can be provided.

Abstract: A single chip wireless sensor (1) comprises a microcontroller (2) connected to a transmit/receive interface (3), which is coupled to a wireless antenna (4) by an L-C matching circuit. The sensor (1) senses gas or humidity and temperature. The device (1) is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process. A Low-K material (57) with an organic polymer component is spun onto the wafer to form a top layer incorporating also sensing electrodes (60). This material is cured at 300° C., which is much lower than CVD temperatures. The polyimide when cured becomes thermoset, and the lower mass-to-volume ratio resulting in K, its dielectric constant, reducing to 2.9. The thermoset dielectric, while not regarded as porous in the conventional sense, has sufficient free space volume to admit enough gas or humidity for sensing.

Abstract: An output circuit of a semiconductor apparatus having two different types of decoupling capacitors is presented. The output circuit includes a first pad, a second pad, a main output unit and a decoupling capacitor region. The first and second pads are configured to respectively provide a power supply voltage and a ground voltage. The main output unit is coupled to the first and second pads. One end of the decoupling capacitor region is coupled to the first pad and the other end is coupled to the second pad. The decoupling capacitor region includes a first decoupling capacitor region spaced apart from a portion of the main output unit by a first distance, and a second decoupling capacitor region spaced apart from the main output unit by a second distance which is greater than the first distance.

Abstract: A data line driver includes a first driver cell configured to drive a first data line connected to a first output pad. The first driver cell includes a first data register configured to latch first image data in response to a first latch clock signal, a first level shifter connected to the first data register, a first digital-analog converter (DAC) connected to the first level shifter, and a first amplifier connected between the first DAC and the first output pad. The first data register and the first amplifier are arranged in a first direction. The first level shifter and the first DAC are arranged adjacent to each other in a second direction and are arranged between the first data register and the first amplifier, and the second direction is perpendicular to the first direction.

Abstract: An integrated circuit is disclosed having a semiconductor component comprising a first p-type region and a first n-type region adjoining the first p-type region, which together form a first pn junction having a breakdown voltage. A further n-type region adjoining the first p-type region or a further p-type region adjoining the first n-type region is provided, the first p-type or n-type region and the further n-type or p-type region adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down.

Abstract: A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse.

Abstract: A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal.

Abstract: In one embodiment of an e-fuse programming/re-programming circuit, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

Abstract: A repair circuit of a semiconductor apparatus includes a transmission control unit configured to generate first through nth (n is an integer equal to or greater than 2) control signals in response to a repair information signal, and enable all mth through nth control signals when the repair information signal indicating an mth (m is an integer equal to or greater than 1 and equal to or less than n) TSV is inputted; transmission units configured to allocate transmission paths for first through nth signals to first through nth TSVs and a repair TSV in response to the first through nth control signals; and receiving units configured to receive the signals transmitted from the first through nth TSVs and the repair TSV in response to the first through nth control signals.

Abstract: The present invention provides a semiconductor device in which a power line is not affected by noise due to a voltage drop caused by instantaneous high-current consumption in the buffer portion and that has no possibility that a logic portion malfunctions. In a case where the same potential is supplied to a logic portion and a buffer portion, by a method in which separate FPC terminals are used for the logic portion and the buffer portion, or by a method in which the FPC terminal is shared but a power line is branched for the logic portion and the buffer portion at a point close to the FPC terminal, a problem that the logic portion is affected by noise generated by a voltage drop of the power line due to instantaneous high-current consumption in the buffer portion can be prevented.

Abstract: Display irregularities in light emitting devices, which develop due to dispersions per pixel in the threshold value of TFTs for supplying electric current to light emitting elements, are obstacles to increasing the image quality of the light emitting devices. An electric potential in which the threshold voltage of a TFT (105) is either added to or subtracted from the electric potential of a reset signal line (110) is stored in capacitor means (108). A voltage, in which the corresponding threshold voltage is added to an image signal, is applied to a gate electrode of a TFT (106). TFTs within a pixel are disposed adjacently, and dispersion in the characteristics of the TFTs does not easily develop. The threshold value of the TFT (105) is thus cancelled, even if the threshold values of the TFTs (106) differ per pixel, and a predetermined drain current can be supplied to an EL element (109).

Abstract: An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (TSVs') in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die.

Abstract: A semiconductor apparatus having a plurality of semiconductor chips is configured in such a manner that the plurality of semiconductor chips share one or more source voltages generated in one of the plurality of semiconductor chips.

Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.

Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

Abstract: The present invention relates to a Network on chip comprising a torus matrix of processing elements formed by a juxtaposition of bricks in rows and columns, each brick comprising a longitudinal extra-connection bus segment connecting two terminals situated on opposite transverse edges of the brick on a first axis; two longitudinal intra-connection bus segments connecting circuits of the brick to respective terminals situated on the opposite transverse edges on a second axis symmetrical to the first axis with respect to the center of the brick; a transverse extra-connection bus segment connecting two terminals situated on opposite longitudinal edges of the brick on a third axis; and two transverse intra-connection bus segments connecting circuits of the brick to respective terminals situated on the opposite longitudinal edges on a fourth axis symmetrical to the third axis with respect to the center of the brick.

Abstract: A semiconductor device, a semiconductor element, and a substrate are provided, which allow the semiconductor element to be provided with a reduced size when combined. The semiconductor device has a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element includes a grayscale voltage generating unit for generating a plurality of grayscale voltages by dividing a reference voltage, a plurality of electrodes for the reference voltage formed in the neighborhood of the grayscale voltage generating unit; and an internal wiring for connecting the grayscale voltage generating unit and the reference voltage electrodes. The substrate includes a wiring pattern for the reference voltage for connecting the external input terminal and the reference voltage electrodes.

Abstract: To include a first semiconductor chip including driver circuits, a second semiconductor chip including receiver circuits, and through silicon vias provided in the second semiconductor chip. The first semiconductor chip includes an output switching circuit that exclusively connects an output terminal of an i-th driver circuit (where i is an integer among 1 to n) to one through silicon via among an i-th through silicon via to an (i+m)-th through silicon via. The second semiconductor chip includes an input switching circuit that exclusively connects an input terminal of an i-th receiver circuit (where i is an integer among 1 to n) to one through silicon via among the i-th through silicon via to the (i+m)-th through silicon via. With this configuration, because a difference in wiring lengths does not occur between signal paths before and after replacement of through silicon vias, the signal quality can be enhanced.

Abstract: A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.

Abstract: Some of the embodiments of the present invention provide an integrated circuit device including a clock distribution network, the clock distribution network comprising an inner band, an outer band, and a clock distribution tree including a plurality of stages, each stage including a plurality of signal drivers, wherein all signal drivers of at least one stage of the clock distribution tree are placed in an area between the inner band and the outer band. Other embodiments are also described and claimed.

Abstract: A circuit arrangement is provided.

Abstract: In a stacked semiconductor device in which a plurality of through silicon vias used for data transfer are shared among a plurality of semiconductor chips, a first semiconductor chip included in the semiconductor chips holds through silicon via switching information for specifying a through silicon via among the through silicon vias to be used for data transfer, and transfers the through silicon via switching information to a second semiconductor chip included in the semiconductor chips. According to the present invention, because the through silicon via switching information is transferred from the first semiconductor chip to the second semiconductor chip, a circuit for storing the through silicon via switching information in a nonvolatile manner is not required in the second semiconductor chip. With this arrangement, a chip area of the second semiconductor chip can be reduced.

Abstract: A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply. Lines of the first and second conductive layers are substantially parallel to each other in a diode region of the diode. Further, for one aspect, a tap for the diode to be coupled to a supply is wider than a minimum width.

Abstract: An efficient logic chip operating power supply having digital circuits in a multi-chip package is provided. A multi-chip package semiconductor device fabricated in common with a driver chip having analog circuits and a logic chip having digital circuits, a logic chip power supply circuit is provided in which a driver chip creates a logic chip power supply dedicated for the logic chip. The logic chip has internal logic circuitry operating by receiving a power supply from the logic chip power supply circuit via power input terminals.

Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal ?(0) to ?(2i?1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal ?(0) to j(2i?1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal ?(0) to ?(2i?1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.

Abstract: The invention relates to an integrated circuit comprising a succession of N identical elementary circuits, juxtaposed in the order of their rank j varying from 1 to N, N being at least equal to 50, and all having to receive two reference potentials Vref and V0 supplied by two conductors. The upstream input of the second conductor is situated geographically on the side of the rank 1 of the succession of juxtaposed circuits, and the upstream input of the first conductor is situated geographically on the side of the rank N of the succession of juxtaposed circuits. This reduces the error in the potential difference applied to the elementary circuits all along the succession, an error that originates from the non-zero resistance of the conductors. Application to analog-digital converters or digital-analog converters with high resolution (10 bits or more).

Abstract: Disclosed is a CCD device in which a charge transfer register of a CCD structure is connected to a charge detector via an output gate and has a reset gate between the charge detector and a reset drain, and an output gate pulse opposite in phase from a reset pulse applied to the reset gate is applied to the output gate. A dummy charge detector and an amplitude adjusting circuit are provided. On the basis of detection of the potential of a diffusion layer in the dummy charge detector, the amplitude adjusting circuit controls the amplitude of the output gate pulse applied to the output gate.

Abstract: A semiconductor device and a method for driving the same rapidly detect failure of a through-semiconductor-chip via and effectively repairing the failure using a latching unit assigned to each through-semiconductor-chip via. The semiconductor device includes a plurality of semiconductor chips that are stacked, and a plurality of through-semiconductor-chip vias to commonly transfer a signal to the plurality of semiconductor chips, wherein each of the semiconductor chips includes a multiplicity of latching units assigned to the through-semiconductor-chip vias and the multiplicity of latching units of each of the semiconductor chips constructs a boundary scan path including the plurality of through-semiconductor-chip vias to sequentially transfer test data.

Abstract: A semiconductor integrated circuit device includes: terminals 11a and 11m; first to (2n+1)-th resistive elements (n is an integer of at least 1) (resistive element group 12) connected in series between the terminals 11a and 11m; a selection circuit 14 selecting, assuming that a terminal 11a connected to one end of the first resistive element is a 0th node, a terminal 11m connected to the other end of the (2n+1)-th resistive element is a (2n+1)-th node, and a connection point of the other end of an i-th resistive element (i is an integer from 1 to 2n) and one end of an (i+1)-th resistive element is an i-th node, any one of the 0th to (2n+1)-th nodes and outputting a voltage applied to the selected node; a switch group 15a capable of shorting any 2k-th node (k is an integer from 0 to n); and a switch group 15b capable of shorting any (2k+1)-th node. The 2k-th and (2k+1)-th nodes are shorted, and subsequently, a predetermined voltage is temporarily applied between the terminals 11a and 11m.

Abstract: A transient voltage suppressing (TVS) circuit with uni-directional blocking and symmetric bi-directional blocking capabilities integrated with an electromagnetic interference (EMI) filter supported on a semiconductor substrate of a first conductivity type. The TVS circuit integrated with the EMI filter further includes a ground terminal disposed on the surface for the symmetric bi-directional blocking structure and at the bottom of the semiconductor substrate for the uni-directional blocking structure and an input and an output terminal disposed on a top surface with at least a Zener diode and a plurality of capacitors disposed in the semiconductor substrate to couple the ground terminal to the input and output terminals with a direct capacitive coupling without an intermediate floating body region.

Abstract: A central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews.

Abstract: To include a plurality of circuit blocks each including a plurality of nonvolatile memory elements arranged in the X direction, a plurality of comparing circuits that are respectively allocated to the nonvolatile memory elements, and a determining circuit that is commonly allocated to the comparing circuits. The nonvolatile memory elements included in a predetermined circuit block among the circuit blocks are arranged in a first area. The comparing circuits and the determining circuit included in the predetermined circuit block are arranged side by side in the X direction in a second area that is located in the Y direction with respect to the first area. With this arrangement, because the circuit block becomes a shaped block, even when a plurality of circuit blocks are repeatedly arranged, it is possible to realize a further reduction of the chip area.

Abstract: A system, including: a first current mirror having a first current, formed of multiple devices disposed on a substrate, where, when a stress is present, a behavior of a device of the multiple devices forming the first current mirror depends on a direction in which the device of the multiple devices forming the first current mirror is disposed on the substrate; a second current mirror having a second current, formed of multiple devices disposed on the substrate, where, when the stress is present, a behavior of a device of the multiple devices forming the second current mirror depends on a direction in which the device of the multiple devices forming the second current mirror is disposed on the substrate; and a device for measuring a ratio of a difference between the first current and the second current to a sum of the first current and the second current.

Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.

Abstract: A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.

Abstract: A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply. Lines of the first and second conductive layers are substantially parallel to each other in a diode region of the diode. Further, for one aspect, a tap for the diode to be coupled to a supply is wider than a minimum width.

Abstract: A field transistor is divided into a number of cells (6) and includes a separate first gate line (20) connected to first transistor cells (8) and a separate second gate line (22) connected to second transistor cells (10). A drive circuit is used to drive all the cells (6) in a normal, saturated operations state but to drive only the second cells (10) in a linear operations state to reduce the number of cells used in the linear operations state.