With Latching Type Element (e.g., Flip-flop, Etc.) Patents (Class 327/57)
  • Patent number: 10284214
    Abstract: The invention relates to a filter circuit (200) comprising at least a first filter line (210). The first filter line (210) has a first input circuit (10), a first integration circuit (20) and a first output circuit (30). The first input circuit (10) is configured in such a way that, as a function of the value of the input signal, it converts an input signal into at least two distinguishable, first first-stage output signals and relays the first-stage output signals to the first integration circuit (20, 240) during a prescribed period of time. The first integration circuit (20) is configured to integrate the first first-stage output signals of the first input circuit (10) over the prescribed period of time and to generate a first integration signal (25). The first output circuit (25) is configured to compare the first integration signal (25) to a first output reference value and to generate a first second-stage output signal (35). The invention also relates to an appertaining filtering method.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: May 7, 2019
    Assignee: FORSCHUNGSZENTRUM JÜLICH GmbH
    Inventor: Christian Grewing
  • Patent number: 10242720
    Abstract: A sense amplifier and method thereof are provided. The sense amplifier includes first and second transistors coupled to first and second bit lines, respectively. The first and second transistors are configured to connect the first and second bit lines to a differential amplifier during a first state (e.g., when a differential voltage is present on the first and second bit lines and prior to a sense signal transition) and to isolate the first and second bit lines from the differential amplifier during a second state (e.g., after the sense signal transition). The sense amplifier further includes a third transistor configured to deactivate the differential amplifier during the first state and configured to activate the differential amplifier during the second state.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: March 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Nan Chen, Ritu Chaba
  • Patent number: 9941872
    Abstract: An apparatus includes first and second input transistors receiving respective first and second input signals, and a feedback circuit coupled to the first and second input transistors. The first and second input transistors provide first and second nodes with first and second currents according to values of the first and second input signals, respectively, when the feedback circuit is turned on. The first and second input transistors produce a reset value on the nodes when the feedback circuit is turned off. A method includes resetting, using first and second input transistors, respectively, values of first and second nodes to a reset value, providing first and second currents to the nodes using the first and second input transistors according to values of first and second input signals, and determining the values of the nodes according to the values of the first and second input signals.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: April 10, 2018
    Assignee: Marvell International Ltd.
    Inventor: Sasan Cyrusian
  • Patent number: 9698763
    Abstract: Redundant inverters with multiple inverter stages enable lower operating voltages to be used. For example, the use of multiple inverter stages produces a strong “0” or a strong “1” output signal. The strong output signal facilitates self-oscillation of a ring oscillator at lower voltages.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: July 4, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Zhihong Luo, Benjamin Shui Chor Lau, Chun Huat Heng, Yong Lian
  • Patent number: 9576623
    Abstract: The present disclosure herein relates to a sense amplifier and a semiconductor memory device employing the same. The sense amplifier includes an inverter including a pull-up transistor and a pull-down transistor, and a switching unit configured to change a connection relationship between the pull-up transistor and the pull-down transistor according to whether an input terminal of the inverter is precharged or a signal applied to the input terminal is sensed.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 21, 2017
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Seongook Jung, Hanwool Jeong, Young Hwi Yang, Kyoman Kang
  • Patent number: 9514836
    Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: December 6, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Iwai, Hiroshi Nakamura
  • Patent number: 9443567
    Abstract: Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to the input sensing stage, for determining whether the input signal is a logic low or a logic high; and a power management circuit, coupled to the input sensing stage and the decision making circuit, which is operable to monitor a state of the decision making circuit and to disable the input sensing stage according to the monitored state. Described is an apparatus which comprises: a decision making circuit integrated with an input sensing stage, wherein the decision making circuit is operable to pre-charge its internal nodes during a phase of the clock signal; and a latching circuit to latch an output of the decision making circuit.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: September 13, 2016
    Assignee: Intel Corporation
    Inventors: Pankaj Vinayak Dudulwar, Chenchu Punnarao Bandi, Lip Khoon Teh, Tat Hin Tan
  • Patent number: 9337156
    Abstract: A method for manufacturing a digital circuit is described comprising forming two field effect transistors, connecting the field effect transistors such that an output signal of the digital circuit in response to a predetermined input signal has an undefined logic state when the threshold voltages of the field effect transistors are equal and setting the threshold voltages of at least one of the field effect transistors such that the output signal of the digital circuit in response to the predetermined input signal has a predetermined defined logic state.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: May 10, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kuenemund, Berndt Gammel
  • Patent number: 9106225
    Abstract: A semiconductor integrated circuit comprises a state holding circuit that inputs an output of one inverter to another inverter with each other; an input circuit that causes a state of the state holding circuit to transition based on a data signal; a first first-conductive transistor that is inserted between an input of the one inverter and an output of the another inverter and is controlled by the data signal; and a first second-conductive transistor that is connected in parallel with the first first-conductive transistor and is controlled by the data signal.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: August 11, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chen kong Teh, Hiroyuki Hara
  • Patent number: 9007119
    Abstract: A method of operating a system including a MEMS device of an integrated circuit die includes generating an indicator of a device parameter of the MEMS device in a first mode of operating the system using a monitor structure formed using a MEMS structural layer of the integrated circuit die. The method includes generating, using a CMOS device of the integrated circuit die, a signal indicative of the device parameter and based on the indicator. The device parameter may be a geometric dimension of the MEMS device. The method may include, in a second mode of operating the system, compensating for a difference between a value of the signal and a target value of the signal. The method may include re-generating the indicator after exposing the MEMS device to stress and generating a second signal indicating a change in the device parameter.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: April 14, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost, Emmanuel P. Quevy
  • Patent number: 8988959
    Abstract: A circuit and method for dynamically changing trip point voltage in a sensing inverter circuit. In one embodiment, the sensing inverter circuit includes: (1) a base inverter circuit couplable to logic-high and logic-low voltage sources at respective inputs thereof and configured to transition an output thereof from a previous logic-level voltage to a present logic-level voltage based on a logic value of an input voltage received by the base inverter circuit, and (2) a feedback circuit associated with the base inverter circuit and configured to employ the previous logic-level voltage to decouple one of the logic-high and logic-low voltage sources from one of the inputs and thereby shift a trip voltage of the base inverter circuit toward the input voltage.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: March 24, 2015
    Assignee: LSI Corporation
    Inventor: Rajiv Roy
  • Publication number: 20150061730
    Abstract: A latch, an operation method of the latch, and a comparator using the latch are disclosed. The latch includes first and second cross-coupled pairs and first and second transistor pairs. First terminals of the first and second current paths of the first cross-coupled pair are respectively coupled to first terminals of the first and second transistors of the first transistor pair. First terminals of the third and fourth current paths of the second cross-coupled pair are respectively coupled to first terminals of the third and fourth transistors of the second transistor pair. Control terminals of the third and fourth transistors are respectively coupled to the first and second current paths. Control terminals of the first and second transistors are respectively coupled to the third and fourth current paths.
    Type: Application
    Filed: December 5, 2013
    Publication date: March 5, 2015
    Applicant: Industrial Technology Research Institute
    Inventors: Chia-Ming Tsai, Bo-Jyun Kuo, Bo-Wei Chen
  • Patent number: 8930862
    Abstract: A system, method, and computer program product for converting a design from edge-triggered docking to two-phase non-overlapping clocking is disclosed. The method includes the steps of replacing an edge-triggered flip-flop circuit that is coupled to a combinational logic circuit with a pair of latches including a first latch circuit and a second latch circuit and determining a midpoint of the combinational logic circuit based on timing information. The second latch circuit is propagated to a midpoint of the combinational logic circuit and two-phase non-overlapping clock signals are provided to the pair of latches.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: January 6, 2015
    Assignee: NVIDIA Corporation
    Inventor: William J. Dally
  • Patent number: 8928357
    Abstract: A sense amplifier is provided. The sense amplifier comprises a first and second cross-coupled transistor pairs, a first and second current sources, a first digital input transistor, and a second digital input transistor. The first and second ends of the first cross-coupled transistor pair are coupled to an operating voltage, the first and second back gate ends of the first cross-coupled transistor pair are coupled to a first and second output ends respectively. The first and second back gate ends of the first cross-coupled transistor pair are coupled to a first and second output ends respectively, and the first and second ends of the first cross-coupled transistor pair are coupled to a first digital input end and second digital input end respectively.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: January 6, 2015
    Assignee: Nanya Technology Corporation
    Inventors: Adam Saleh El-Mansouri, Adrian Jay Drexler, Hofstetter Martin Ryan
  • Patent number: 8890576
    Abstract: An input/output sense amplifier includes: a data input unit configured to amplify data using a driving voltage and to output the amplified data, and a latch unit configured to latch and output an output signal of the data input unit to an output terminal.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: November 18, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jong Su Kim
  • Publication number: 20140152345
    Abstract: A latch circuit comprises true and complement data nodes. During a setup period of a latching operation, true node setup circuitry draws the true data node toward an input data signal in parallel with complement node setup circuitry drawing the complement node upward toward a high-voltage reference source (VDD) when the data signal is low or downward toward a low-voltage reference source (VSS) when the data signal is high. After the setup period, true and complement clock signals are used as control signals to turn the setup circuitry off and amplification circuitry on. The amplification circuitry, which comprises a pair of cross-coupled inverters coupled between VDD and VSS, is capable of resolving relatively small voltage differentials between the true and complement nodes by pulling the true node (i) upward toward VDD when the data signal is high and (ii) downward toward VSS when the data signal is low.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Applicant: LSI Corporation
    Inventors: Manish Trivedi, Manish Umedlal Patel
  • Patent number: 8742796
    Abstract: Embodiments of the present technology are directed toward circuits for gating pre-charging sense nodes within a flip-flop when an input data signal changes and a clock signal is in a given state. Embodiments of the present technology are further directed toward circuits for maintaining a state of the sense nodes.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: June 3, 2014
    Assignee: Nvidia Corporation
    Inventors: William Dally, Jonah Alben
  • Patent number: 8710868
    Abstract: A sense-amplifier monotizer includes an amplifier circuit and a keeper circuit. The amplifier circuit outputs a predetermined logic state while a clock signal is in a first phase, and samples a data signal and outputs at least one of the data signal and a complementary logic state of the data signal while the clock signal is in a second phase. A subsequent change of the data signal does not affect an output of the amplifier circuit once the data signal is sampled while the clock signal is in the second phase. The keeper circuit keeps a logic state of the sampled data signal once the data signal is sampled while the clock signal is in the second phase. The amplifier circuit may receive multiple data signals, and output a data signal selected by the select signal and/or a complementary value while the clock signal is in the second phase.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: April 29, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Samuel D. Naffziger, Visvesh S. Sathe, Srikanth Arekapudi
  • Patent number: 8705304
    Abstract: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Seong-Hoon Lee, Onegyun Na, Jongtae Kwak
  • Patent number: 8704553
    Abstract: Circuits that operate with power supplies of less than 1 Volt are presented. More particularly, circuits that operate with supply voltages near or lower than the threshold voltage of the transistors in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers, biasing circuits, integrators, continuous-time sigma delta modulators, track-and-bold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor to bipolar junction transistors may implement the techniques presented herein.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: April 22, 2014
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Kong-Pang Pun, Shouri Chatterjee, Peter R. Kinget
  • Patent number: 8692581
    Abstract: A constant switching current flip-flop includes a latch circuit that provides latch outputs of the flip-flop, whereby the latch outputs are reset to zero at the beginning of each clock cycle to eliminate pattern dependent switching currents. The latch circuit is reset responsive to control signals provided without significant delay.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: April 8, 2014
    Assignee: Agilent Technologies, Inc.
    Inventor: Minjae Lee
  • Patent number: 8680890
    Abstract: A sense amplifier circuit includes a first transistor and a second transistor of a first type, a first transistor and a second transistor of a second type, a first resistive device, and a second resistive device. A first end of the first resistive device is coupled to a first data line. A second end of the first resistive device is coupled to a drain of the first transistor of the second type and a gate of the second transistor of the first type. A first end of the second resistive device is coupled to a second data line. A second end of the second resistive device is coupled to a drain of the second transistor of the second type and a gate of the first transistor of the first type.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: March 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hyun-Sung Hong
  • Patent number: 8665003
    Abstract: A dead-time generating circuit includes a constant current circuit; a current generating circuit generating a capacitor-charge current; and a control circuit receiving a dead time control signal and a comparator signal. The control circuit generates a dead time generating signal based on the dead time control signal and the comparator signal, and a charge/discharge signal based on the dead time generating signal. Charging or discharging of a capacitor is controlled by the capacitor-charge current in accordance with the charge/discharge signal. A voltage of the capacitor is compared with a threshold voltage in order to generate a comparator signal when the voltage of the capacitor exceeds the threshold voltage. The control circuit generates the charge/discharge signal for a duration starting from a time when the delay time has elapsed from the rise or fall timing of the dead time control signal until the control circuit receives the comparator signal.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: March 4, 2014
    Assignee: Ricoh Company, Ltd.
    Inventors: Yasuo Ueda, Masashi Tokuda, Toshihiro Tsukagoshi
  • Patent number: 8659322
    Abstract: An integrated circuit includes a memory cell and a sense amplifier coupled to the memory cell via a first bit line and a second bit line. The sense amplifier includes first and second inverters cross-coupled to provide a latch. The first inverter is responsive to a first data signal provided by the memory cell over the first bit line. The second inverter is responsive to a second data signal as provided by the memory cell over the second bit line. A first negative bias temperature instability (NBTI) compensation transistor includes a source electrode coupled to receive a reference voltage, a drain electrode coupled to a source electrode of the first inverter, and a gate electrode coupled to first logic responsive to the first data signal.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: February 25, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Alexander B. Hoefler, James D. Burnett, Scott I. Remington
  • Patent number: 8653858
    Abstract: A signal operating circuit includes: a loading device, having a loading value, wherein the loading value is deviated from a predetermined loading value by a loading deviation value; an input stage coupled to the loading device, for converting an input signal into an output signal according to a controlling signal; a latching stage coupled to the loading device and the input stage for latching the output signal according to the controlling signal; and a controlling circuit coupled to the latching stage for adjusting an operating current flowing through the latching stage and an operating current flowing through the input stage to compensate the loading deviation value according to the loading deviation value of the loading device.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: February 18, 2014
    Assignee: Silicon Motion Inc.
    Inventor: Hui-Ju Chang
  • Patent number: 8624632
    Abstract: Sense amplifier-type latch circuits are provided which employ static bias currents for enhancing operating frequency. For example, a sense amplifier-type latch circuit includes a latch circuit that captures and stores data during an evaluation phase of the sense amplifier-type latch circuit, and outputs the stored data to differential output nodes. An input differential transistor pair has drains connected to the latch circuit and sources commonly connected to a coupled source node. A static bias current circuit is connected to the coupled source node to provide a static bias current which flows through the differential transistor pair and cross-coupled inverters of the latch during a precharge phase. A switch device, which is connected to the coupled source node, is turned off during the precharge phase and turned on during the evaluation phase by operation of a clock signal to increase current flow through the differential transistor pair.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventor: John F. Bulzacchelli
  • Patent number: 8559240
    Abstract: A CMOS latch-type sense amplifying circuit is disclosed. The circuit comprises a CMOS differential amplifier configured to amplify a voltage signal of an input line pair to generate a first amplified voltage signal pair, and provide the first amplified voltage signal pair to an output line pair, a first pre-charge voltage having a first voltage level being applied to the input line pair. The circuit further comprises a CMOS latch-type sense amplifier configured to amplify a voltage signal of the output line pair to generate a second amplified voltage signal pair, and provide the second amplified voltage signal pair to the output line pair. The circuit additionally comprises a first common node controlled by a first common enable signal and connected to both the CMOS differential amplifier and the CMOS latch-type sense amplifier, such that the first common enable signal controls both the CMOS differential amplifier and the CMOS latch-type sense amplifier.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Pyo Hong, Doo-Young Kim
  • Publication number: 20130257483
    Abstract: Sense amplifier-type latch circuits are provided which employ static bias currents for enhancing operating frequency. For example, a sense amplifier-type latch circuit includes a latch circuit that captures and stores data during an evaluation phase of the sense amplifier-type latch circuit, and outputs the stored data to differential output nodes. An input differential transistor pair has drains connected to the latch circuit and sources commonly connected to a coupled source node. A static bias current circuit is connected to the coupled source node to provide a static bias current which flows through the differential transistor pair and cross-coupled inverters of the latch during a precharge phase. A switch device, which is connected to the coupled source node, is turned off during the precharge phase and turned on during the evaluation phase by operation of a clock signal to increase current flow through the differential transistor pair.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 3, 2013
    Applicant: International Business Machines Corporation
    Inventor: John F. Bulzacchelli
  • Patent number: 8536898
    Abstract: A sense amplifier for use in a memory array having a plurality of memory cells is provided. The sense amplifier provides low power dissipation, rapid sensing and high yield sensing operation. The inputs to the sense amplifier are the differential bitlines of an SRAM column, which are coupled to the sense amplifier via the sources of two PMOS transistors. A CMOS latching element comprised of two NMOS transistors and the aforementioned PMOS transistors act to amplify any difference between the differential bitline voltages and resolve the output nodes of the sense amplifier to a full swing value. The latching element is gated with two additional PMOS transistors which act to block the latching operation until the sense amplifier is enabled. One or more equalization transistors ensure the latch remains in the metastable state until it is enabled. Once the latch has resolved it consumes no DC power, aside from leakage.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: September 17, 2013
    Inventors: David James Rennie, Manoj Sachdev
  • Patent number: 8487659
    Abstract: An adaptive delay device that provides a delay to a signal based on circuit conditions such as temperature, supply voltage values and/or fabrication processes. The adaptive delay device may respond to circuit conditions by charging a capacitive device to a threshold voltage. A comparator may incorporate the adaptive delay device to provide adaptive timing for the comparator functions thereby attaining improved noise performance and/or reduce power consumption.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: July 16, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Ronald Kapusta
  • Patent number: 8476933
    Abstract: A receiver circuit of a semiconductor apparatus includes a first sense amplifier, a level restriction unit, and a second sense amplifier. The first sense amplifier amplifies an input signal in response to a clock signal and generates a first signal with a voltage swing between a first level and a second level. The level restriction unit receives the first signal and generates a correction signal with a voltage swing between the first level and a third level. The second sense amplifier amplifies the correction signal in response to the clock signal and generates a second signal with the voltage swing between the first level and the second level.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: July 2, 2013
    Assignee: SK Hynix Inc.
    Inventor: Sang Yeon Byeon
  • Patent number: 8462572
    Abstract: An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: June 11, 2013
    Assignees: Stichting IMEC Nederland, Katholieke Universiteit Leuven
    Inventors: Vibhu Sharma, Stefan Cosemans, Wim Dehaene, Francky Catthoor, Maryam Ashouei, Jos Huisken
  • Patent number: 8432188
    Abstract: A latch circuit includes a first tri-state inverter configured to invert an input voltage in response to a pulse and to output the inverted voltage to a first node, a second tri-state inverter connected between the first node and a second node and to invert a voltage of the second node in response to an inverted pulse being an inverted version of the pulse, and a variable inversion unit connected between the first node and the second node. The variable inversion unit adjusts a logical threshold value according to a logical value corresponding to a voltage of the first node and inverts a voltage of the first node based upon the adjusted logical threshold value, the logical threshold value indicating a voltage for discriminating the logical value.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: April 30, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gunok Jung, Minsu Kim
  • Patent number: 8410820
    Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: April 2, 2013
    Assignee: Broadcom Corporation
    Inventors: Klaas Bult, Rudy Van de Plassche, Jan Mulder
  • Publication number: 20130057422
    Abstract: A comparator including a preamplifier amplifying a first signal and a second signal to produce a first amplified signal on a first output terminal and a second amplified signal on a second output terminal. The comparator also includes a capacitor, a clamp and a latch coupled in parallel to the first output terminal and the second output terminal of the preamplifier. A control circuit is coupled to the variable capacitor and the clamp and is configured to close the clamp during a first time period to cause the first amplified signal and the second amplified signal to bypass the capacitor and the latch, and open the clamp during a second time period following the first time period to cause the first amplified signal and the second amplified signal to be coupled to the capacitor and the latch. The capacitor filters the amplified signals, and the latch produces a digital output signal of the comparator based on the filtered signals.
    Type: Application
    Filed: September 30, 2011
    Publication date: March 7, 2013
    Applicant: APTINA IMAGING CORPORATION
    Inventors: Robert Johansson, Steffen Skaug, Timothy Bales
  • Patent number: 8355431
    Abstract: A Decision Feedback Equalizer (DFE) capable of preventing incremental increases of a jitter of a recovered clock and reduction of a voltage margin of decided data due to delay of feedback data. The DFE includes a combiner for combining received data with feedback data and outputting the combined data as equalization data, a decision circuit for deciding recovery data by receiving the equalization data, a feedback loop for supplying the recovery data to the combiner as feedback data and a clock recovery circuit for removing a delay data component from the equalization data through the feedback loop, recovering a clock with respect to the other equalization data except the delay data component and supplying the recovered clock for decision operation of the decision circuit.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: January 15, 2013
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Ki-Hyuk Lee
  • Patent number: 8339158
    Abstract: A dynamic high-speed comparative latch comprises a pre-amplifier unit for enlarging input differential signals, a regenerating latch unit for latching outputted differential signals from the pre-amplifier unit by using a positive feedback, specifically, converting the output of the pre-amplifier unit into a latched result at a first state of a clock cycle, and then retaining the latched result and simultaneously resetting relevant nodes at a second state opposite to the first state of the clock cycle, and a latch unit for outputting the effective outputted value of the regenerating latch unit when the regenerating latch unit being in a retaining state. The pre-amplifier unit is connected with the regenerating latch unit, and the regenerating latch unit is connected with the latch unit. The pre-amplifier unit comprises only one input clock signal. The present invention has a simple structure, and ensures the correctness of the output result of the latch.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: December 25, 2012
    Assignee: IPGoal Microelectronics (SiChuan) Co., Ltd.
    Inventors: Bin Li, Guosheng Wu
  • Patent number: 8330745
    Abstract: In one embodiment of the present invention, a source driver includes a shift register including latch stages each including a level shifter that level-shifts clock signals so that the signals are fed into a set-reset flip-flop as inverted set input signals. Outputs from the set-reset flip-flop are delayed by a hazard preventing circuit and then fed into a level shifter in the next latch stage as enable signals. A delay trimming circuit causes a NAND circuit to perform a NAND operation with respect to outputs obtained by a delay of the outputs by a delay circuit and outputs from the level shifter in the next latch stage, so that a sampling pulse is derived. This allows for provision of a pulse output circuit capable of further trimming delay in output pulses and of securing a sufficient interval between the output pulses.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: December 11, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Makoto Yokoyama, Yuhichiroh Murakami
  • Patent number: 8320211
    Abstract: A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias compensation unit. The sensing unit includes a sense amplifier, a latch circuit, a first precharged bit line, and a second precharged bit line. The equalizing unit is electrically connected to the first and the second precharged bit line for regulating a voltage of the first precharged bit line and a voltage of the second precharged bit line to the same electric potential. The bias compensation unit is electrically connected to the sense amplifier for compensating an input offset voltage of the current-sense amplifier.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: November 27, 2012
    Assignee: National Tsing Hua University
    Inventors: Meng-Fan Chang, Yu-Fan Lin, Shin-Jang Shen, Yu-Der Chih
  • Patent number: 8310853
    Abstract: A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: November 13, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sun Min, Kyu-Chan Lee, Chul-Woo Yi, Jong-Hyun Choi
  • Patent number: 8269527
    Abstract: A hysteresis comparator circuit that compares first and second input signals to output a hysteresis output signal includes a constant current source, a first comparator, a second comparator, and an output circuit. The constant current source includes a load resistor to generate a given constant current. The first comparator is controlled by the constant current supplied from the constant current source to compare the first and second input signals to output a first comparison result. The second comparator is controlled by the constant current supplied from the constant current source to compare the first and second input signals to output a second comparison result. The output circuit has a pair of inputs thereof connected to the first and second comparators, respectively, which inverts an output thereof in response to each of the first and second comparison results to generate the hysteresis output signal.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: September 18, 2012
    Assignee: Ricoh Company, Ltd.
    Inventor: Yasuo Ueda
  • Patent number: 8258819
    Abstract: Traditionally, latched comparators have suffered from performance problems related to exposure of the latch to load capacitances. Even attempts to isolate the latch from the load capacitances by way of resistors has resulted in performance problems (namely, voltage swing degradation). Here, however, a latched comparator is provided that employs inductors to generally provide isolation from load capacitances, which generally improves performance. Moreover, the latch has been modified to accommodate the inductors during a track period (namely, provision of grounding paths).
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: September 4, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Vaibhav Tripathi, Marco Corsi, Venkatesh Srinivasan
  • Patent number: 8249533
    Abstract: A rapidly adjustable local oscillation (LO) module for use in a radio transmitter or a radio receiver includes an oscillation generating module and a high frequency switching module. The oscillation generating module is operably coupled to generate a plurality of local oscillations. The high frequency switching module is operably coupled to, for a first one of a plurality of transmission paths, provide one of the plurality of local oscillations when a first transmission path selection indication is in a first state and provide another one of the plurality of local oscillations when the first transmission path selection indication is in a second state and, for a second one of the plurality of transmission paths, provide the one of the plurality of local oscillations when a second transmission path selection indication is in a first state and provide the another one of the plurality of local oscillations when the second transmission path selection indication is in a second state.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: August 21, 2012
    Assignee: Vixs Systems, Inc.
    Inventors: Bojan Subasic, Mathew A. Rybicki
  • Publication number: 20120194222
    Abstract: An integrated circuit includes a memory cell and a sense amplifier coupled to the memory cell via a first bit line and a second bit line. The sense amplifier includes first and second inverters cross-coupled to provide a latch. The first inverter is responsive to a first data signal provided by the memory cell over the first bit line. The second inverter is responsive to a second data signal as provided by the memory cell over the second bit line. A first negative bias temperature instability (NBTI) compensation transistor includes a source electrode coupled to receive a reference voltage, a drain electrode coupled to a source electrode of the first inverter, and a gate electrode coupled to first logic responsive to the first data signal.
    Type: Application
    Filed: January 28, 2011
    Publication date: August 2, 2012
    Inventors: Alexander B. Hoefler, James D. Burnett, Scott I. Remington
  • Patent number: 8188768
    Abstract: The present invention is directed for a comparator circuit used in an analog-to-digital converter, and more particularly, for a low power consumption low kick-back noise comparator circuit for an analog-to-digital converter, which can significantly reduce kick-back noise generated in a signal input stage due to a signal regeneration method employed in a signal comparing operation and can efficiently reduce power consumption.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: May 29, 2012
    Assignee: Postech Academy-Industry Foundation
    Inventors: Jun Hyun Bae, Hong June Park
  • Publication number: 20120119788
    Abstract: An apparatus for monitoring at least supply voltage in an IC includes a plurality of monitor circuits distributed throughout the integrated circuit. Each of the monitor circuits is operative to receive the supply voltage, or a signal representative thereof, and to generate an output signal indicative of a comparison between the supply voltage and a reference voltage. The apparatus further includes a control circuit coupled to the plurality of monitor circuits. The control circuit is operative to receive the respective output signals from the plurality of monitor circuits and to generate an output of the apparatus which is a function of information conveyed in the respective output signals from the plurality of monitor circuits.
    Type: Application
    Filed: November 17, 2010
    Publication date: May 17, 2012
    Inventors: Mark Franklin Turner, Jeffrey S. Brown, Jonathan W. Byrn
  • Patent number: 8143921
    Abstract: A compare cycle of a comparator includes a precharge phase and a compare phase. During the precharge phase, a node of the comparator is precharged to a defined voltage. In addition, during the precharge phase an input transistor of the comparator is decoupled from the node. During the compare phase, an input voltage is coupled to the node via the input transistor. The input transistor is maintained in saturation during both the precharge phase and the compare phase, reducing switching noise.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: March 27, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Fernando Z. Neto, Fernando Chavez Porras, Jon S. Choy, Walter Luis L. Tercariol
  • Patent number: 8140039
    Abstract: The present invention relates to a quadrature divider which may be used in a phase locked loop or frequency synthesizer or with a single side band mixer. According to a preferred embodiment the divider takes a quadrature input and has a quadrature output. The divider has four analog mixers 1, 2, 3 and 4. The first two mixers 1, 2 take the in-phase quadrature input, while the second mixers 3, 4 take the quadrature-phase quadrature input. The outputs and feedback loops of the mixers are properly arranged such that the in-phase and quadrature-phase outputs of the divider have a determinisitic phase sequence relationship based on the phase sequence relationship of the corresponding quadrature inputs. Third order harmonics may be minimized or reduced by addition or subtraction of the mixer outputs. As the divider is able to take a quadrature input, there is no need for a dummy divider in the phase locked loop, thus saving space and power.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: March 20, 2012
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Howard Cam Luong, Hui Zheng
  • Patent number: 8120385
    Abstract: The present disclosure relates to reduction in the effect of kickback in comparators by means of charge injection implemented by means of voltage controlled switches with attributes similar to those of an input differential pair. The voltage controlled switches produce charge to neutralize the charge loss during latching of inputs in the comparator.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: February 21, 2012
    Assignee: ST-Ericsson SA
    Inventors: Pratap Singh, Chandrajit Debnath
  • Patent number: 8111090
    Abstract: A comparator apparatus for comparing a first and a second voltage input includes a pair of cross-coupled inverter devices, including a pull up device and a pull down device, with output nodes defined between the pull up and pull down devices. A first switching device is coupled to the first input and a second switching device is coupled to the second input, with control circuitry configured for selective switching between a reset mode and a compare mode. In the reset mode, the first and second voltage inputs are coupled to respective output nodes so as to develop a differential signal thereacross, and the pull down devices in each inverter are isolated from the pull up devices. In the compare mode, the voltage inputs are isolated from the output nodes, and the pull down devices in each inverter are coupled to the pull up devices to latch the output nodes.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: February 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Fadi H. Gebara, Jeremy D. Schaub