Abstract: Pseudo resistor having an auto-tune function automatically calibrates resistance of the pseudo resistor and compensates for DC drift based on an output signal of an electrical circuit to which the pseudo resistor is coupled, as to mitigate signal phenomenon in the output signal caused by PVT variation. The pseudo resistor includes first transistor, second transistor, and adder. The first terminal of the second transistor is coupled to the first terminal of the first transistor and forms a first common node. The control terminal of the first transistor is coupled to the control terminal of the second transistor and forms second common node. The adder is coupled between the first and second common nodes and configured to receive adjustment voltage for generating a bias voltage for controlling the first and second transistors, where the adjustment voltage corresponds to the output signal coupled to the second terminal of the second transistor.

Abstract: A regeneration circuit includes a first inverting circuit, a second inverting circuit, a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to an input of the first inverting circuit. The regeneration circuit also includes a third transistor including a gate coupled to a gate of the first transistor, a first switch configured to couple the third transistor to the input of the second inverting circuit based on a voltage of the first inverting circuit, a fourth transistor including a gate coupled to a gate of the second transistor, and a second switch configured to couple the fourth transistor to the input of the first inverting circuit based on a voltage of the second inverting circuit.

Abstract: An n+ layer 3a connected to a source line SL at both ends, an n+ layer 3b connected to a bit line BL, a first gate insulating layer 4a formed on a semiconductor substrate 1 existing on an insulating film 2, a gate conductor layer 16a connected to a plate line PL, a gate insulating layer 4b formed on the semiconductor substrate, and a second gate conductor layer 5b connected to a word line WL and having a work function different from a work function of the gate conductor layer 16a are disposed on the semiconductor substrate, and data hold operation of holding, near a gate insulating film, holes generated by an impact ionization phenomenon or gate-induced drain leakage current inside a channel region 12 of the semiconductor substrate 1 and data erase operation of removing the holes from inside the substrate 1 and the channel region 12 are performed by controlling voltage applied to the source line SL, the plate line PL, the word line WL, and the bit line BL.

Abstract: A display device includes a substrate, a plurality of pixels provided to the substrate, a plurality of first light emitting elements provided to each of the pixels and configured to output visible light, a pixel circuit provided to the substrate and configured to supply a drive signal to each of the first light emitting elements, and a second light emitting element provided to the pixel circuit and configured to output infrared light.

Abstract: An integrated circuit including a power supply including an AC input, an AC to DC rectifier, a DC output of the rectifier, a switch for shunting the AC input, and a controller including a first connection to the DC output, a second connection to the AC input, wherein the controller is configured to monitor the DC output, determine if the DC output is within a first threshold of a desired output, monitor instantaneous AC voltage across the AC input, determine if an absolute difference of the AC input from zero voltage is less than a second threshold, and if the DC output is within the first threshold and the absolute difference of the instantaneous AC input from zero voltage is less than the second threshold, then provide a command to the switch to shunt the AC input. Related apparatus and methods are also described.

Abstract: A two-terminal device (TTD) capable of preventing leakage current by using diffusion current having bidirectionality and generated due to a potential barrier by an insulator, and a lighting device using the TTD are disclosed.

Abstract: A method of fabricating a semiconductor device includes forming a semiconductor fin structure over a substrate, where the semiconductor fin structure includes a plurality of semiconductor fins and defines trenches among the semiconductor fins, and forming a dielectric fin structure having a plurality of dielectric fins. Forming the dielectric fin structure includes filling the trenches with a first dielectric material layer and a second dielectric material layer over the first dielectric material layer, the second dielectric material layer having a composition different from that of the first dielectric material layer, removing a portion of the second dielectric material layer to form a recess, and filling the recess with a third dielectric material layer, the third dielectric material layer having the same composition as the first dielectric material layer.

Abstract: A semiconductor device including a semiconductor substrate having a first surface and a second surface that face each other, and having an element region and an isolation region, the element region including a transistor in the first surface, and the isolation region including an element isolation layer surrounding the element region; and a contact plug extending from the first surface to the second surface in the isolation region of the semiconductor substrate.

Abstract: An energy supply device to supply electrical energy for at least one terminal device, with a power grid connector for connection of the energy supply device to an alternating current power grid and with a rectifier device for conversion of an alternating current supplied via the power grid connector to a direct current in an intermediate circuit. In this case, a plurality of voltage transformers and a plurality of direct current terminals are provided, wherein the voltage transformers are each electrically connected, on the one hand, at least intermittently, to the intermediate circuit and, on the other hand, at least intermittently, to a direct current terminal of the plurality of direct current terminals.

Abstract: A method of forming a semiconductor device, the method comprises forming a gate trench and a contact trench concurrently in a semiconductor substrate using a patterned masking layer, forming a gate conductive filler in the gate trench, forming a deep body region below the contact trench, and forming a contact conductive filler in the contact trench. The method further comprises forming a gate trench dielectric liner in the gate trench, forming a gate trench dielectric liner in the gate trench, and forming an interlayer dielectric layer (IDL) over the gate conductive filler. The method further comprises forming a contact implant at a bottom of the contact trench, and forming a barrier layer in the contact trench.

Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

Abstract: A semiconductor FET provides a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies.

Abstract: Some embodiments include an integrated assembly having digit lines extending along a first direction, and rails over the digit lines. The rails include semiconductor-material pillars alternating with intervening insulative regions. The rails have upper, middle and lower segments. A first insulative material is along the upper and lower segments of the rails. A second insulative material is along the middle segments of the rails. The second insulative material differs from the first insulative material in one or both of thickness and composition. Conductive gate material is along the middle segments of the rails and is spaced from the middle segments by the second insulative material. Channel regions are within the middle segments of the pillars, upper source/drain regions are within the upper segments of the pillars and lower source/drain regions are within the lower segments of the pillars. Some embodiments include methods of forming integrated assemblies.

Abstract: An optical detector includes a stacked structure, an active layer, a gate insulating layer, and a gate electrode. The stacked structure includes a first electrode, a photoelectric conversion layer, a second electrode, a first insulating layer, and a third electrode. The active layer is electrically coupled to one of the first electrode or the second electrode, and electrically coupled to the third electrode. The gate insulating layer is arranged on the active layer. The gate electrode is arranged on the gate insulating layer.

Abstract: A novel MRI-compatible amplifier design uses positive feedback from a low-noise Field-Effect Transistor to amplify the signal current within a resonant NMR coil. The amplified signal current in this low-power circuit produces RF flux can be coupled out to receiving loops positioned externally without significant loss in sensitivity. In other aspects, the amplifier may be remotely powered by external resonant loops, a small non-magnetic battery, or optical power, such that the NMR coil can be positioned during highly invasive procedures such as for surgical resection of tumors in deep-lying tissues to develop high-resolution images.

Abstract: A junction termination with an internal field plate, the field plate structure and the junction termination extension region are folded inside the device to make full use of the thickness of the drift region in the body, thereby reducing the area of the termination and relieving the electric field concentration at the end of the PN junction. The breakdown position is transferred from the surface into the body of the original PN junction, and the withstand voltage of termination can reach to the breakdown voltage of the parallel plane junction. Under such design, a smaller area can be obtained than that of the conventional structure at the same withstand voltage.

Abstract: In accordance with an embodiment, a cascode connected semiconductor component and a method for manufacturing the cascode connected semiconductor component are provided. The cascode connected semiconductor component has a pair of silicon based transistors, each having a body region, a gate region over the body region, a source region and a drain. The source regions of a first and second silicon based transistor are electrically connected together and the drain regions of the first and second silicon based transistors are electrically connected together. The gate region of the second silicon based transistor is connected to the drain regions of the first and second silicon based transistors. The body region of the second silicon based transistor has a dopant concentration that is greater than the dopant concentration of the first silicon based transistor. A gallium nitride based transistor has a source region coupled to the first and second silicon based transistor.

Abstract: An electrical chain-link converter system includes a converter phase leg for converting a plurality of DC electrical currents from a plurality of DC power sources to an AC current of an electrical power distribution network. The phase leg includes a plurality of serially connected converter cells each of which is connected to a respective power source of the plurality of DC power sources. The system also includes a control unit associated with the phase leg, the control unit including a processor; and a storage unit storing instructions that, when executed by the processor, cause the control unit to, for each of the converter cells: obtain a dedicated voltage reference for the converter cell; and transmit the voltage reference to the converter cell.

Abstract: A semiconductor switching circuit, for use in a HVDC power converter, comprising: a main semiconductor switching element, including first and second connection terminals between which current flows from the first connection terminal to the second connection terminal and an auxiliary semiconductor switching element electrically connected between the first and second connection terminals thereof, and a control unit, operatively connected to auxiliary semiconductor switching element and programmed to control the switching element to create an alternative current path between the first and second connection terminals by at least two of: a fully-on mode in which the switching element is operated at its maximum rated base current or gate voltage; a pulsed switched mode in which the switching element is turned on and off; and an active mode in which the switching element is operated with a continuously variable base current or gate voltage.

Abstract: An electrical system can include a power supply coupled to an electrical load, where the power supply includes an AC/DC converter and a number of DC/DC converters, where the AC/DC converter provides raw DC power to the DC/DC converters, where the DC/DC converters receive the raw DC power and generate final DC power for the electrical load. The electrical system can also include a controller coupled to the power supply, where the controller selectively enables and disables the DC/DC converters.

Abstract: The invention relates to a DC power distribution system for distributing DC power to one or several electrical devices. The system comprises an electrical device (2) for receiving DC power via an electrical conductor (4) from a power supply device (3) with a power supply control unit (5) and for transmitting a signal to the power supply control unit for requesting a lower power or a higher power. The power supply device is operable in a high power mode and in a low power mode, wherein the power supply control unit controls the power mode of the power supply device depending on the received signal. This allows adapting the power supply to the power, which is actually really needed in the DC power distribution system, in a technically relatively simple way. Particularly standby situations can be handled more efficiently.

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Abstract: In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

Abstract: A power amplifier includes an amplifier element and overstress management circuitry coupled to the amplifier element. The overstress management circuitry is configured to detect an overstress condition of the amplifier element and adjust one or more operating parameters of the amplifier element in response to the detection of an overstress condition of the amplifier element. Using the overstress management circuitry prevents damage to the amplifier element that may occur due to uncorrected overstress conditions which may degrade or destroy a gate oxide of the amplifier element. Accordingly, the longevity of the amplifier element is improved.

Abstract: Representative implementations of devices and techniques provide a linearized high-ohmic resistor. In an example, a quantity of serially connected nonlinear impedances is arranged as a resistance. In one example, the quantity of impedances is applied in an amplifier circuit, between an input of the amplifier and an output of the amplifier, and arranged to set a DC operating point for the amplifier.

Abstract: A radio-frequency amplifier circuit includes first and second FETs cascode-connected to each other. The gate of the first FET is connected to a radio-frequency input terminal, and the drain of the second FET is connected to a radio-frequency output terminal. The source of the first FET is connected to a ground, and the drain of the first FET and the source of the second FET are connected to each other. A drive voltage is applied to the drain of the second FET. A bias setting unit is connected to the gate of the second FET. The bias setting unit sets a second control voltage to be applied to the second FET so that a node voltage between the drain of the first FET and the source of the second FET will be substantially half of the drive voltage.

Abstract: A method for fabricating monolayer graphene-boron nitride heterostructures in a single atomically thin membrane that limits intermixing at boundaries between graphene and h-BN, so as to achieve atomically sharp interfaces between these materials. In one embodiment, the method comprises exposing a ruthenium substrate to ethylene, exposing the ruthenium substrate to oxygen after exposure to ethylene and exposing the ruthenium substrate to borazine after exposure to oxygen.

Abstract: A transistor device includes a first conductivity type drift layer, a second conductivity type first region in the drift layer, a body layer having the second conductivity type on the drift layer including the first region, a source layer on the body layer, and a body contact region that extends through the source layer and the body layer and into the first region. The transistor device further includes a trench through the source layer and the body layer and extending into the drift layer adjacent the first region. The trench has an inner sidewall facing away from the first region. A gate insulator is on the inner sidewall of the trench, and a gate contact is on the gate insulator.

Abstract: A semiconductor FET provides a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies.

Abstract: An integrated circuit includes a capacitor having first, second and third nodes. The first and second nodes of the first transistor are connected together and the first and second nodes of the second transistor are connected together. The third node of the first transistor is connected to the third node of the second transistor. Each of the third nodes is constructed so that each node comprises a width and a length that is at least ten percent of the width.

Abstract: A gate control circuit for controlling gates of at least a half side of an H-bridge circuit includes: an input terminal configured to connect to a PWM signal; a power terminal configured to connect to a voltage source that supplies a positive voltage; a ground terminal configured to connect to a ground reference; and a control circuit connected with the input terminal, the power terminal, and the ground terminal. The control circuit includes: two high side switches configured to be connected with the voltage source respectively through the power terminal; two low side switches configured to be connected with the ground reference respectively through the ground terminal; a first inverter connecting the two high side switches; a second inverter connecting the two low side switches; and a first resistor and a second resistor connecting the two high side switches to the two low side switches respectively.

Abstract: In accordance with one exemplary embodiment, an electronic circuit is provided, wherein the electronic circuit comprises a first transistor and also a second transistor coupled in series with the first transistor. Furthermore, the electronic circuit comprises a capacitor, wherein a first terminal of the capacitor is coupled to a control terminal of the second transistor, and wherein a second terminal of the capacitor is coupled to an electrical potential which is dependent on a radio-frequency input signal of the electronic circuit.

Abstract: A transistor with excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) is provided. The transistor includes an oxide semiconductor layer including a channel formation region, a first gate electrode, a second gate electrode, a source electrode, and a drain electrode. The oxide semiconductor layer is between the first gate electrode and the second gate electrode. The oxide semiconductor layer has a pair of side surfaces in contact with the source electrode and the drain electrode and includes a region surrounded by the first gate electrode and the second gate electrode without the source electrode and the drain electrode interposed therebetween.

Abstract: The present disclosure relates to a graphene roll-to-roll transfer method, a graphene roll-to-roll transfer apparatus, a graphene roll manufactured by the graphene roll-to-roll transfer method, and uses thereof.

Abstract: A circuit for reducing flicker noise includes a first current source coupled to an input current. The circuit includes current minors to generate output currents in response to the input current. The output currents include the flicker noise. In addition, the circuit includes a chopping circuit to reduce the flicker noise from each of the output currents.

Abstract: A variety of circuits, methods and devices are implemented for providing an adjustable resistance. According to one such implementation an adjustable resistive device includes a metal-oxide semiconductor (MOS) transistor having a gate, a drain, a source, and a body. First circuitry controls a resistance from drain to source by applying a gate voltage that is a function of a variable control input. Second circuitry adjusts a voltage at the body according to a drain voltage and a source voltage, whereby the resistance from drain to source is substantially linear for a given value of the variable control input and over a voltage range.

Abstract: One or more systems and techniques for limiting a voltage potential between an antenna and a radio-frequency switch circuit are provided. A voltage controller comprises a voltage generator, a voltage detection circuit and a switch cell. The voltage detection circuit is coupled to the voltage generator and to the switch cell, and the switch cell is coupled to a voltage source, and to a node between the radio-frequency switch circuit and the antenna. When the voltage potential exceeds a specified threshold, the voltage generator produces a voltage which the voltage detection circuit measures such that the voltage detection circuit activates the switch cell, resulting in a short circuit between the radio-frequency switch circuit and the voltage source. This serves to inhibit the voltage potential from exceeding the specified threshold, for example.

Abstract: A compensated hysteresis circuit comprises a hysteresis circuit including an output node and a first control transistor. The first control transistor provides feedback to the hysteresis circuit. A temperature and voltage compensation circuit includes a self-biasing threshold control circuit including an input coupled to the output node of the hysteresis circuit, and a first trim transistor coupled between the first control transistor of the hysteresis circuit and the self-biasing threshold control circuit.

Abstract: A circuit includes a direct current (DC) gate termination impedance having an impedance for DC signals higher than a maximum impedance DC at which dendrite growth occurs in the circuit, and a radio frequency (RF) gate termination impedance having an impedance for RF signals lower than a maximum impedance at which RF stability for the circuit is maintained for an application.

Abstract: A method for reducing an off-current of a field effect transistor in which two electrodes of the field effect transistor have fixed voltage values and the rest electrode has an alternating voltage value by an AC voltage pulse generator to form an off-stress near source and drain junctions in turn.

Abstract: Circuits that operate with power supplies of less than 1 Volt are presented. More particularly, circuits that operate with supply voltages near or lower than the threshold voltage of the transistors in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers, biasing circuits, integrators, continuous-time sigma delta modulators, track-and-bold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor to bipolar junction transistors may implement the techniques presented herein.

Abstract: A current source and an associated method for supplying current to a load such as an arrangement of LEDs. The intensity of the supplied current varies as a function of the temperature of the load. The intensity of the current is temperature-dependent and limited to a predefined maximum. The temperature dependence is achieved by the component parts that are used without the help of special temperature sensors. The current source is supplied with a reference voltage derived from an integrated circuit. The reference voltage is tapped from a port of the IC and therefore it is switchable. The reference voltage is used to produce a control current, which is fed through a driver stage to produce the current of the current source. Elements in the current source limit the current's intensity and change it as a function of temperature.

Abstract: A semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a voltage generator configured to generate a test voltage, a graphene transistor configured to receive a gate-source voltage based on the test voltage, and a detector configured to detect whether the gate-source voltage is a Dirac voltage of the graphene transistor, and output a feedback signal applied to the voltage generator indicating whether the gate-source voltage is the Dirac voltage.

Abstract: A reference circuit comprises a first proportional to temperature component providing a first quantity exhibiting a first type of variation as a function of temperature, a first complementary to temperature component providing a second quantity exhibiting a second type of variation as a function of temperature that is complementary to the first type of variation, and curvature correction circuitry. An output of the reference circuit provides a reference signal generated based on a combination of the first and second quantities. The curvature correction circuitry is coupled to the reference circuit output and comprises at least one additional complementary to temperature component. The curvature correction circuitry adjusts the reference signal in a feedback arrangement to compensate for a temperature response bowing effect attributable to combining the first and second quantities. The reference circuit may be implemented in a disk-based storage device for use in fly height control or other control functions.

Abstract: Semiconductor devices include a transistor having a gate structure located close to a channel region that comprises a colossal magnetocapacitive material. The gate structure is configured to affect electrical current flow through the channel region between a source and a drain. The colossal magnetocapacitive material optionally may be disposed between two structures, one or both of which may be electrically conductive, magnetic, or both electrically conductive and magnetic. Methods of fabricating semiconductor devices include forming a colossal magnetocapacitive material close to a channel region between a source and a drain of a transistor, and configuring the colossal magnetocapacitive material to exhibit colossal magnetocapacitance for generating an electrical field in the channel region. Methods of affecting current flow through a transistor include causing a colossal magnetocapacitive material to exhibit colossal magnetocapacitance and generate an electrical field in a channel region of a transistor.

Abstract: In various embodiments, a circuit is provided including a supply terminal, a logic circuit, an inverter and a control transistor which may include a body region, first and second source/drain regions, a gate insulating region having a layer thickness and a gate region. The first source/drain region may be coupled to the supply terminal. The logic circuit may have an internal supply terminal connected to the second source/drain region of the control transistor and a plurality of transistors each having a gate insulating region having a second layer thickness. The inverter input may be coupled to the internal supply terminal of the logic circuit and the output to the gate region of the control transistor. The inverter may include a transistor with a gate insulating region having a third layer thickness substantially equal to the first and second layer thicknesses.

Abstract: A solid state Klystron structure is fabricated by forming a source contact and a drain contact to both ends of a conducting wire and by forming a bias gate and a signal gate on the conducting wire. The conducting wire may be at least one carbon nanotube or at least one semiconductor wire with long ballistic mean free paths. By applying a signal at a frequency that corresponds to an integer multiple of the transit time of the ballistic carriers between adjacent fingers of the signal gate, the carriers are bunched within the conducting wire, thus amplifying the current through the solid state Klystron at a frequency of the signal to the signal gate, thus achieving a power gain.

Abstract: An isolator circuit (25) for a unit of a safety system (10) includes a power control line (14) connectable to a first loop of a safety system and a power connection (16) connectable to a second loop of the safety system. A switch (26) is connected to the power control line (14), and the switch has a closed configuration and an open configuration. A controller (28) controls the configuration of the switch (26). If a voltage across the circuit (10) from the power connection (16) to the power control line (14) falls below a predetermined level, the controller (28) opens the switch (26), thereby causing a disconnection to occur in the first loop.

Abstract: A system and circuit for simulating gate-to-drain breakdown in an N-channel field effect transistor (NFET). In one embodiment, a simulation circuit includes a primary field effect transistor (FET), a first depletion mode FET and a second depletion mode FET. The first depletion mode FET and the second depletion mode FET are connected between a gate and a drain of the primary FET. A gate and a drain of the first depletion mode FET are connected to the gate of the primary FET. A gate and a drain of the second depletion mode FET are connected to the drain of the primary FET.

Abstract: A variable-capacitance device includes a first capacitance element coupled between a first power supply terminal and an output terminal, a capacitance selection switch that is turned on and off in accordance with a capacitance switching signal, a second capacitance element coupled in parallel to the first capacitance element and in series to the capacitance selection switch, and an error correction circuit configured to operate such that in a state in which the capacitance selection switch is in an OFF state, in response to a charge reset signal that causes a voltage at the output terminal to be reset to a reset voltage, the error correction circuit substantially eliminates a difference between the voltage at the output terminal and a voltage at a capacitance switching node at which the second capacitance element is coupled to the capacitance selection switch.