Abstract: A semiconductor device includes a lateral double diffused metal oxide semiconductor (LDMOS) , a junction field effect transistor (JFET) and an inner circuit. The lateral double diffused metal oxide semiconductor includes a first source, a common drain and a first gate. The junction field effect transistor includes a second source, the common drain and a second gate. The second source is electrically connected to the first gate. The inner circuit is electrically connected to the first source.

Abstract: An exemplary voltage regulating circuit for a motherboard includes a selecting switch and a first switch module, the selecting switch comprising a first input terminal arranged to receive a standby power provided by a power supply, a first control terminal arranged to receive a state signal from the motherboard via a first switch module controlled by a power good signal generated by the power supply, and an output terminal, wherein, when the motherboard is turned off, the state signal is at a high level and the first switch module is turned on by the power good signal for turning off the selecting switch to stop outputting the standby power.

Abstract: A method and system for bandwidth enhancement using hybrid inductors are disclosed and may include providing an electrical impedance that increases with frequency via hybrid inductors comprising a transistor, a capacitor, an inductor, and a resistor. A first terminal of the hybrid inductors may comprise a first terminal of the transistor. A second terminal of the transistor may be coupled to a first terminal of the resistor and a first terminal of the capacitor. A second terminal of the resistor may comprise a second terminal of the hybrid inductors. A third terminal of the transistor may be coupled to a first terminal of an inductor, and a second terminal of the inductor may be coupled to a second terminal of the capacitor. The hybrid inductors may be configured by varying transconductance, resistance, and/or capacitance and may be utilized as an amplifier load.

Abstract: A double-gate semiconductor device includes a MOS gate and a junction gate, in which the bias of the junction gate is a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices. The double-gate semiconductor device may also be fabricated in a higher spatial density configuration such that a common implantation between the MOS gate and the junction gate is eliminated.

Abstract: A semiconductor device such as an RFID, which can easily generate a given stable potential, is provided. Circuits included in a semiconductor device are categorized depending on whether a given stable power source potential is necessary. A power source potential generated from a wireless signal received by an antenna with the use of the antenna and a rectifier circuit is supplied to a circuit which needs a given stable power source potential through a regulator. On the other hand, a power source potential generated by the rectifier circuit is supplied to a circuit other than the circuit which needs the arbitrary power source potential. Thus, a semiconductor device including a regulator circuit easily designed with a smaller layout can be provided, and the semiconductor device can easily generate a given stable power source potential.

Abstract: A power supply for providing power to an electrical device is described. The power supply converts a received input signal to a first electrical having a first voltage level at a first power converter. The power supply additionally converts the first electrical signal to a second electrical signal having a second voltage level at a second power converter, to provide the second electrical signal having the second voltage level to an output port. The power supply includes a circuit to selectively bypass the second power converter and provide the first electrical signal having the first voltage level from the first power converter to the output port. The first power converter may include one or more switches that may be disabled to disconnect power from the first power converter for additional standby power saving features.

Abstract: In accordance with one exemplary embodiment, an electronic circuit is provided, wherein the electronic circuit comprises a first transistor and also a second transistor coupled in series with the first transistor. Furthermore, the electronic circuit comprises a capacitor, wherein a first terminal of the capacitor is coupled to a control terminal of the second transistor, and wherein a second terminal of the capacitor is coupled to an electrical potential which is dependent on a radio-frequency input signal of the electronic circuit.

Abstract: A bidirectional Trench Lateral Power MOSFET (TLPM) can achieve a high breakdown voltage and a low on-resistance. A plurality of straight-shaped islands having circular portions at both ends are surrounded by a trench arrangement. The islands provide first n source regions and a second n source region is formed on the outside of the islands. With such a pattern, the breakdown voltage in the case where the first n source regions are at a high potential can be higher than the breakdown voltage in the case where the second n source region is at a high potential. Alternatively, in the case of not changing the breakdown voltage, the on-resistance can be reduced.

Abstract: The present disclosure relates to impedance transformation with transistor circuits.

Abstract: A system and method are provided to reduce the influence of parasitic capacitance at the drain and source of MOS transistors of a sampling circuit. In one embodiment, the bulk is left floating during a first phase and refreshed during a second phase. During the first phase, the effective parasitic contribution of the drain or source of a MOS transistor is lower due to the series combination of Cj and Cw capacitances. In another embodiment, a large resistance provides a path from a reference voltage to the bulk of a MOS transistor, thereby resulting in an effective parasitic capacitance of the series combination of Cj and Cw. Advantageously, the parasitic capacitance is reduced as well as its non-linear effect, the operating speed is improved, as well as the signal distortion and noise.

Abstract: Electronic apparatus and methods of forming the electronic apparatus may include a tantalum aluminum oxynitride film for use in a variety of electronic systems and devices. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.

Abstract: A traveling wave device employs an active Gallium Nitride FET. The Gallium Nitride FET has a plurality of gate feeding fingers connecting to an input gate transmission line. The FET has a drain electrode connected to an output drain transmission line with the source electrode connected to a point of reference potential. The input and output transmission lines are terminated with terminating impedances which are not matched to the gate and drain transmission lines. The use of Gallium Nitride enables the terminating impedance to be at much higher levels than in the prior art. The use of Gallium Nitride permits multiple devices to be employed, thus resulting in higher gain amplifiers with higher voltage operation and higher frequency operation. A cascode traveling wave amplifier employing GaN FETs is also described having high gain and bandwidth.

Abstract: Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

Abstract: A variable gain amplification circuit comprises a signal generator that has an output terminal and is able to vary an output amplitude; a variable capacitor connected between the output terminal and an AC grounded terminal; and a control circuit for controlling the output amplitude of the signal generator, and a capacitance of the variable capacitor. Therefore, unnecessary signals can be attenuated even when the gain is low, and degradation in distortion characteristics in the latter block can be suppressed.

Abstract: Embodiments include but are not limited to apparatuses and systems including a field-effect transistor switch. A field-effect transistor switch may include a first field plate coupled with a gate electrode, the first field plate disposed substantially equidistant from a source electrode and a drain electrode. The field-effect transistor switch may also include a second field plate proximately disposed to the first field plate and disposed substantially equidistant from the source electrode and the drain electrode. The first and second field plates may be configured to reduce an electric field between the source electrode and the gate electrode and between the drain electrode and the gate electrode.

Abstract: In one embodiment, a sensing circuit includes a sense transistor and a compensation circuit to improve the accuracy of a sensing signal formed by the sensing circuit.

Abstract: A circuit and method for compensating for parasitic elements of a transistor. A transistor, a controller, and a compensation element are mounted to a printed circuit board. The transistor includes parasitic drain and source inductors. The compensation element may be a discrete inductor that has an inductance value equal to about the sum of the inductance values of the parasitic drain and source inductors. The magnitudes of the compensation voltage and the sum of the voltages across the parasitic drain and source inductances are substantially equal. Thus, the compensation voltage developed across the compensation inductor is used to adjust a reference voltage within the controller. A drain-to-source voltage is applied to one input of a comparator within the controller and the adjusted reference voltage is applied to another input of the comparator. An output signal of the comparator is input to drive circuitry that drives a gate of the transistor.

Abstract: Aspects provide for the broadband amplification of RF signals. Other aspects provide for the conversion of single ended input to differential output. Various aspects provide for tuning the response to a particular frequency band. Other aspects provide for various transconductance elements. In several aspects, broadband current to voltage converters and voltage to current converters are presented. Some implementations incorporate a buffer circuit, and various implementations incorporate feedback circuits.

Abstract: Aspects provide for the broadband amplification of RF signals. Other aspects provide for the conversion of single ended input to differential output. Various aspects provide for tuning the response to a particular frequency band. Other aspects provide for various transconductance elements. In several aspects, broadband current to voltage converters and voltage to current converters are presented. Some implementations incorporate a buffer circuit, and various implementations incorporate feedback circuits.

Abstract: A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.

Abstract: A III-nitride based high electron mobility transistor is described that has a gate-connected grounded field plate. The gate-connected grounded field plate device can minimize the Miller capacitance effect. The transistor can be formed as a high voltage depletion mode transistor and can be used in combination with a low voltage enhancement-mode transistor to form an assembly that operates as a single high voltage enhancement mode transistor.

Abstract: A doped semiconductor region having a same conductivity type as a bottom semiconductor layer is formed underneath a buried insulator layer in a bottom semiconductor layer of a semiconductor-on-insulator (SOI) substrate. At least one conductive via structure is formed, which extends from a interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to the doped semiconductor region. The shallow trench isolation structure laterally abuts at least one field effect transistor that functions as a radio frequency (RF) switch. During operation, the doped semiconductor region is biased at a voltage that keeps an induced charge layer within the bottom semiconductor layer in a depletion mode and avoids an accumulation mode. Elimination of electrical charges in an accumulation mode during half of each frequency cycle reduces harmonic generation and signal distortion in the RF switch.

Abstract: Mutual capacitances between regions of a MOS device become substantial factors that limit the speed and performance of the device as the device dimensions are reduced in size. A MOS transistor with a shielding structure formed above the gate is described. The shielding structure is connected to ground and is configured to reduce at least some of these mutual capacitances.

Abstract: A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.

Abstract: A low noise reference voltage circuit without using an amplifier inside is capable of transforming a current IPTAT in positive proportion to absolute temperature into a voltage VPTAT in positive proportion to absolute temperature, and outputting it to a ring oscillator. The low noise reference voltage circuit improves a degradation of noise performance compared with a conventional band-gap reference voltage circuit and is in characteristic of low noise and higher PSRR.

Abstract: A cost-effective device for influencing the transmission of electrical energy of an alternating voltage line with a plurality of phases has phase modules, which each have an alternating voltage terminal for connecting to a phase of the alternating voltage line and two connecting terminals. A phase module branch extends between each connecting terminal and each alternating voltage terminal. The phase module branch is formed of a series connection of sub-modules, each having a power semiconductor circuit and an energy accumulator connected in parallel to the power semiconductor circuit. The connecting terminals are connected to one another. The power semiconductor circuit is equipped with power semiconductors that can be switched off and are connected to each other in a half bridge.

Abstract: A body switch system includes a timing module that generates a plurality of clock signals, an input node that receives an input signal, an output node that transmits an output signal; and a body switch circuit that selectively couples a body of a first transistor of a plurality of transistors to one of the input node and the output node and a body of a second transistor of the plurality of transistors to the other one of the input node and the output node based on the plurality of clock signals.

Abstract: A system and method for emulating an ideal diode for use in a power control device is provided. In one embodiment, the invention relates to a circuit for emulating an ideal diode, the circuit including at least one field effect transistor including a source, a drain, a gate, and a body diode, an input; an output coupled to the drain, a control circuit including a current sensor coupled between the input and the source, and a control circuit output coupled to the gate, wherein the control circuit is configured to activate the at least one field effect transistor based on whether the current flowing into the source is greater than a predetermined threshold, and wherein the body diode comprises an anode coupled to the source and a cathode coupled to the drain.

Abstract: A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).

Abstract: A quantum interference transistor may include a source; a drain; N channels (N?2), between the source and the drain, and having N?1 path differences between the source and the drain; and at least one gate disposed at one or more of the N channels. One or more of the N channels may be formed in a graphene sheet. A method of manufacturing the quantum interference transistor may include forming one or more of the N channels using a graphene sheet. A method of operating the quantum interference transistor may include applying a voltage to the at least one gate. The voltage may shift a phase of a wave of electrons passing through a channel at which the at least one gate is disposed.

Abstract: Provided is a highly efficient rectifier which can readily replace a two-terminal diode and whose conduction loss is reduced from that of the two-terminal diode. Connected between the source and drain of a MOSFET (2) including a parasitic diode (2a) are: a micro-power converter section (3) for boosting a conduction voltage Vds between the source and drain to a predetermined voltage; and a self-drive control section (4) that operates based on a voltage outputted from the micro-power converter section (3). When the source and drain are conductive with each other, the micro-power converter section (3) generates, from the conduction voltage Vds, a power source voltage for the self-drive control section (4), and the self-drive control section (4) continues drive control of the MOSFET (2).

Abstract: A semiconductor device including a bias voltage generator formed from a junction field effect transistor (JFET). The JFET includes a control gate terminal and a first and a second source/drain terminal. The first and second source/drain terminals can form a first terminal of a p-n junction and the control gate terminal can form a second terminal of the p-n junction. The first terminal of the p-n junction can be provided with a first potential. The second terminal can be left essentially floating to provide a bias voltage. A bias receiving circuit can receive the bias voltage. The bias receiving circuit can be in close proximity on the semiconductor device to the bias voltage generator.

Abstract: A method and circuit arrangement for increasing the dielectric strength of at least one metal oxide transistor at low temperatures is described. Various embodiments include heating the metal oxide transistor prior to the application of a voltage in the vicinity of a breakdown voltage of the metal oxide transistor.

Abstract: A circuit is provided that (in one implementation) includes a first transistor having a first drain terminal, first gate terminal, and a first source terminal. The first drain terminal is connected to the first gate terminal, the first source terminal is connected to a first voltage. The circuit further includes a second transistor having a second drain terminal, second gate terminal, and a second source terminal. The second gate terminal is connected to both the first gate terminal and the first drain terminal, and the second source terminal is connected to the first voltage. The circuit further includes a third transistor having a third drain terminal, a third gate terminal, and a third source terminal. The third drain terminal is connected to the first drain terminal, and the third source terminal is connected to both the third gate terminal and a second voltage that is lower than the first voltage.

Abstract: The invention relates to a method and a corresponding circuit for protecting a power MOSFET from thermal overload when switching the MOSFET off and on, wherein the MOSFET is switched on again after at least a determined off-period has passed.

Abstract: A stacked MOS configuration for use in short channel length analog circuit technologies is provided. The stacked MOS configuration comprises a plurality of short-channel MOS transistors coupled in series and sharing a common gate terminal. In an embodiment, a first peripheral transistor provides a drain terminal for the stacked MOS configuration. A second peripheral transistor provides a source terminal for the stacked MOS configuration. Adjacent transistors in the stacked MOS configuration are connected in a drain-to-source configuration.

Abstract: An integrated circuit has a control circuit (2) for a power field-effect transistor (3), wherein the integrated circuit has a first input (202) for receiving a control signal (CE) and an output to switch the field-effect transistor (3) on or off. The control circuit further has a driver circuit for providing a voltage level at the output in response of the control signal. A second input is provided for receiving a configuration signal, the configuration signal for configuring the voltage level being provided by the driver circuit in response to the control signal.

Abstract: A vertical device structure includes a volume of semiconductor material, laterally adjoining a trench having insulating material on sidewalls thereof. A gate electrode within the trench is capacitively coupled through the insulating material to a first portion of the semiconducting material. Some portions of the insulating material contain fixed electrostatic charge in a density high enough to invert a second portion of the semiconductor material when no voltage is applied. The inverted portions can be used as induced source or drain extensions, to assure that parasitic are reduced without increasing on-resistance.

Abstract: Operations as a variable resistor are favorably realized even when a drain-source voltage of a variable MOS resistor and that of a reference MOS resistor are not the same. A gate voltage Vp12 of the variable MOS resistor is controlled with reference to a gate voltage Vp11 which is controlled such that a voltage generated in the reference MOS resistor is controlled to be the same as a reference voltage. A resistor is connected in parallel with the reference MOS resistor between the drain and source thereof, the resistor including resistor bodies R11 and R12 having the same resistance connected in series. Half of a drain-source voltage Vds of the reference MOS resistor is detected at an intermediate point of the resistor having resistor bodies connected in series. The gate voltage Vp12 of the variable resistor is obtained by subtracting Vds/2 from the gate voltage Vp11 of the reference MOS resistor.

Abstract: An electronic circuit such as a latch or a sequencer includes a plurality of transistors, all of the transistors being either NMOS transistors or PMOS transistors, and dissipates less than or approximately the same amount of power as an equivalent CMOS circuit.

Abstract: A semiconductor integrated circuit apparatus and an electronic apparatus having a power control function configured from power control MOS transistors such that leakage current and on-resistance at the time of cut-off is sufficiently small in actual use. The semiconductor integrated circuit apparatus includes a CMOS logic circuit, a first pseudo power supply line connected to a high potential side power supply terminal of the CMOS logic circuit, a second pseudo power supply line connected to a low potential side power supply terminal of the CMOS logic circuit, and a power control NchMOS transistor connected across the second pseudo power supply line and a low potential side power supply line, with the substrate and gate of the power control NchMOS transistor being electrically connected. The gate and the substrate may also be connected via a current limiter utilizing a source follower of a depletion type NchMOS transistor.

Abstract: A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes: An auxiliary inductor in series with the main switching FET for inducing an auxiliary inductive voltage proportional to di/dt. An auxiliary FET in parallel with the main switching FET. The auxiliary FET gate is connected to produce a gate voltage equal to the auxiliary inductive voltage. When the di/dt tends to exceed a pre-determined maximum rate of decrease, the auxiliary FET produces an auxiliary current component counteracting further decrease of the di/dt. The main switching FET and the auxiliary FET can be formed from a single die with shared source and drain. The auxiliary inductor can be implemented as a parasitic inductance of an inherently required bonding wire connecting the main switching FET to its device terminal to simplify packaging with reduced cost.

Abstract: Devices and systems for generating a bias current with a low minimum voltage, for example, are disclosed. One such device includes a first transistor having a source coupled to a voltage supply, a drain coupled to a first node, and a gate coupled to a second node, a second transistor having a source coupled to a reference, and a drain and a gate coupled to the first node, a third transistor having a source coupled to the reference, a drain coupled to a third node, and a gate coupled to the first node, a first resistive element coupled between the voltage supply and the third node, a second resistive element coupled between the voltage supply and the second node, and a fourth transistor having a source coupled to the reference, a drain coupled to the second node, and a gate coupled to the third node.

Abstract: A design structure embodied in a machine readable medium used in a design process includes a voltage divider device, including a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region; the first and second gates configured to have an input voltage coupled thereacross; and at least one of a source of the FET and a drain of the FET configured to have an output voltage taken therefrom; wherein the output voltage represents a divided voltage with respect to the input voltage.

Abstract: Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery.

Abstract: A standard cell includes an input terminal, an output terminal, first and second inverters coupled in series between the input and output terminals, the first inverter including a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor being coupled between a first power source terminal and a first node, and the second transistor being coupled between a second node and a second power source terminal, and a plurality of resistance elements which are used to provide a conductivity path between the first and second nodes, in order to adjust a duty ratio of a signal which passes the standard cell.

Abstract: The invention provides a semiconductor device that is thermally isolated from the printed circuit board such that the device operates at a higher temperature and radiates heat away from the printed circuit board. In another embodiment, the semiconductor is stacked onto a second device and optionally thermally isolated from the second device.

Abstract: A current consumption prevention apparatus includes a first current supply unit for transferring charges from a capacitor connected to a first inverter group to a capacitor connected to a second inverter group, and a second current supply unit for transferring charges of the capacitor connected to the second inverter group to the capacitor connected to the first inverter group. The current supply units are operated complementarily.

Abstract: A switching power converter with a controlled startup mechanism includes a switching stage which provides a voltage Vout at an output node in response to a switching control signal, with the output node adapted for connection to a non-linear load. A feedback network compares a signal which varies with the current conducted by the load (Iload) with a reference signal, and provides the switching control signal so as to maintain Iload at a desired value. A capacitor connected to the output node provides a current Ic to the feedback network which varies with dVout/dt. The feedback network is arranged to limit dVout/dt in response to current Ic when Iload is substantially zero. In this way, large inrush currents or damage that might otherwise occur during startup are avoided.

Abstract: A dual voltage switching circuit includes an input terminal receiving a control signal, an output terminal, three transistors, and a Zener diode. The gate of the first transistor is connected to the input terminal. The drain of the first transistor is connected to a standby power and the gate of the second transistor. The drain of the second transistor is connected to a first system power and the gate of the third transistor. The sources of the first transistor and the second transistor are grounded. The drain of the third transistor is connected to the input terminal. The source of the third transistor is connected to a second system power. The anode of the Zener diode is connected to the standby power. The cathode of the Zener diode is connected to the output terminal. The output terminal selectively outputs the standby power or the second system power.