Abstract: A locally gated graphene nanostructure is described, along with methods of making and using the same. A graphene layer can include first and second terminal regions separated by a substantially single layer gated graphene nanoconstriction. A local first gate region can be separated from the graphene nanoconstriction by a first gate dielectric. The local first gate region can be capacitively coupled to gate electrical conduction in the graphene nanoconstriction. A second gate region can be separated from the graphene nanoconstriction by a second gate dielectric. The second gate region can be capacitively coupled to provide a bias to a first location in the graphene nanoconstriction and to a second location outside of the graphene nanoconstriction. Methods of making and using locally gated graphene nanostructures are also described.

Abstract: A field-effect transistor device, including: a semiconductor heterostructure comprising, in a vertically stacked configuration, a semiconductor gate layer between semiconductor source and drain layers, the layers being separated by heterosteps; the gate layer having a thickness of less than about 100 Angstroms; and source, gate, and drain electrodes respectively coupled with said source, gate, and drain layers. Separation of the gate by heterosteps, rather than an oxide layer, has very substantial advantages.

Abstract: An isolation circuit is provided. The isolation circuit is coupled between a master circuit and a slave circuit for isolating or conducting an inter integrated circuit (I2C) signal. While the master circuit has electricity and the slave circuit does not, the isolation circuit isolates the master circuit to prevent the I2C signal being transmitted to the slave circuit. While the master circuit and the slave circuit have electricity, the isolation circuit conducts the master circuit to transmit the I2C signal to the slave circuit. The present invention solves the signal isolation problem between the master and slave circuits, and also improves the operational stability of an I2C bus.

Abstract: Semiconductor device with a controllable decoupling capacitor includes a decoupling capacitor connected between a power voltage terminal and a ground terminal and a switching unit configured to enable/disable the decoupling capacitor in response to a control signal. According to another aspect, a semiconductor device with a controllable decoupling capacitor includes multiple circuits, decoupling capacitors being connected in parallel to each of the circuits and switching units being configured to enable/disable the decoupling capacitors in response to control signals.

Abstract: A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes: An auxiliary inductor in series with the main switching FET for inducing an auxiliary inductive voltage proportional to di/dt. An auxiliary FET in parallel with the main switching FET. The auxiliary FET gate is connected to produce a gate voltage equal to the auxiliary inductive voltage. When the di/dt tends to exceed a pre-determined maximum rate of decrease, the auxiliary FET produces an auxiliary current component counteracting further decrease of the di/dt. The main switching FET and the auxiliary FET can be formed from a single die with shared source and drain. The auxiliary inductor can be implemented as a parasitic inductance of an inherently required bonding wire connecting the main switching FET to its device terminal to simplify packaging with reduced cost.

Abstract: A semiconductor device includes a substrate of semiconductor material. A source region, a drain region, and a conducting region of the semiconductor device are formed in the substrate and doped with a first type of impurities. The conducting region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state. A gate region is also formed in the substrate and doped with a second type of impurities. The gate region abuts a channel region of the conducting region. A stress layer is deposited on at least a portion of the conducting region. The stress layer applies a stress to the conducting region along a boundary of the conducting region that strains at least a portion of the conducting region.

Abstract: A current-limiting circuit for limiting rising of a current above a predetermined level. The circuit including forward- and reverse-conducting devices, each device including a MOS and a bipolar transistor, wherein ON-resistance of one of the devices is used instead of a current-sensing resistance for another of the devices; and a gate driver connected to the gates of the forward- and reverse-conducting devices for controlling the devices such that a channel of each of the devices simultaneously conducts a current.

Abstract: A power switch apparatus includes a substrate; a semiconductor die mounted on the substrate and including power electronics circuitry for a high power, alternating current motor application; gate drive circuitry mounted on the substrate and electrically coupled to the power electronics circuitry on the semiconductor die; and control circuitry mounted on the substrate and electrically coupled to the gate drive circuitry.

Abstract: Provided is a random number generating circuit having a simple circuit structure, for generating a physical random number based on a noise. The random number generating circuit includes a reference voltage section, an inverting amplifier section having a threshold voltage equal to a reference voltage level, and a semiconductor switch provided between an output terminal of the reference voltage section and an input terminal of the inverting amplifier section. A thermal noise produced from the reference voltage section is held by the semiconductor switch and a capacitor and amplified by the inverting amplifier section to generate the physical random number.

Abstract: A first transistor includes: a first terminal that receives one of differential input signals; a second terminal that receives a control signal for varying an impedance; a third terminal connected to the second transistor; and a fourth terminal that supplies a potential to a substrate. A second transistor includes: a fifth terminal that receives the other of the differential input signals; a sixth terminal that receives a control signal, the seventh terminal connected to the first transistor, and the eighth terminal that supplies a potential to a substrate. The third terminal, the fourth terminal, the seventh terminal, and the eighth terminal are connected together.

Abstract: An active load including a current source, a first resistive element, and a switch. The current source is configured to provide a bias current and the first resistive element is configured to receive the bias current and provide a bias voltage. The switch has an input and an output and is configured to receive a drive voltage at the input, receive the bias voltage between the input and the output, provide an output voltage at the output that is sufficiently different than the drive voltage to maintain headroom, and provide an inductive impedance that enhances circuit bandwidth.

Abstract: An active load arrangement is used to provide proper output load to an object TO under test. The arrangement Z comprises a voltage_controlled transistor MOSFET having a source S, a gate G and a drain D. The drain D is associated with the gate G and connected to an arrangement input I2 associated with an output O1 of the object under test. The source S is connected to an arrangement output O2 associated with an input I1 of the object under test. A feedback arrangement is connected to the source S and the gate G. The feedback arrangement changes phase and amplitude of the gate-to-source voltage by varying frequency in order to obtain low impedance at low frequencies and high impedance at high frequencies.

Abstract: A basic electronic circuit generates a magnitude. The circuit has certain structural characteristics and the magnitude undergoes variations in function of the structural characteristics of the circuit. The circuit comprises at least two circuit parts suitable for supplying respective fractions of the magnitude and the at least two circuit parts have different structural characteristics.

Abstract: A transistor control circuit (74) comprises a source-gated thin film transistor (70), an input for receiving a drive voltage representing a desired control of the source-gated transistor and a current source (82) for causing a known current to pass through the source-gated transistor (70). A first capacitor (78) stores a resulting gate-source voltage of the source-gated transistor when the known current is passed through the source-gated transistor The drive voltage is modified using the resulting gate-source voltage, and the modified voltage is used in the control of the source-gated transistor This control can provide a translational shift in the operating characteristics of the transistor, and it has been found that this can compensate for ageing of the transistor, for non-uniformity between different devices, and for temperature variations.

Abstract: A JFET transistor device configured to provide an amplitude estimate of a time varying input signal, and associated methods for using such a device, are disclosed. An exemplary JFET transistor device includes a gate region and a substrate (back gate, or the like), at least one of which is at a floating potential and the other of which is at a circuit common potential; and a channel region, connecting a source region and a drain region of the transistor device for receiving a time varying input signal at a first location and for producing an output signal related to amplitude of the time varying signal at a second location.

Abstract: With the aim of suppressing power consumption and reducing circuit size, a positive FET is turned on in accordance with a positive pulse signal and turned off when a return voltage rises up to a positive threshold. An active ground clamp circuit causes the output line to return to the ground voltage after the elapse of a predetermined period of time. A negative FET is turned on in accordance with a negative pulse signal and turned off when the return voltage falls down to a negative threshold. The active ground clamp circuit causes the output line to return to the ground voltage after the elapse of a predetermined period of time.

Abstract: A current conveyor circuit with improved power supply noise immunity. Additional biasing circuitry causes the nominal biasing potential applied to the output circuit to be increased, thereby producing a corresponding increase in the magnitude of noise voltage needed to appear on the power supply before the output signal becomes affected.

Abstract: An arrangement and a method for connecting a capacitor into a circuit and disconnecting it therefrom are disclosed. The capacitor includes two capacitor elements, each with a main terminal and an auxiliary terminal. The auxiliary terminals are connected to one another at a reference node to which a control signal can be coupled as a function of the desired capacitance value. The capacitance value is tapped at the main terminals of the capacitor elements. When the capacitor is switched on, a high quality level is obtained, and when the capacitor is switched off, low parasitic capacitance components are obtained. For this reason the described arrangement is particularly suitable for use in voltage-controlled oscillators.

Abstract: A cascode circuit with improved withstand voltage is provided. The cascode circuit includes three or more transistors, such as MOSFET transistors. Each transistor has a control terminal, such as a gate, and two conduction terminals, such as a drain and a source. The conduction terminals are coupled in series between two output terminals, such as where the drain of each transistor is coupled to the source of another transistor. A signal input is provided to the gate for the first transistor. Two or more control voltage sources, such as DC bias voltages, are provided to the gate of the remaining transistors. The DC bias voltages are selected so as to maintain the voltage across each transistor to a level below a breakdown voltage level.

Abstract: A method for detecting a null current condition in a PWM driven inductor connected between a voltage source node and a second circuit node of a line for outputting current to a load includes generating a derivative signal by time differentiating a voltage on the second node. The method further includes monitoring an instant when the derivative signal becomes negative, and signaling verification of the null current condition each time the derivative signal becomes negative.

Abstract: According to an embodiment of the present invention, a capacitor comprising field effect transistors and a bias transistor.

Abstract: A voltage reference generation circuit is disclosed including a voltage reference generating stage and a voltage reference output stage, in which a depletion-mode MOS transistor and an enhancement-mode MOS transistor are connected in series, and the junction formed between these MOS transistors serves as an output terminal for outputting a voltage to be input to the voltage reference output stage. In the output stage, two enhancement-mode MOS transistors having the same channel dopant profile are connected in series between a power source and the ground, the gate of one MOS transistor is connected to the output terminal of the generating stage, the gate and drain of the other MOS transistor are interconnected, and the junction formed between these MOS transistors serves as an output terminal for a voltage reference.

Abstract: A circuit configuration for providing a capacitance includes short-channel MOS transistors that are reverse-connected in series or in parallel, and that have the same channel type. When the short-channel MOS transistors are operated exclusively in the depletion mode in the required voltage range, the useful capacitance is increased, because of intrinsic capacitances, as compared with circuit configurations having conventional long-channel MOS transistors. These circuits greatly reduce the area taken up and reduce the costs.

Abstract: The present invention relates to a circuitry for detecting the power of a RF signal (7) comprising a FET transistor (1) connected in parallel to two inputs (2, 2′) for supplying the RF signal and two outputs (13, 13′) for detecting the power of the RF signal (7). The circuitry has a resistor (9) having a resistance larger than the drain-source resistance of the FET transistor (1). This resistor (9) is connected between one of the outputs and the source (14) of the FET transistor (19. Further a capacitor (10) is connected between one of the input and the source of the FET transistor. The gate (8) of the FET transistor is connected to ground.

Abstract: A switching circuit device has a first FET and a second FET, and operates with single control terminal. The device also has a common input terminal connected to the drain or source electrode of the two FETs, a first output terminal and a second output terminal connected to the source or the drain electrode of the respective FET, a bias element applying an bias to the first output terminal, a first connection connecting the control terminal to the second FET, a second connection connecting the gate of the second FET to the ground, and a direct current isolation element placed between the two FETs. The device is housed in a MCP6 package with six pins.

Abstract: A novel gate driver apparatus in which an energy recovery circuitry is incorporated in a square-wave gate driver. The energy recovery circuitry has a first loop circuit for discharging the energy from the gate capacitor to an inductor when the gate driver is turned off, and a second loop circuit for discharging the energy from the inductor to the power supply. Thus, the energy of the gate capacitor is transferred to the power source when the gate driver is turned off, and the gate driver apparatus still maintains its operating flexibility as the square-wave driver and is independent of switching frequency.

Abstract: A circuit design of a transistor connected as a diode, in particular to a design able to reduce the threshold voltage of the transistor and equal to the difference of the threshold voltage of the used transistors in the circuit disposal. The circuit design includes a first pMOS transistor having a second nMOS transistor connected as a diode connected between the gate and the drain of the first transistor and a current generator connected to the gates of the two transistors. Such a circuit design is also applicable to a nMOS transistor. From a general point of view the invention is directed to a nMOS or pMOS transistor whose gate voltage is increased (for the nMOS transistors) or decreased (for the pMOS transistors) by using a circuit in series with the gate that provides an appropriate delta of voltage.

Abstract: Large output driver transistors are used to shunt electro-static-discharge (ESD) pulses. ESD pulses are capacitivly coupled to the gates of the large driver transistors by R-C networks. The capacitive coupling causes a gate-to-source voltage to exceed the transistor threshold, turning on the large driver transistor to shunt the ESD current. Transistor switches are inserted into the R-C networks. These transistor switches disconnect the R-C networks during normal operation, and ensure that the R-C networks couple the I/O pad to the gates of the output driver transistors only when power is turned off. Since ESD events normally occur when power is disconnected, such as during handling by a person or machine, the ESD protection is only needed when power is off. Thus an active ESD-protection device can be disabled during normal powered operation of the IC. A feedback circuit detects power and biases the gates of the transistor switches.

Abstract: A voltage drop DC-DC converter includes a switch circuit including a plurality of switches for alternately connecting a first and second capacitors in series and in parallel in response to an output signal of an oscillator circuit oscillating at a constant frequency. An efficient voltage dropping conversion is possible by deriving a voltage divided by the first and second capacitors when the first and second capacitors are connected in series and deriving terminal voltages of the first and second capacitors when the first and second capacitors are connected in parallel. When the derived voltage is increased beyond an aimed reference output voltage, the oscillation of the oscillator circuit is stopped.

Abstract: A circuit arrangement for generating an electronically controlled electrical resistance by apparatus of at least one MOS transistor. A source-drain junction of the MOS transistor is used for the generation of the electrical resistance between a first and a second terminal, in order to optimize the linearity of the electrical resistance, there have been provided means for generating a bulk signal, which apparatus generate from the voltage on that terminal of the circuit arrangement which is coupled to the source electrode of an associated MOS transistor a signal for driving a bulk electrode of the associated MOS transistor, which signal is generated from the voltage on the terminal and an additionally superposed direct voltage of such a polarity that, depending on the doping type of the MOS transistor the formation of a diode between the source and bulk regions of this MOS transistor is avoided.

Abstract: Non linear circuit for open load control in Low-Side Driver type circuits, including at least two power transistors, scaled according to an area ratio 1 to M, with M>1, wherein the power transistor having the smaller area is controlled by a circuit input signal while the transistor having the larger area is controlled by an output value of an AND type logic gate, managed by a control circuit, that is regulated by the output value of a voltage sensor, placed in parallel with the power transistor having the larger area, and by the output value of a current sensor, placed in series with the power transistor having the smaller area, so that, when a current flowing in the power transistor having the smaller area is less than a predetermined value of the threshold current, the control circuit signals the open load on an output pin.

Abstract: A process and an integrated circuit are intended for obtaining an adjustable electrical resistance, in which a first voltage is applied to an integrated MOS transistor on its source, its gate and its substrate, and a second voltage is applied on its drain, the first and second voltages being able to initiate a breakdown of the MOS transistor by: avalanche of the drain/substrate junction; biasing of the parasitic bipolar transistor of the MOS transistor; irreversible breakdown of the drain/substrate junction; and shorting between the drain and the source.

Abstract: A constant gate drive metal-oxide semiconductor ("MOS") analog switch. In one embodiment, the analog switch includes first, second, and third devices, and a level shifter. The first device includes a source coupled to an input terminal, a drain coupled to an output terminal, and a gate. The second device includes a source coupled to the input terminal, a drain, and a gate. The third device includes a source coupled to the drain of the second device, a drain coupled to the output terminal, and a gate. The level shifter includes an input coupled to the drain of the second device and an output coupled to the gates of the first, second, and third devices. The level shifter provides a constant gate drive to the first device, regardless of a signal on the input terminal, resulting in a constant on-resistance of the analog switch. In addition, a constant linearity of on-resistance is achieved by keeping the gate voltage constant with respect to the mid-point of the source and drain voltages.

Abstract: A circuit for providing unity gain buffering of an input signal with reduced power consumption and symmetrical load driving capability. A feedback circuit between a buffer transistor and a bias circuit modulates the bias current to the buffer transistor. Modulating the bias current allows the buffer circuit to have a smaller quiescent bias current and increased current sink capability than the prior art unity gain buffer circuit. The modulating bias current allows more efficient operation of the buffer circuit while maintaining symmetrical load driving capability.

Abstract: An N-channel power MOSFET includes a storage capacitor and a pair of diodes connected between the gate and drain terminals, respectively, and the capacitor. Since at any given time the voltage at either the drain or the gate of the MOSFET is high, a charge is maintained on the storage capacitor as the MOSFET is switched on and off. The charge stored on the capacitor yields an output voltage which may be used to power a gate drive circuit or other components within or outside the MOSFET.

Abstract: Two FET transistors provide an electrical circuit characterized by a stable capacitance across a wide range of input voltages and temperture fluctuations. Additionally, the transistors provide a capacitive compensation circuit which stabilizes the output voltage of a band-gap reference circuit. The compensation circuit encompasses the electrical connecting of a PFET capacitor across the terminals of an NFET capacitor (preferably a low threshold voltage NFET), wherein the gate of the of the NFET capacitor is directly connected to an input lead, the substrate is grounded, and the source and drain are directly connected to a common output lead. The PFET is also directly connected to the the input lead and the output lead, however, instead of the substrate being grounded, the substrate of the PFET is electrically connected to the common output lead.

Abstract: An N-channel power MOSFET is fabricated with its source and body connected together and biased at a positive voltage with respect to its drain. The gate is controlled by a switch which alternately connects the gate to the source or to a voltage which turns the channel of the MOSFET fully on. When the gate is connected to the source, the device functions as a "pseudo-Schottky" diode which turns on at a lower voltage and provides a lower-resistance path than a conventional PN diode. When the gate is connected to the positive voltage the channel of the MOSFET is turned fully on. This MOSFET switch is particularly suitable for as a synchronous rectifier in a power converter where it reduces the power loss and stored charge in the "break before make" interval (i.e., the interval between the turn-off of the shunt switch and the turn-on of the synchronous rectifier).

Abstract: A structure is provided to create a voltage-independent capacitive structure using a typical MOS fabrication process. The capacitive structure includes two FET devices connected in series by having their source, drain, and body terminals all coupled together into a common node. A biasing circuit that includes a current generator and a current mirror biases the common node so that a constant capacitance is maintained across the gate terminals of the two serially connected FET devices, independent of the applied voltage.

Abstract: An apparatus comprising an electrical device having a first connection terminal, a second connection terminal and a holder for holding a voltage source having two voltage-source terminals. The holder has a first contact, a second contact and a third contact for cooperation with the voltage-source terminals. Via these contacts the first connection terminal is connectable to one voltage-source terminal and the second connection terminal is connectable to the other voltage-source terminal. The holder is adapted to allow the first contact, the second contact and the third contact to engage simultaneously with the voltage-source terminals. When the voltage source is present the first contact and one of the two other contacts are in engagement with one of the voltage-source terminals, and the other contact, which is not in engagement with the first voltage-source terminal, is in engagement with the second voltage-source terminal.

Abstract: A field-effect transistor has a covering electrode overlying at least part of the transistor's channel. The covering electrode is formed on an insulating layer that covers the source, gate, and drain of the transistor. One voltage is applied to the covering electrode when the field-effect transistor is switched on. Another voltage is applied when the field-effect transistor is switched off, creating an electric field that hinders current flow in the channel. In an antenna switch, this type of transistor couples an antenna to a receiving circuit, and another transistor couples the antenna to a transmitting circuit.

Abstract: An integrated semiconductor circuit comprising an output terminal connected to a ground terminal via a series connection of a first switching transistor and a second switching transistor of inverse polarization with respect to the latter, each of said switching transistors having parasitic transistors. Whether the second semiconductor switch means is conducting or not, is dependent on the current flow through a resistor connected between gate and source of the second semiconductor switch means. Whether current flows through this resistor, is dependent on the switching condition of a further switching transistor, which in turn is also determined by the output signal of a comparator circuit by means of which a potential corresponding to the potential present at output terminal is compared to a reference potential.

Abstract: A charge amplifier with DC offset cancelling for use in a pixel element of an MOS image sensor is disclosed. The charge amplifier can be manufactured using a standard CMOS single polycrystalline process, making it much more cost effective than prior art designs. The charge amplifier includes an operational amplifier, a source capacitor, a series capacitor, and a feedback capacitor. The source capacitor holds the input signal. The output of the operational amplifier provides the output signal. Switches control the routing of the signal flow from the source capacitor, the series capacitor, and the feedback capacitor.

Abstract: An N-channel power MOSFET is fabricated with its source and body connected together and biased at a positive voltage with respect to its drain. The gate is controlled by a switch which alternately connects the gate to the source or to a voltage which turns the channel of the MOSFET fully on. When the gate is connected to the source, the device functions as a "pseudo-Schottky" diode which turns on at a lower voltage and provides a lower-resistance path than a conventional PN diode. When the gate is connected to the positive voltage the channel of the MOSFET is turned fully on. This MOSFET switch is particularly suitable for use as a synchronous rectifier in a power converter where it reduces the power loss and stored charge in the "break before make" interval (i.e., the interval between the turn-off of the shunt switch and the turn-on of the synchronous rectifier).

Abstract: A monolithic CMOSFET integrated circuit which includes a first MOSFET integrant transistor having a gate area chosen to provide a desired range of resistance when operated in its triode region which constitutes (i) a preamplifier, (ii) a voltage controlled resistance (VCR) device, and (iii) a high-pass filter when capacitive with a transducer. Preferred operating characteristics are achieved by including an active CMOSFET linearization network including a pair of second and third integrant MOSFET transistors having only one-hundredth (1/100th) to one-tenth (1/10th) the gate area of the first transistor. The present invention operates with a reduction in distortion resulting from the filtering effect of the combined capacitive reactance of the sensor and the resistance of the resistor.

Abstract: An N-channel power MOSFET includes a storage capacitor and a pair of diodes connected between the gate and drain terminals, respectively, and the capacitor. Since at any given time the voltage at either the drain or the gate of the MOSFET is high, a charge is maintained on the storage capacitor as the MOSFET is switched on and off. The charge stored on the capacitor yields an output voltage which may be used to power a gate drive circuit or other components within or outside the MOSFET.

Abstract: A method and an apparatus for providing an adjustable floating capacitance between a first node and a second node in an integrated circuit. First and second transistors having commonly coupled gates are coupled between the input and output nodes of a digitally-adjustable floating MOS capacitor. The source and drain of the first transistor are coupled to the input node, while the source and drain of the second transistor are coupled to the output node. A switch responsive to an enable signal is coupled to the gates of the first and second transistors. In response to the enable signal, the switch alternatively couples the gates of the first and second transistors to either a first potential or a second potential. When the gates of the first and second transistors are coupled to the first potential, a first capacitance is realized between the input and output nodes.

Abstract: In a microcircuit device such as a memory chip, where a bank of state devices such as fuses and anti-fuses determine the enabling and disabling of redundant circuitry, a scheme for blowing one or more state devices by applying a programing voltage through a switching circuit comprising thin film transistors (TFTs) which are not damaged by the device blowing, programming voltage. The TFTs can be activated by a low voltage enable signal provided by a state device designator logic module.

Abstract: A BIFET vacuum tube replacement structure includes a plurality of devices that replicate the characteristics of a vacuum tube. The vacuum tube replacement structure has the same pin-out as the vacuum tube being replaced and so can be exchanged directly for a vacuum tube in an audio amplifier. The vacuum tube replacement structure is suitable for use in a wide range of audio amplifier applications without modification to the audio amplifiers. Further, there is no noticeable degradation to the human ear in the sound quality when the vacuum tube replacement structure is used in an audio amplifier in place of a vacuum tube. A unitary device that is a combination of a high impedance bipolar like transistor and a unipolar junction field effect transistor, that is referred to as a BIFET, is used in the vacuum tube replacement structure. In one embodiment, the bipolar like transistor is formed in combination with the gate of the unipolar junction field effect transistor.

Abstract: In an atomic switch, opposite ends of an atom wire are connected to an input and output, and a switching gate is connected to a switching power supply. An input signal is outputted when a switching atom is connected to the atom wire, whereas an input signal is not outputted when the switching atom is moved to disconnect from the atom wire. There are provided an atom wire having a plurality of atoms arranged in a line or in a plurality of lines, in a ring shape, or in a curved line, and a switching gate made of an atom wire. The atom wire is switched by the field effect of the switching gate.

Abstract: In a microcircuit device such as a memory chip, where a bank of state devices such as fuses and anti-fuses determine the enabling and disabling of redundant circuitry, a scheme for blowing one or more state devices by applying a programming voltage through a switching circuit comprising thin film transistors (TFTs) which are not damaged by the device blowing, programming voltage. The TFTs can be activated by a low voltage enable signal provided by a state device designator logic module.