Abstract: A method and apparatus for rapidly measuring chemical properties of a solution using a plurality of devices having relatively long thermal time constants selectively coupled to a control means. Current I.sub.d flows through only one device at a time. A timing logic control circuit controls the timing of the drain switch and, if present, the reference switch. The output of the multiplexing circuit is sampled a precise amount of time after each device begins conducting current. The temperature at the sample time is a constant. The characteristics of the solution in which the device is immersed is the only variable in the operation of the device (i.e., I.sub.d, and V.sub.ds are held constant). By sampling the output a predetermined amount of time after the device has been turned on, the temperature rise is controlled.

Abstract: An analog isolation circuit for providing electrical isolation between interrelated electrical circuitry contained within a vortex flowmeter. The circuit provides a low power and low cost solution to the problem of ground isolation presented in flowmeters utilizing grounded sensors which generate low frequency sinusoidal signals. A pair of clock-controlled analog switches couples the voltage difference between two successive samples of an analog signal across an isolation barrier. The operation of the switches at a low frequency rate and with a short sampling interval while utilizing a low magnetizing current preserves the magnitude of the input waveform while consuming approximately 1 mW of power.

Abstract: A sample circuit (10) maintains linear operation over frequency. A switchable diode bridge (12) passes the analog input signal when enabled to one terminal of a sample storage capacitor (14). The second terminal of the capacitor is coupled through a closed FET switch (16) to a reference node (18). Once the analog input signal is stored across the capacitor, the FET switch opens before the diode bridge disables. When the second terminal of the capacitor floats and prevents any further charge from altering the sample voltage across the capacitor. When the diode bridge is disabled, the sample voltage across the capacitor does not change. The sample voltage may be amplified and digitized for further processing in the cellular system.

Abstract: Switch circuits 21 and 22 are opened before switch circuits 31 and 32 are opened so that clock field through-noises inputted from the switch circuits 31 and 32 are not inputted to a differential amplifier circuit, and also switch circuits 11, 12, 51 and 52 are closed immediately before a comparison operation is started by the switch circuit 21 and 22 so that the differential amplifier circuit remains balanced, thereby to realize a high-speed comparator circuit.

Abstract: A signal conditioning apparatus useful in applications, such as automotive applications, having a signal conditioning circuit capable of conditioning a sensor input signal and providing an output useful, for example, to a fuel-air mixture control system. The signal conditioning circuit employs an amplifier with a feedback impedance, NMOS and PMOS transistors, an input impedance, a detection impedance, input terminals coupled to a sensor. The sensor, such as an oxygen sensor, has a sensor output referenced to sensor ground and input terminals coupled to a power supply and power supply ground. The signal conditioning circuit utilizes switched impedances to provide an output voltage proportional to the differential voltage between the sensor output voltage and the sensor ground when an impedance between the signal conditioning circuit input terminals is low relative to the detection impedance.

Abstract: In a sampling circuit including a first main terminal (P) and a series coupling of a hold capacitor (C2) and a sampling switch (S2) between the first main terminal (P) and a second main terminal (E), a parallel circuit (L2, R4) of a coil and a resistor (L2) is coupled in series with the sampling switch (S2) and the hold capacitor (C2), whereby the combination of the coil (L2), the resistor (R4) and the hold capacitor (C2) generate an excitation within a time period in which the sampling switch (S2) is conductive.

Abstract: A chopper type comparator is disclosed and implements a differential configuration with inverter amplifiers each having a control terminal. The comparator, therefore, successfully cancels noise of the same phase while preventing a current from constantly flowing therethrough. The cancellation of noise of the same phase, coupled with differential signals, doubles the signal range in the same voltage range, compared to a single end configuration. Hence, a high resolution is achievable even when a power source voltage is low.

Abstract: An electronic switch for sampling a signal. A small switch is placed in parallel with a large switch. The large switch is opened first. Any residual charge from the large switch is compensated by a low impedance path through the small switch. Speed is maximized by providing high current capacity through the large switch. Noise is minimized by leaving only residual charge from the small switch. Example embodiments are provided for sampling both voltage and current signals.

Abstract: A sampling circuit is not susceptible to an influence of structural components and environmental changes. A phase difference detecting circuit (5) detects a deviation of a sampling clock (.phi.2) from optimal sampling timing and outputs a phase difference signal. On the other hand, a phase reference signal (ORG) which is used as a reference to determine a phase advance and a phase lag is generated by a phase reference detecting circuit (4). In accordance with these signals, a sampling clock shifting circuit (2) shifts the sampling clock (.phi.2) so that the sampling clock (.phi.2) is activated at optimal sampling timing. Sampling is performed in accordance with such a sampling clock (.phi.2), whereby a basic signal is generated from which the phase reference signal (ORG) and the phase difference signal (i.e., an equivalent signal (EQU) and a non-equivalent signal (UPDN)) are generated. By means of feedback control, the sampling clock is automatically activated at optimal sampling timing.

Abstract: A sample and hold circuit has an analog switch, a hold capacitor, a voltage-follower type operational amplifier, and a ringing cancel circuit. The ringing cancel circuit is interposed between a non-inverted input terminal of the operational amplifier and a signal ground so that the ringing cancel circuit is connected in parallel with the hold capacitor. The ringing cancel circuit is made up of a resistance and a capacitor connected in series with each other. With this arrangement, a high-speed, highly accurate, low power consumptive sample and hold circuit can be realized.

Abstract: A differential track and hold amplifier circuit (200) is provided. The track and hold amplifier includes an input transconductance amplifier (212), an output amplifier (111), and a second transconductance amplifier (214). The track and hold circuit further includes a switching circuit (108) for coupling the output of the input transconductance amplifier to a capacitor (110) in the output stage of the track and hold circuit during track mode, and for decoupling the capacitor from the input amplifier during hold mode. The track and hold circuit further includes a subtractor circuit (103) for reducing a common mode voltage of the output of the input transconductance amplifier, thereby maintaining a stable voltage across the capacitor during hold mode. Further, during hold mode, the second transconductance amplifier acts in a negative feedback configuration to reduce the gain of the input amplifier to attenuate its output signal.

Abstract: The subject of the invention is a differential sampler circuit including a voltage/current converter (1) having two differential inputs (E1a, E1b) and two outputs (S1a, S1b). According to the invention, each of these outputs is linked via an input multiplexer module (2a) to two interposed track-and-hold modules (5a, 6a), in such a way that at any instant one of the track-and-hold modules (5a, 6a) operates in track mode whereas the other (6a, 5a) operates in hold mode. These two modules (5a, 6a) are linked to the output (S4a) of the sampler circuit via an output multiplexer module (7a). This structure makes it possible to double the sampling frequency without increasing the intrinsic speed of the circuit. Each track-and-hold module (5a, 6a) includes an input load (10a, 11a) linked in parallel with a capacitor (C18a, C19a), an output emitter-follower transistor (T20a, T21a), and a switching cell (5-6a). Thus, the high-frequency performance of the circuit is improved.

Abstract: In a comparator including a first differential amplifier stage for amplifying the difference in potential between input signals, a second differential amplifier stage for amplifying the difference in potential between output signals of the first differential amplifier stage, and a latch stage for positively feeding output signals of the second amplifier stage back thereto, a first differential switch circuit alternately activates the second differential amplifier stage and the latch stage, and a second differential switch circuit alternately activates the first differential amplifier stage and the latch stage.

Abstract: Method and apparatus for sampling an electrical signal in order to obtain at least one signal weighted together from two or more samples, in which in a first step the electrical signal is connected to a number of capacitors connected in parallel. In a second step, one capacitor is disconnected from the electrical signal at each time of sampling and in a third step, when the sampling is completed, the capacitors are connected together. In this manner, one or more signals weighted together are generated in dependence of the charge of the capacitors when they are disconnected from the electrical signal and of the capacitances of the capacitors.

Abstract: Offset-compensated sample and hold arrangement to sample an input signal comprising at least an operational amplifier (A), a first capacitor (C1), a second capacitor (C2), a first switch (S110), a second switch (S211), a third switch (S210), a fourth switch (S111), a fifth switch (S120), a sixth switch (S121), a seventh switch (S220) and an eighth switch (S221), which switches capacitors and operational amplifier are interconnected in such a way and may be switched in such a way that during an offset-compensation phase the output voltage will only experience a very small voltage change.

Abstract: A sampling circuit which obtains a level of sampled-and-held signal which is determined with respect to a well-determined reference level V0, even though the input signal is a useful signal referenced with respect to a low-stability reference level. This is the case in particular for sampling of signals derived from charge-transfer photosensitive devices for which the dark level can vary. The circuit includes a sample-and-hold device (EB1) and an input via a capacitor (C1), with a reset circuit which periodically charges the capacitor (C1) to a value which is roughly the difference between the (variable) input reference level and the (fixed) output reference level. According to the invention, it is provided that the reset circuit comprises a looped amplifier (AD1) in which the loop (B1, EB2, B2) is designed to introduce a voltage level shift equal to the shift introduced intrinsically by the sample-and-hold device (B1, EB1, B2).

Abstract: An latch circuit includes an input line receiving electrical signals from a bus, a latch for conducting electrical signals from the precharged bus to a receiving circuit, and a structure for enabling the latch only when data is driven onto the bus.

Abstract: A constant impedance sampling switch suitable for a high-frequency analog-to-digital converter, presents a substantially constant impedance to the input signal regardless of the instantaneous level of the input signal. The exemplary sampling switch employs a single metal oxide semiconductor (MOS) transistor to selectively couple the input signal to a sampling circuit. The gate signal for this transistor is generated by circuitry which is disconnected from the gate of the transistor while the transistor is in an non-conductive state. During a sampling interval, the gate signal is boot-strapped by the instantaneous potential of the input signal to render the transistor conductive. Accordingly, the potential difference between the signal being sampled and the gate potential of the transistor remains substantially constant over a relatively wide range of amplitudes for the analog input signal.

Abstract: A low voltage AC electric power monitoring system includes a processor which samples the current and circuit breaker system includes a processor which samples each of the current components at seventeen samples per cycle to obtain current samples representing a single period of the AC power signal. The processor samples the voltage component at different points in the voltage cycle over several cycles to obtain voltage samples representing a single period of the AC power signal.

Abstract: A sample and hold circuit to reduce hold error when analog data is held and transferred. The circuit includes a plurality of capacitors and inverters for guaranteeing level, selectively holds an input voltage at one capacitor by a first switching means, transfers charged voltage to a second capacitance by a second switching means and reduces data transfer time.

Abstract: A method and apparatus are provided for translating small voltage continuous signals into large full supply signals to generate a clock signal. At least one oscillator input signal is applied to a first amplifier stage for generating an amplified voltage output signal. A first inverter is coupled to the first amplifier stage. A second inverter is coupled to the first inverter. An AC coupling capacitor couples the amplified voltage output signal to the first inverter input, and a feedback resistor is connected between the output and input of the first inverter.

Abstract: A digital data detector samples a signal at twice the data rate and calculates a phase interval from a zero crossing point to the current sampling point. The phase of the current sampling point is predicted based on the phase of a sampling point located before the current sampling point, the phase of a sampling point located at least two points before the current sampling point, and a zero crossing detection signal. A predicted error is calculated between a calculated phase interval and a predicted current phase. The frequency band of the predicted error is limited, and the phase of the current sampling point is calculated according to the band-limited predicted error, the predicted current phase, and the zero crossing detection signal. A data detection clock is detected in synchronization with a received digital data according to the calculated phase of each sampling point. A digital data value is detected using the phase interval, the calculated current phase, and sampling data.

Abstract: A voltage track and hold circuit operates to track a tuning voltage and holding the tuning voltage (404) as a reference voltage (408). In the track mode, the track and hold circuit includes a first operational transconductance amplifier (401) and a first charge storage device (402) coupled to a first input (403) of the first operational transconductance amplifier (401). The first charge storage device (402) accumulates a charge that corresponds with the tuning voltage (404). A second charge storage device (405) is coupled to a second input (406) and an output (407) of the first operational transconductance amplifier (401). The second charge storage device (405) accumulates a reference charge such that the reference voltage (408) present at the second charge storage device (405) is substantially equivalent to the tuning voltage (404).

Abstract: A sample-and-hold circuit device capable of realizing a high-precision and high-speed operation, in which the output signal is independent of the error signal caused by a MOS transistor. The circuit includes a first switch coupled between an input terminal and a first internal terminal, a second switch coupled between the first internal terminal and a second internal terminal, a capacitor coupled between the second internal terminal and a reference potential, a buffer for transferring a potential held in the capacitor to an output terminal, a control signal generator for controlling the first switch to turn off after the second switch is turned off, and then to again turn on the second switch so as to replace an error charge into the second switch.

Abstract: A high speed sampling demultiplexer based on a plurality of sampler banks, each bank comprising a sample transmission line for transmitting an input signal, a strobe transmission line for transmitting a strobe signal, and a plurality of sampling gates at respective positions along the sample transmission line for sampling the input signal in response to the strobe signal. Strobe control circuitry is coupled to the plurality of banks, and supplies a sequence of bank strobe signals to the strobe transmission lines in each of the plurality of banks, and includes circuits for controlling the timing of the bank strobe signals among the banks of samplers. Input circuitry is included for supplying the input signal to be sampled to the plurality of sample transmission lines in the respective banks. The strobe control circuitry can repetitively strobe the plurality of banks of samplers such that the banks of samplers are cycled to create a long sample length.

Abstract: A circuit which can be used to hold either the maximum or minimum voltage applied. A comparator compares the input voltage to the previous high or low and a set of two mirror circuits either charge or discharge a holding copacitor to the new value. A control circuit of transistor switches configures the circuit into either a maximum or minimum holding mode.

Abstract: A track and hold circuit is disclosed which may be used in high speed analog to digital conversions. The circuit includes a control transistor which keeps the circuit's input transistor in a conductive state even when the circuit is in hold mode. As a result, the track and hold circuit achieves a high switching speed while minimizing input voltage spikes.

Abstract: A discrete-time signal processing system includes a signal sampling circuit controlled by a sampling signal generator in which a clock signal is derived from an oscillation signal having a higher frequency by means of a switchable frequency divider which is driven by a sigma-delta modulator. By alternately switching from one dividend n to the other dividend n+1 and vice versa, an effective dividend m, where n.ltoreq.m.ltoreq.n+1, is realized, so that a very fine frequency tuning can take place. The use of the .SIGMA.-.DELTA. modulator is advantageous in that the frequency spectrum of the sampled signal is not corrupted by the frequency spectrum of the sampling signal (clock signal) generated by way of the switching frequency divider.

Abstract: An analog signal processing circuit used to suppress unipolar transient effects and signal averaging. Two transistors and one capacitor are provided in series to sample and condition an input signal. An additional transistor is provided in parallel to the capacitor to provide further signal processing capabilities. The circuit can function as an analog signal average, suppressing unipolar transient effects and as a peak detector while using a conservative amount of fabrication material and can be operated with low power.

Abstract: A sampling frequency converter capable of obtaining data sampled by sampled pulses having a sampling frequency of 2-, 4-, or 8-fold of 44.1 kHz without using an over-sampling filter. Input data sampled by sampling pulses having a sampling frequency of 32 kHz is over-sampled by a 3-fold by a first over-sampling filter, and down-sampled by a one-2nd-fold by a first down-sampling filter. One of input data sampled by sampling pulses having a sampling frequency of 48 kHz and the output of the first down-sampling filter is selected by a first selector. The output of the selector is over-sampled by a 147-fold by a second over-sampling filter, and down-sampled by a one-20th-fold by a second down-sampling filter. The output of the second down-sampling filter is down-sampled by one-2nd-, one-4th-, and one-8th-folds respectively by third, fourth, and fifth down-sampling filters. One of the outputs of the second to fifth down-sampling filters is selected by a second selector.

Abstract: The present invention relates to a comparator circuit which is arranged such that detected data signal is waveform-shaped without producing any bit error, so that the data signal as transmitted can be accurately demodulated. Reference voltage V.sub.RE of the comparator which is compared with the data signal V.sub.IN is provided by adding output resulting from integration of the data signal V.sub.IN and integrated output of an inverter 2 which inverts output of the comparator 1. The reference voltage V.sub.RE of the comparator 1 can always be located at the center between the high level and the low level of the data signal V.sub.IN despite variations in DC voltage level of the data signal V.sub.IN.

Abstract: The present invention is a closed loop peak detection circuit comprising switching means, comparing means, control means, two current sources, and a holding capacitor. The switching means selectively provides one of a plurality of input signals to the comparing means. The control means is coupled to the comparing means. The control means receives first and second control signals for selecting one of three modes: reset, peak detect, and hold. First and second current sources are coupled to the control means. A capacitor is coupled to the first and second current sources for generating an output signal. The output signal is feedback coupled to the comparing means. The comparing means determines when one of the plurality of input signals exceeds the output signal. The control means enables and disables the current sources in response to the comparing means and to the first and second control signals.

Abstract: An improved back gate switched sample and hold circuit includes a sample and hold channel including a sample switch having a back gate and a storage element; a back gate circuit for controlling the back gate of the sample switch; and a first attenuator circuit for scaling the input signal from a low impedance source for delivery to the sample switch and a second attenuator circuit responsive to the input signal from the low impedance source to independently drive the back gate circuit and isolate any distortion of the input signal in the back gate circuit from affecting the input signal in said sample and hold channel.

Abstract: Each of the remote high speed circuits of a digital system is provided with a sync pulse generation circuit for generating periodic sync pulses with a predetermined periodicity using a control value. Additionally, each of the remote high speed circuits is further provided with a sampling circuit for sampling the sync pulse generation control value, a comparison circuit for determining whether each of the sampled sync pulse generation control values are consistent, and an adjustment circuit for adjusting the sync pulse generation control value of the particular remote high speed circuit. Furthermore, a sync pulse generation coordinator comprising a clock selection circuit, a delay line, a delayed clock selection circuit, and a coordination pulse generation circuit is provided to the digital system for generating periodic coordination pulses. The periodic coordination pulses are used to control the sampling and comparison.

Abstract: A sample-and-hold circuit, capable of charging and discharging its holding capacitor quickly regardless of a voltage of an analog input signal and an output impedance of an analog driving source, includes a pre-sampling capacitor and at least one CMOS inverter. Before the holding capacitor holds the sampled signal, the pre-sampling capacitor stores the signal level of the analog input signal, and then the CMOS inverter charges and discharges the one side of the holding capacitor according to the stored voltage in the pre-sampling capacitor. Since the one side of the holding capacitor is charged and discharged by the CMOS inverter thus controlled, the sample-and-hold circuit can operate with high speed and handle a wide range of the analog input signal.

Abstract: A hold circuit has a purpose to provide a hold circuit capable of controlling a hold error of an analog hold in the minimum during transferring. A hold circuit keeps a voltage signal, whose voltage level is compensated by operational amplifiers Amp.sub.1 and Amp.sub.2, at capacitances C.sub.1 and C.sub.2 by two steps, and holding and transferring of voltage data is performed at the different timing. The accuracy is compensated, as well.

Abstract: An apparatus and method for receiving a continuous time pulse amplitude-modulated passband signal is disclosed. The pulse amplitude modulated signal is periodically sampled by a local clock to generate received samples. A convolution of the received samples and an impulse response function is evaluated at a particular value of a phase difference variable to derive corrected samples. Using a narrow transmission band filter, a periodic signal is derived from the corrected samples. The periodic signal has a period equal to a symbol period of the pulse-amplitude modulated signal. Successive samples in each period of the periodic signal are compared to determine if the corrected samples lag or are ahead of optimal samples. If the corrected samples lag or are ahead of the optimal samples, the phase difference variable used to evaluate the convolution is varied by a fixed discrete stepsize.

Abstract: Apparatus for generating a phase startable clock signal, comprises an oscillator for providing a continuous sinusoidal input signal, a control signal source for providing a control input signal having a transition between a first state and a second state at a selected time during the signal epoch of the sinusoidal input signal, and a phase splitter, track and holds, multipliers and a summation device for operating on the sinusoidal input signal with the control input signal to produce a sinusoidal output signal commencing with a predetermined phase at a predetermined time relative to the transition.

Abstract: In an autozero type MOSFET comparator, the spurious current induced by the high frequency input voltage can flow through the resistance of the reset switch to introduce an offset voltage error during the autozero mode. A canceler is used to prevent the spurious current from flowing through the reset switch. A T-network with two series capacitors and a shunt switch is used as the canceler. The spurious current is by-passed by the shunt switch and prevented from flowing through the reset switch placed at the output of the T-network.The spurious current canceler is particularly useful for a sub-ranging ADC, where the comparator is used also as a sample-and-hold circuit to hold the input voltage across the series capacitors by opening all the sampling switches, the reset switch and the shunt switch.

Abstract: An integrating circuit is formed in the present invention, of which the active element is a pair of bipolar transistors (T5/T6) or a CMOS transistor (T8) which with the aid of switches (s81 to s88) controls the storing of a sample charge from the signal voltage (Us) in a sampling capacitor (Ci) and the discharging of the sample into an integrating capacitor (Co). The circuit only consumes current while charges are being transferred.

Abstract: A sample and hold circuit is arranged to have a common input bus line and a plurality of combinations of analog switches and capacitors connected to the command input bus line. The sample and hold circuit includes as features a signal feeding unit for sequentially feeding a sampling control signal to the analog switches and a preventing unit for preventing the plurality of analog switches from being made conductive at one time because of the delay of the sampling control signal.

Abstract: A reference voltage terminal and an input voltage terminal are connected via a first capacitor to a first electrode of a differential amplifier. Also, the reference voltage terminal and the input voltage terminal are connected via a second capacitor to a second electrode of a differential amplifier. The first capacitor samples a difference Vref-Vin in potential between the reference voltage terminal (Vref) and the input voltage terminal (Vin), and the second capacitor samples a difference Vin-Vref in potential between the reference voltage terminal and the input voltage terminal. Thus, the differential amplifier amplifies 2.times.(Vref-Vin).

Abstract: A transconductance push-pull amplifier (20) generates primary push-pull currents (I1, I2) corresponding to a voltage input signal (VIN). Current mirrors (42,44) generate secondary push-pull currents (I3, I4) corresponding to the primary push-pull currents (I1, I2). For sampling, both the primary and secondary push-pull currents (I1, I2, I3, I4) are applied to charge a capacitor (C3) in a current feed-forward arrangement with high slew rate and fast signal acquisition to produce a voltage output signal (VOUT). The capacitor (C3) is disconnected from the amplifier (20) and current mirrors (42,44) to hold the output signal (VOUT). Switching transistors (Q13, Q15) which are connected between the capacitor (C3) and the current mirrors (42,44) have substantially the same non-linear modulation characteristics as corresponding output transistors (Q7, Q8) in the amplifier (20).

Abstract: An optical imaging surface inspection system and method are provided. The system comprises an illumination source for illuminating an image pattern on a surface to be inspected, a video camera for detecting a portion of the light reflected from the surface and outputting an analog video signal, a dynamic thresholding circuit for converting the analog video signal into a digital representation of the image pattern, and means to compare a known accurate digital representation of the image pattern to the digital representation provided by the dynamic thresholding circuit. The method includes the steps of illuminating the surface, scanning the surface with the video camera, separating the video signal into a black level signal component and a white level signal component, detecting successive peak levels in the white level signal component and outputting a corresponding variable peak voltage. A variable threshold voltage is determined by selecting a percentage of the variable peak voltage.

Abstract: A low voltage AC electric power monitoring system includes a processor which samples the current and circuit breaker system includes a processor which samples each of the current components at seventeen samples per cycle to obtain current samples representing a single period of the AC power signal. The processor samples the voltage component at different points in the voltage cycle over several cycles to obtain voltage samples representing a single period of the AC power signal.

Abstract: An integrating circuit (12) includes a capacitor (22) which charges at a rate proportional to the instantaneous amplitude of an input signal V.sub.IN generated by a photosensor (14) to produce an integrated output signal V.sub.OUT. The input signal V.sub.IN is proportional to the photon rate upon the photosensor (14), which is the quantity of interest. The output signal V.sub.OUT is non-destructively oversampled at a rate which is much higher than the Nyquist rate of the input signal V.sub.IN to produce sample signals V.sub.S1 which are differenced and later recombined to produce a replica of the output signal V.sub.OUT. The capacitor (22) is discharged and the output signal V.sub.OUT thereby reset to zero whenever the amplitude of the output signal V.sub.OUT reaches a predetermined maximum value V.sub.RESET. The output signal V.sub.OUT is thereby "folded" into a sawtooth waveform, which has a dynamic range of V.sub.RESET divided by a minimum value.

Abstract: A voltage level sense circuit that has temperature compensation is disclosed. The circuit includes charge-sharing capacitors in each of an input leg and a reference leg. The charge-sharing capacitors are precharged to voltages that are integral multiples of the forward bias voltage drop across the base-emitter junction of a bipolar transistor. The bipolar transistors in the input leg differ from those in the reference leg, so that the difference in base-emitter on voltages increases with temperature. The increasing difference in base-emitter on voltage compensates for the decrease in the absolute value of the base-emitter on voltage with temperature. Voltage level sensing is accomplished by sampling the input voltage with a capacitor, charge-sharing the sampled voltage with one of the precharged charge-sharing capacitors, and coupling the charge-shared result to an input of a differential amplifier comparator.

Abstract: A peak detector samples and holds amplitudes of pulses of a servo burst and includes a master peak detector for following a portion of a rising edge of each pulse until a peak amplitude is reached, and for decaying rapidly at a falling edge of each burst following the peak until a rising edge of a subsequent burst is intercepted at a point of interception, and for generating a control window extending from the point of interception of a rising edge to a peak value of each subsequent pulse; a slave peak detector enabled by the control window of the master detector for following the portion of the rising edge of each burst from the point of interception to the peak value, and for holding the peak value reached by the master detector during the control window, a holding circuit responsive to the slave detector and having a first, rapid time constant for rapidly acquiring a peak value of at least one initial peak of the burst, and having a second, slower time constant for adjusting the initially acquired peak val