Abstract: Certain aspects of the present disclosure provide various sampling networks for switched-capacitor integrators, which may be used in switched-capacitor analog-to-digital converters (ADCs). Rather than having both an input sampling capacitor and a reference sampling capacitor, certain aspects of the present disclosure use a shared sampling capacitor for the reference voltage and the input voltage, thereby reducing ADC input-referred noise, decreasing op amp area and power, and avoiding anti-aliasing filter insertion loss. Furthermore, by sampling the reference voltage during the sampling phase and sampling the input voltage during the integration phase using the shared sampling capacitor, a high-bandwidth reference buffer need not be used for the reference voltage.

Abstract: A circuit and method compensates for comparator offset in a successive approximation register analog-to-digital converter. The circuit includes a multiplexed sampler to sample either a common mode voltage or an input signal. The sampled signal is added to a conversion voltage and an offset correction voltage and input to a comparator. The comparator determines a polarity of deviation of the sum of the sampled signal, conversion voltage and off-set correction voltage. Based on the polarity, the offset correction voltage and the conversion voltage are alternately subjected to a successive approximation process to compensate for the offset of the sum from the sampled input signal or sampled common voltage signal.

Abstract: An optoelectronic device includes a driving transistor, a correction transistor, and a control circuit. The driving transistor adjusts a first current from a power supply based on a voltage stored in a first capacitor. The driving transistor supplies the adjusted first current to the light-emitting element. The correction transistor is electrically connected on a path of a second current flowing from the power supply to the first capacitor, and adjusts the second current based on a voltage stored in a second capacitor. The control circuit controls the second capacitor to store a gray scale voltage while the first current flows, and controls flow of the second current to update the voltage stored in the first capacitor while the first current is blocked.

Abstract: A sample and hold switch circuit includes a clock generation sub-circuit, a gate voltage bootstrap unit, a sampling Field Effect Transistor, a holding capacitor and a substrate selection sub-circuit which is connected with a signal input terminal, a signal output terminal and a substrate of the sampling Field Effect Transistor and arranged for selecting the signal input terminal or the signal output terminal to connect with the substrate of the sampling Field Effect Transistor according to the voltages of the analog signal inputted and the analog signal outputted. The sample and hold switch circuit reduces nonlinearity of the sampling Field Effect Transistor caused by its gate-source voltage changing with input signal, and eliminates bulk effect of the sampling Field Effect Transistor, thereby improving linearity of the sampling Field Effect Transistor, and extending dynamic range of the sample and hold switch circuit.

Abstract: An impedance calibration apparatus of a semiconductor integrated circuit includes: a D/A conversion unit configured to receive a code and generate an analog voltage depending on the code; a virtual code voltage generation unit configured to detect a level of the analog voltage and generate a plurality of virtual code voltages based on the level of the analog voltage; a comparison unit configured to receive the plurality of virtual code voltages and a reference voltage as inputs, and compare the plurality of virtual code voltages with the reference voltage to generate a plurality of comparison signals; and a code generation unit configured to receive the plurality of comparison signals and generate the code using the plurality of comparison signals.

Abstract: A bootstrap circuit for a sampling transistor. A circuit includes a MOS transistor having a source terminal coupled to an input for receiving an input voltage; an output at a drain terminal of the MOS transistor coupled to one plate of a sampling capacitor; a first switch coupling the input voltage to a gate terminal of the MOS transistor responsive to an initial phase control signal; a bootstrap capacitor having a top plate coupled to the gate terminal of the MOS transistor and coupled to the first switch; a second switch coupling a bottom plate of the bootstrap capacitor to a first low voltage supply responsive to the initial phase control signal; a third switch coupling the bottom plate of the bootstrap capacitor to a positive voltage supply greater than the first low voltage supply responsive to a first phase periodic control signal. Additional circuits and systems are disclosed.

Abstract: There are provided a touch sensing device and a touchscreen device. The touch sensing device according to an embodiment of the invention may include: a buffer unit including a buffer capacitor charged and discharged by a first voltage and a second voltage input at a predetermined period; an integrating circuit unit integrating a charging voltage of the buffer capacitor; a signal conversion unit comparing a voltage output from the integrating circuit unit with a predetermined reference voltage to generate the second voltage; and a touch determination unit counting the second voltage with a predetermined reference clock to determine a touch.

Abstract: A level-crossing based circuit with offset voltage cancellation includes a first level-crossing detector section having a first output capacitor, wherein the first level-crossing section is configured to charge the first output capacitor to a first voltage corresponding to an input signal. The first voltage includes a first offset voltage. The level-crossing based circuit also includes a second level-crossing detector section having a second output capacitor, wherein the second level-crossing detector section is configured to discharge the second output capacitor to a second voltage corresponding to the input signal such that the second voltage includes a second offset voltage that is substantially equal in magnitude to the first offset voltage and opposite in polarity to the first offset voltage relative to an average of the first voltage and the second voltage.

Abstract: A precharge sample-and-hold circuit is provided that has an input terminal, a reference voltage terminal and an output terminal. The circuit has a sampling capacitance coupled between the input terminal and the reference voltage terminal. The sampling capacitance is configured to provide the sample voltage when the sample-and-hold circuit is in a holding mode. The circuit also has a cancellation capacitance. An analog/digital converter is provided that uses the precharge sample-and-hold circuit. A method to operate the precharge sample-and-hold circuit is also provided.

Abstract: A sensing circuit having a reduced bias clamp and method of operating the sensing circuit are provided. The sensing circuit may include a reference path and a sensing path. The sensing path may include a first transistor, clamping capacitor and a pair of switches. The reference path may include a second transistor, clamping capacitor and another pair of switches. A common gain stage receiving a bias voltage charges the clamping capacitors for the respective paths in a charging mode. The clamping capacitors may be charged in a serial or partially parallel manner during the charging mode. Each path may be coupled to a comparator, which may sense current or voltage changes between the paths during a sense mode. The sensing circuit may be configured to provide for sensing current or voltage changes between multiple sensing and/or reference paths in a parallel or serial manner.

Abstract: A semiconductor circuit which can have stable input output characteristics is provided. Specifically, a semiconductor circuit in which problems caused by the leakage current of a switching element are suppressed is provided. A field-effect transistor in which a wide band gap semiconductor, such as an oxide semiconductor, is used in a semiconductor layer where a channel is formed is used for a switching element included in a switched capacitor circuit. Such a transistor has a small leakage current in an off state. When the transistor is used as a switching element, a semiconductor circuit which has stable input output characteristics and in which problems caused by the leakage current are suppressed can be fabricated.

Abstract: A comparator is provided having a voltage generator, having an output terminal for providing a reference voltage. The comparator also has a buffer unit, providing an output signal according to a first input signal and the reference voltage; wherein the voltage generator provides the reference voltage according to a second input signal, and the output signal represents a compare result of the first and second input signals.

Abstract: A semiconductor device which stores data, and in which refresh operation is not needed, is described. The semiconductor device comprises at least a transistor and a capacitor. A first electrode of the capacitor is connected to a reference voltage terminal and a second electrode of the capacitor is connected to one of a source and a drain of the transistor. The semiconductor device is configured to put, when necessary, the other of the source and the drain of the transistor to the same potential as the one of the source and the drain, so that charge accumulated in the capacitor, which is connected to the one of the source and the drain of the transistor, does not leak through the transistor.

Abstract: A sampling device comprising a first input port and a second input port, wherein an input-signal is fed to the first input port and wherein an optical clock signal is fed to the second input port. The sampling device comprises a plurality of track and hold units, wherein each of the plurality of track and hold units is connected to the first input port. The plurality of the track and hold units is further connected to the second input port through an optical waveguide in such a manner that the plurality of tack and hold units operate in a time-interleaved mode.

Abstract: A method for clock recovery and data recovery from a data stream on a communication channel includes sampling a data stream on the communication channel at a sampling frequency determined by a clock signal and generating a sampled signal. The method further includes determining a phase shift between the communication data stream and the sampled signal and modifying the phase of the clock signal on the basis of the phase shift to obtain a desired phase difference between the sampled signal and the data stream.

Abstract: A packaged device includes a first die, a second die, and specially spaced and positioned sets of package terminals. The first die includes a pulse-width modulator (PWM), a processor, a timer, high-side drivers, low-side drivers, and a fault protection circuit. The second die includes ultra-high voltage high-side drivers. In an ultra-high voltage application, the PWM and external circuitry together form a switching power supply that generates a high voltage. The high voltage powers external high-side transistors. The processor and timer control the ultra-high voltage high-side drivers, that in turn supply drive signals to the external high-side transistors through the package terminals. External low-side transistors are driven directly by low-side drivers of the first die. If the fault protection circuit detects an excessive current, then the fault protection circuit supplies a disable signal to high-side and low-side drivers of both dice.

Abstract: In accordance with various embodiments, a method for sampling an input signal may be provided, wherein the method may include providing a single frequency clock signal; selecting clock pulses from the single frequency clock signal in a random manner to generate a spread spectrum clock signal; and sampling the input signal using the spread spectrum clock signal. A corresponding device for sampling an input signal may be provided.

Abstract: An analog to digital converter comprising at least one sampling capacitor connected to a sample node, and a pre-charge circuit arranged to cause the voltage on the sample node to substantially match the input voltage prior to the analog to digital converter entering an acquire mode in which the sample node is connected to the input node by a sample switch.

Abstract: A positive/negative sampling and holding (S/H) circuit is disclosed herein. The positive/negative S/H circuit includes an operational amplifier, a first capacitor, a second capacitor being parallel with the first capacitor and forming an integration circuit with the operational amplifier, and several discharge switches correspondingly connecting discharge paths of the first and the second capacitors to control the first and the second capacitors to output a first sampling signal and a second sampling signal respectively, and herein, the first and the second sampling signals has the same magnitude but opposite voltage polarities.

Abstract: A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit.

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract: Methods and systems for sampling a differential signal. The sampling circuit includes a differential input and a differential output. A logic control block, which is powered by VDD and VSS sources, controls the state of switches used to sample and store differential signals. The logic control block is AC coupled to the switches. The sampling circuit is configured to sample a common mode voltage at the differential input of a level that exceeds that of the VDD and VSS sources.

Abstract: A sampling circuit and a sampling method are provided, where the sampling circuit includes a first delay chain, a second delay chain, and a half-speed binary-phase detector. The first delay chain is used to delay an input signal according to an up signal and a down signal, so as to generate a first delay signal; and the second delay chain is used to delay the first delay signal according to a preset delay value, so as to generate a second delay signal. The half-speed binary-phase detector is used to sample a data signal according to edge trigger of the first delay signal and that of the second delay signal, and generate an output signal, an up signal, and a down signal according to a sampling result of the data signal.

Abstract: A method and a circuit achieve fully isolated sampling of bipolar differential voltage signals. The isolated sampling network is suitable for applications in which sampling signals far outside of the supply voltages are desired. A sampling network of the present invention may sample a differential signal between voltages ?VDSMAX and VDSMAX, even with common mode voltages that exceed the supply voltage (e.g., an input stage of an ADC). The bipolar isolated input sampling network may include a polarity comparator and sampling switches that operate as rectifiers. Rectification ensures that a unipolar sampling network needs only to sample signals of predetermined voltage levels.

Abstract: Circuits and methods for fast detection of a low voltage in the range of few ?Volts have been achieved. In a preferred embodiment the low voltage represents a current via a shunt resistor and the circuit is used to generate a digital wake-up signal. In regard of the wake-up application the circuit invented is activated periodically and in case of a certain level of the voltage drop, e.g. 50 ?V, at the shunt resistor. The time required for a measurement of the voltage drop is inclusive calibration and integration time far below 1 ms. It is obvious that the circuit invented can be used for any measurements of very small voltages.

Abstract: A control circuit of a power converter according to the present invention comprises a switching circuit, a sample-and-hold circuit and a current source. The switching circuit generates a switching signal in response to a feedback signal. The sample-and-hold circuit samples the feedback signal. The current source is coupled to a feedback terminal for generating a programming voltage. A programmable signal is generated in accordance with the programming voltage and the feedback signal, and the programmable signal is coupled to set a parameter.

Abstract: A compensation circuit for eliminating harmonic content resulting from a phase imbalance in a differential sampling circuit. The compensation circuit includes a pair of field effect transistors operating in saturation mode, each field effect transistor coupled in parallel with the differential switch of the sampling circuit, which operates in linear mode. The saturation region transistors across the differential switch allow the harmonic content to flow through the compensation circuit instead of the sampling capacitors of the sampling circuit.

Abstract: Accumulators that operate to fully or partially remove noise from a signal, including removing noise inserted into the signal by the accumulator itself. In some embodiments, an accumulator may be operated in a sampling phase and a transfer phase each time the accumulator samples an input signal. In some such embodiments, an op-amp of an accumulation circuit of the accumulator may be auto-zeroed during some or all of the sampling phases of an accumulation period. In some embodiments in which the op-amp is auto-zeroed during some or all of the sampling phases, the accumulation circuit may include a holding capacitor that, during an auto-zeroing process, holds a value output by the op-amp during a prior transfer phase. Including such a holding capacitor in an accumulator may reduce a voltage that the op-amp output rises following the auto-zero process, which may reduce a bandwidth and noise of the accumulation circuit.

Abstract: The invention relates to a low leakage switch having an input node for receiving an input voltage and an output node for providing an output voltage. The low leakage switch comprises a main sampling transistor the backgate voltage of which is biased through other transistors, and wherein the control gate of the main sampling transistor is controlled through a second control signal and the control gates of the other transistors are controlled through a first control signal, wherein the electronic device is further configured to activate the other transistor for adjusting the backgate voltage of the main sampling transistor through the first control signal before activating the main sampling transistor for sampling the input voltage on a main sampling capacitor through the second control signal.

Abstract: Techniques pertaining to an analog sample circuit are disclosed. One embodiment of the analog sample circuit shows characteristics of low distortion and high linearity, which can be used in many circuits including integrated circuits (IC). In a switch circuit or an analog sample circuit of one embodiment, a constant voltage module is configured to stabilize the gate-source voltage of the PMOSFET switch as the sample switch, so that the gate-resource voltage of the PMOSFET switch doesn't vary with the input signal Vin; a switch circuit is configured to ensure that the switch circuit or the analog sample circuit is capable of processing the input signal lower than a minimum voltage in the circuit.

Abstract: Provided is a direct sampling circuit in which signal mixing between systems is avoided, even when signal systems in which time sharing is integrated are used together by time sharing. History capacitors (153, 155) are connected at a preceding step to a switched capacitor filter (160) for each system, buffer capacitors (173, 175) are connected at a subsequent step to the switched capacitor filter (160) for each system, and the history capacitors and buffer capacitors, which are connected to a rotation capacitor of the switched capacitor filter (160), are switched for each time-sharing system that is input.

Abstract: A sensor circuit for obtaining physical quantities with a small margin of error even when the temperature varies is provided. The sensor circuit includes a sensor, a sampling circuit for obtaining a voltage value or a current value of a signal output from the sensor during a predetermined period and holding the value, and an analog-to-digital converter circuit for converting the held analog voltage value or current value into a digital value. The sampling circuit includes a switch for obtaining the voltage value or the current value and holding the value. The switch includes a transistor including an oxide semiconductor in a channel formation region.

Abstract: A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.

Abstract: A method for generating a ramp comprises providing a voltage reference source, providing a summing amplifier, providing n switched capacitor elements coupled in parallel between the voltage reference source and the summing amplifier, and selectively activating a predetermined number of the switched capacitor elements to first store charge on each activated switched capacitor element and then to measure the sum of the charges on the activated capacitor switch elements in each of a fixed-integer number of time slots in a cyclical manner, the predetermined number being between 0 and n.

Abstract: A sampling circuit includes a continuous section which is a circuit for transmitting a continuous signal; a digital section for transmitting a signal which is sampled and quantized; and a sampling and holding section for transmitting a signal which is sampled but not quantized between the continuous section and the digital section. The sampling and holding section includes capacitors for accumulating charge generated by an input signal and plural switches for accumulating the charge in the capacitors. The plural switches receive plural clock signals having different operation timings and perform an ON/OFF operation in response to the supplied clock signals.

Abstract: A sampling circuit comprising: an input node; a first signal path comprising a first sampling capacitor and a first signal path switch in a signal path between the input node and a first plate of the first sampling capacitor; a second signal path comprising a second sampling capacitor and a second signal path switch in a signal path between the input node and a first plate of the second sampling capacitor, and a signal processing circuit for forming a difference between a signal sampled onto the first sampling capacitor and a signal sampled onto the second sampling capacitor.

Abstract: A circuit for sampling an analog input signal may include a transistor disposed on a substrate and a sampling capacitor coupled to one of the source and the drain of the transistor. The transistor may be disposed on a substrate that is coupled to ground. A source and a drain of the transistor may be disposed in a back gate of the transistor. The analog input may be supplied to one of the source and the drain of the transistor, and the back gate may receive a back gate voltage having a value that is lower than ground.

Abstract: A semiconductor circuit which can have stable input output characteristics is provided. Specifically, a semiconductor circuit in which problems caused by the leakage current of a switching element are suppressed is provided. A field-effect transistor in which a wide band gap semiconductor, such as an oxide semiconductor, is used in a semiconductor layer where a channel is formed is used for a switching element included in a switched capacitor circuit. Such a transistor has a small leakage current in an off state. When the transistor is used as a switching element, a semiconductor circuit which has stable input output characteristics and in which problems caused by the leakage current are suppressed can be fabricated.

Abstract: Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch.

Abstract: A system and method have been provided for passively isolating a latch circuit. The method provides a latch having a first input, an output, and a reset port. The latch first input is selectively connected to a first reference voltage. While the latch first input is connected to the first reference voltage, the latch is reset. Subsequent to disconnecting the latch first input from the first reference voltage, a first node is selectively connecting to the latch first input. In response to selectively connecting the first node, a first analog signal is supplied to the latch first input. Subsequent to resetting the latch, the first analog signal is captured and the latch output supplies a digital signal responsive to the captured first analog signal.

Abstract: A circuit includes an input, two or more sampling capacitors each in a different channel, means for connecting each sampling capacitor to the input, means for discharging the sampling capacitors to a given voltage in a reset phase, and means to use the voltage across the sampling capacitor for further processing in a hold phase. The two sampling capacitors operate in anti-phase such that the reset phase and sampling phase of one channel are performed in the time period the other channel is in the hold phase.

Abstract: A sample-and-hold circuit for generating a variable sample delay time of a transformer includes a discharge detection unit, a sample delay time generation unit, and a comparator. The discharge detection unit generates a first voltage according to a first turning-on signal and a first reference current. Length of the first turning-on signal is varied with a discharge time of a present period of the transformer. The sample delay time generation unit generates a second voltage according to the first turning-on signal and a second reference current. The comparator generates a sample signal to a control circuit of the transformer according to a first voltage corresponding to a previous period of the transformer and a second voltage corresponding to the present period of the transformer. The first reference current is K times the second reference current, and 0<K<1.

Abstract: A double switched track-and-hold circuit includes an input buffer having a first switched amplifier circuit for passing an input signal in a track mode and isolating the input signal from a buffer output in a hold mode, and a track-and-hold core circuit responsive to the input buffer and having a second switched amplifier circuit for tracking the input signal in a track mode and isolating the input signal from a track-and-hold output in a hold mode. The first and second switching amplifier circuits turn off approximately simultaneously during the hold mode to provide enhanced isolation.

Abstract: A receiver includes an antenna interface, a frequency translation bandpass filter (FTBPF), a sample and hold module, and a down conversion module. The antenna interface is operable to receive a received wireless signal from an antenna structure and to isolate the received wireless signal from another wireless signal. The FTBPF is operable to filter the received wireless signal to produce an inbound wireless signal. The sample and hold module is operable to sample and hold the inbound wireless signal in accordance with an S&H clock signal to produce a frequency domain sample pulse train. The down conversion module is operable to convert the frequency domain sample pulse train into an inbound baseband signal.

Abstract: Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch.

Abstract: The data latch circuit of the invention includes a means for short-circuiting an input terminal and an output terminal of an inverter and by connecting the input terminal to one electrode of a capacitor and sampling a data signal or a reference potential to the other electrode of the capacitor, an accurate operation can be obtained without being influenced by variations in the TFT characteristics even when the amplitude of an input signal is small relatively to the width of a power supply voltage.

Abstract: Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch.

Abstract: An input circuit for an analog-to-digital converter (ADC) includes at least one bootstrap circuit, including at least one first switch for connecting electrical power to a first terminal of at least one capacitor; at least one second switch for connecting a second terminal of the at least one capacitor to a signal to be sampled; at least one third switch for connecting the first terminal of the at least one capacitor to the control gate of at least one sampling network input switch; at least one fourth switch for connecting the at least one sampling network input switch to a substrate; and at least one fifth switch for connecting the second terminal of the at least one capacitor to the substrate.

Abstract: A track-and-hold circuit comprises at least first and second amplifier stages, and switched capacitor circuitry coupled between the first and second amplifier stages. In a track mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to decouple inputs of the second amplifier stage from respective outputs of the first amplifier stage and to couple the inputs of the second amplifier stage to a common mode voltage via respective first and second capacitors. In a hold mode of operation of the track-and-hold circuit, the switched capacitor circuitry is configured to couple the inputs of the second amplifier stage to the respective outputs of the first amplifier stage via the respective first and second capacitors. Multiple instances of the track-and-hold circuit may be implemented in parallel in a time-interleaved analog-to-digital converter.

Abstract: Various exemplary embodiments relate to a tracking system and method. The system includes a transistor switch having a gate node and a source node, a power source circuit connected to the gate node, and a bootstrapping circuit connected to the source node and to the gate node. The power source circuit charges the switch during a first tracking phase, and the bootstrapping circuit charges the switch during a second tracking phase.