Abstract: An energy saving clock signal generator is disclosed including a source of multi-phase waveform signals, a shift register, and a matrix switch. The waveform source provide four, six or more waveform signals to the shift register and the matrix switch. A number of progressive pulses N.sub.pp which are an integer multiple of the number of waveform signals are applied from the shift register to the matrix switch. The matrix switch responds to the waveform signals and the progressive pulse signals to produce a number of output clock signals which may be used to drive adiabatic logic circuits.

Abstract: A clock switcher circuit for providing at least one set of clock signals selected from a plurality of clock sources. A first clock signal having a first pulse length and a second clock signal having a second pulse length are circuit inputs. Another circuit input is a clock selection input. When the clock selection input indicates a new output clock signal, different from the then current output clock signal, should be output by the circuit, the circuit provides a means for switching to output the new output clock signal. In switching to output the new output clock signal, the circuit prevents the occurrence of the output clock signal ever having a pulse shorter than the normal pulse length of the then current output clock signal, whether the then current output clock signal is the first clock signal or the second clock signal.

Abstract: An ECL multiplexing circuit (20) includes two differential pairs (21 and 22) for receiving first and second ECL level input signals, emitter-follower output transistors (27 and 28), and a differential pair (31 and 32) for receiving differential clock signals. The differential clock signals control which of the two differential pairs (21 and 22) is coupled to the emitter-follower output transistors (27 and 28). The ECL level input signals that control a logic state of the output signals is determined by the logic state of the clock signals. The ECL multiplexing circuit (20) receives non-overlapping clock signals and is used in a quadrature frequency divide-by-two circuit (40) to divide a frequency of an input clock signal by two.

Abstract: A dynamic clock switching circuit in which a multiplexer (MUX) is connected to clock A and clock B. MUX control lines are encoded to signal clock A or clock B. A MUX control change detector is connected to the multiplexer and to the MUX control lines. A MUX control change detector decodes the MUX control lines and asserts a MUX change signal upon a condition that a change from one clock to another is signaled. A Hold Sync flip-flop is connected to a hold output of a Hold Start flip-flop. The Hold Sync flip-flop is connected to and clocked by the clock A. A Hold Disable flip-flop is connected to an OK to change output of the Hold Sync flip-flop. The Hold Disable flip-flop is connected to and clocked by clock A. A Clock Sync flip-flop is connected to a hold disable output of the Hold Disable flip-flop. A reset input of the Hold Start flip-flop is connected to a clock sync output of the Clock Sync flip-flop. An AND is connected to the hold output and to the hold disable output.

Abstract: A device detecting a sync signal is provided, which comprises a sync signal detector having an output selector, an internal clock generator and a combination of three current mirror circuits formed of MOS transistors, and two MOS transistors having resistance characteristics. Irrespective of the high and low state of the input clock signal, the selecting signal for selecting the received sync signal, is made to be high, and the discharge time of the capacitor is minimized so that a capacitor having small capacity can be used and the volume of an integrated circuit element can be minimized and the stable operation is performed, irrespective of the frequency band of the sync signal and the duty thereof.

Abstract: An input buffer is described which is configurable depending on whether a 5.0 or 3.3 volt supply voltage is present, The input buffer includes two input buffer circuits. The output of a first input buffer circuit is output as valid data when the supply voltage VCC equals 5.0 volts. The output of the second input buffer circuit is output as valid data when the supply voltage VCC equals 3.3 volts.

Abstract: If, in a clock generator according to the present invention, the first clock is switched to the second clock with a lower frequency, the frequency count circuit counts the frequency of the second clock with using the first clock as reference. The clock switching control means judges whether the frequency of the second clock is stable or not based on the count result from said frequency count circuit and, if it is stable, switches the switching means for clock switching to the second clock.

Abstract: A clock signal switching circuit, to which at least first and second clock signals and a switching signal requesting a switching operation are inputted, and which selectively outputs one of the inputted first and second clock signals by the requested switching operation, the second clock signal being synchronized with the first clock signal and having an integer multiple times cycle of the first clock signal, is provided with: a generating device, to which the second clock signal is inputted, for generating a strobe pulse at a transition timing of the inputted second clock signal; and a sampling device, to which the switching signal and the generated strobe pulse are inputted, for sampling the inputted switching signal at a timing of the inputted generated strobe pulse.

Abstract: An accurate phase shifting circuit providing two analog signals having a 90-degree phase shift between them from a single sampled-data input without the need for components external to a monolithic integrated circuit. A combination of two discrete-time circuits achieves the required 90-degree phase relationship over a broad frequency region. Several sample-and-hold circuits and multiplexors are used to produce two discrete-time versions of the analog input signal. Subtracting that older sample from the most-recent sample yields a forward difference signal and adding the most recent and the older samples produces a forward average signal. The phase difference between any single-frequency component of the forward difference and forward average signals is always 90 degrees. A pair of matched filters serves to reconstruct the sampled analog waveforms and to remove unwanted high-frequency noise in the +90.degree. output signal.