Abstract: A method and apparatus for automatically determining the protocol being used from the frequency of an applied clock without the need for a separate pin or switch or a second external clock. The clock's frequency is identified when its frequency falls into the set range for which the apparatus is targeted. Based on the detected frequency in the set range, a mode select signal is generated. The mode select signal causes the chip to configure to the appropriate frequency for that mode, as well as any other unique configuration parameters. In one embodiment, the invention generates a ramp signal triggered by the external clock (which is the clock frequency for the desired protocol). The clock is simultaneously applied to a counter. When the ramp signal reaches a reference voltage, the count of the counter is compared to at least one threshold to determine to which frequency it corresponds. In response to this determination, the chip is configured according to the communication mode or protocol indicated.

Abstract: A device includes a first input pin, a second input pin, a differential signal generator, and a differential receiver. The first input pin is adapted to receive a first signal. The second input pin is adapted to receive a second signal. The differential signal generator is coupled to the first and second input pins and adapted to receive an enable signal. The differential signal generator is adapted to isolate the second input pin and generate an internal signal based on an inversion of the first signal in response to the enable signal being asserted. The differential receiver has a first input terminal and a second input terminal. The differential receiver is adapted to receive the first signal at the first input terminal and one of the second signal and the internal signal at the second input terminal and generate a differential output signal. A method for generating a differential signal is provided. A first input signal is received at a first input pin of a device. An enable signal is received.

Abstract: A method and apparatus for automatically determining the protocol being used from the frequency of an applied clock without the need for a separate pin or switch or a second external clock. The clock's frequency is identified when its frequency falls into the set range for which the apparatus is targeted. Based on the detected frequency in the set range, a mode select signal is generated. The mode select signal causes the chip to configure to the appropriate frequency for that mode, as well as any other unique configuration parameters. In one embodiment, the invention generates a ramp signal triggered by the external clock (which is the clock frequency for the desired protocol). The clock is simultaneously applied to a counter. When the ramp signal reaches a reference voltage, the count of the counter is compared to at least one threshold to determine to which frequency it corresponds. In response to this determination, the chip is configured according to the communication mode or protocol indicated.

Abstract: A clock routing circuit is coupled to receive a primary clock signal, a secondary clock signal, and a select signal, all of which may be asynchronous with respect to one another. When the select signal is in a first state, the clock routing circuit passes the primary clock signal as an output clock signal. When the select signal transitions to a second state, the clock routing circuit waits for the primary clock signal to transition in a predetermined direction (i.e., rising edge or falling edge). Upon detecting the transition of the primary clock signal, the clock routing circuit holds the state of the output clock signal. The clock routing circuit then waits for the secondary clock signal to transition in the predetermined direction. Upon detecting the transition of the secondary clock signal, the clock routing circuit passes the secondary clock signal as the output clock signal.

Abstract: A unique hierarchical multiplexer is employed to multiplex signals read out from analog array elements one at a time to an output. In an embodiment of the invention, the multiplexer switching elements, i.e., switches, are arranged in groups in a hierarchical, i.e., tree, configuration. In the tree configuration for a given analog array size, output capacitance is significantly reduced because each analog array element and its associated buffer amplifier drive fewer switches than in other configurations. The lower capacitance reduces any resulting FPN and the resulting lower analog array element and buffer amplifier drive current reduces power dissipation. The reduced capacitance also decreases the transient settling time interval.

Abstract: An internal input voltage generating/external output voltage generating circuit is provided within a semiconductor device, a voltage on a pad corresponding to a supply pin terminal is detected to specify the inserted orientation of the semiconductor device based on the detection result and apply a correct voltage to a chip internal circuit. According to the specified direction, one of a plurality of pin terminals located in rotation or line-symmetry is selected to couple the selected terminal to the chip internal circuit. Accordingly, a semiconductor device can be implemented that is never damaged and operates normally even if the device is mounted on a circuit board in any possible orientation which the device can take upon board mounting.

Abstract: A circuit for spike-free clock switching which offers asynchronous switching between two clock signals of the same frequency and of any desired phase angle, which is purely digital, which can be fully implemented in an integrated module, and which avoids spikes/glitches during switching.

Abstract: A clock signal switching circuit that switches between two clock signals having a phase difference. The clock signal switching circuit includes a first selector that selects one of the clock signals according to the level of a selection signal, a second selector that selects one of first and second control signals according to the level of the selection signal. The level of the first and second control signals are changed in response to an original signal and the first or the second clock signal. A gate circuit generates the output signal from the first and second selectors wherein the level of the selection signal is changed in response to the original signal after the levels of both of the first and second control signals have changed.

Abstract: The clock switchover circuit includes a NAND circuit supplied with an output of a first inverter circuit, and a first DFF supplied with an output of the NAND circuit. Further, there is provided a NOR circuit, and a second DFF supplied with an output of the NOR circuit. A second inverter circuit is supplied with an output of the first DFF. A clock signal selection section is supplied with outputs of the second DFF and the second inverter circuit. A third inverter circuit is supplied with an output of the clock signal selection section.

Abstract: A circuit configured to generate an output clock signal generally having (i) a first frequency when in a first mode and (ii) a second frequency when in a second mode, in response to a plurality of signals. A delay of the output clock signal may be identical when operating in either the first mode or the second mode.

Abstract: First and second clocked digital sources are provided in each of two data paths, and are clocked by respective direct and complementary clock pulses. The clocked outputs of these devices are directed to a multiplexer where the inter-leaved data path signals are recombined into a single output line. This multiplexer includes clocked transmission gates, the clock signals for which are shifted in time by 90° from the clock signals applied to the originating signal sources. The result is that additional time is made available for sampling the digital signals applied to the multiplexer.

Abstract: A differential amplifier is provided, incorporating negative hysteresis by automatic reference voltage adjustment. A delayed output signal is routed to a switch or multiplexer which functions to select one of two reference voltage levels, creating negative hysteresis. The delayed output signal is delayed by a series of inverters, which prevent certain embodiments of the invention from oscillating under some conditions. The two reference voltage levels are selected to be near the respective data signal input high and low signal voltage levels, but far enough from these levels so as not to be adversely affected by noise or other interference.

Abstract: A circuit including a plurality of first calibration circuits, a second circuit and a third circuit. The plurality of calibration circuits may each be configured to present a calibration signal. The second circuit may be configured to select one of the calibration signals in response to a plurality of configuration signals. The third circuit may be configured to generate a control signal in response to (i) a reference signal and (ii) the selected calibration signal.

Abstract: High-bandwidth, analog multiplexer circuits with low signal feed-through and good common mode properties are described. These are BiCMOS circuits with N-MOS control transistors which emphasize low parasitic capacitance through circuit layout techniques and the use of smaller geometry devices where possible. These circuits can be used in both single-ended and differential configurations and address applications having multiplexing ratio requirements ranging from 2-to-1 up to many-to-1.

Abstract: Disclosed is a control circuit of a simplified circuit configuration and control while power consumed by the continuous supply of a clock signal to a functional block which is in an inoperative status is reduced. A functional block supplies a status detection signal indicative of an operative status or an inoperative status to a clock control unit. When the status detection signal indicates the operative status, the clock control unit supplies a clock signal to thereby operate the functional block. When the status detection signal indicates the inoperative status, the clock control unit stops the supply of the clock signal to thereby stop the functional block.

Abstract: A clock generator circuit has a pulse generator with an output connected to a multiplexer and an output connected via a clocked latch to a second input of the multiplexer. The clock latch is transparent in one clock state. By selecting the relationship between the outputs of the pulse generator, different clock outputs can be derived.

Abstract: A reference frequency signal switching circuit of the invention comprises: a internal oscillator for generating an internal reference frequency signal; an external reference frequency signal input terminal to which an external reference frequency signal is supplied; and a signal switching circuit for selectively outputting the internal reference frequency signal and the external reference frequency signal. Since an output level adjusting circuit for setting the external reference frequency signal outputted to a reference frequency signal output terminal so as to be at a predetermined level is provided, the output level can be made constant.

Abstract: A signal distributing circuit of the invention includes a first element which outputs a first signal and a second signal which is opposite to that of the first signal. The circuit is provided with a first signal line on which the first signal is transmitted and a second signal line on which the second signal is transmitted. A plurality of second elements each of which is connected to the first signal line in a first order and connected to the second signal line in a second order, wherein the second order is opposite to that of the first order. A method for connecting a plurality of loads to first and second signal lines, which are allocated to a regular signal and a signal opposite to that of the regular signal, respectively, of the invention includes connecting the loads to the first signal lines in a first order; and connecting the loads to the second signal lines in an order opposite to that of the first order.

Abstract: A multiplexer includes a first input device that receives a first input signal and a first select signal. When the first select signal has a first state, the first input device generates a first voltage at a first node in response to the first input signal. When the first select signal has a second state, the first input device generates a first reference voltage at the first node. A second input device receives a second input signal and a second select signal related to the first select signal. When the second select signal has a first state, the second input device generates a second voltage at a second node in response to the second input signal. When the second select signal has a second state, the second input device generates a second reference voltage at the second node. A first output buffer has an input terminal coupled to the first node and an output terminal coupled to an output node.

Abstract: A circuit for discriminating between complementary first and second input signals. By using a logic gate in parallel with a signal amplifying circuit, the signal amplifying circuit can be disabled when it is no longer required. Once the logic gate is capable of detecting distinct complementary states in the two input signals, the signal amplifying circuit is disabled and the circuit uses one of the input signals as its output signal. The circuit is improved by using a pair of Schmitt inverters so the logic circuit will not vacillate unpredictably when the input signals are in an indeterminate state.

Abstract: A circuit for switching digital signals on a plurality of signal lines where signals on different signals line may have different signal rates includes a controller that prevents a switch from being turned off until after another switch is stably turned ON. This allows more than one switch at a time to supply a correspondingly received digital signal to an output. Substantially identical digital signals may be supplied to two inputs of such a circuit while the circuit is switched between the respective inputs. The circuit may be driven by an encoder that supplies encoded signals without recursion but that conforms to encoding conventionally supplied by recursion. The encoder may be implemented in parallel configuration for rapid encoding of a signal, and may be implanted to perform a data strobe signal encoding conforming to IEEE standard 1394.

Abstract: The present invention includes a method and apparatus for smooth transitions (switching) between asynchronous clocks without the occurrence of glitches. In one embodiment the present invention is used when powering up and powering down a computer system and transitioning between a relatively faster primary clock and a slower alternate clock. In another embodiment the present invention is used for transitioning between a relatively faster primary clock to a slower alternate clock to conserve power, for example, when a laptop transitions between use mode and sleep mode.

Abstract: The invention relates to a fast signal selector having a plurality of transfer gates which are connected in parallel. The input signals are applied to the signal inputs of the transfer gates and a selection signal is applied to control inputs of the transfer gates. Due to the switching properties of the transfer gates, the input signals can be switched through onto a common output line essentially without any power loss and with a very short time delay of approximately 20 ps.

Abstract: A signal sorter for magnitude sorting among a number of signals is disclosed that allows for magnitude sorting of a number of signals in an ascending or descending ordered manner governed by the clock controlling signals. The sorter can generate sorted outputs fast enough for real-time applications and has a circuit structure suitable for implementation as integrated circuit devices. The sorter has a signal input section, maximum-deriving section, a feedback control and voltage output section and a sorted output section. All four sections are controlled by a set of timing clock input signals to manipulate the signal magnitude sorting.

Abstract: Circuits for the restoration of a drooped signal are disclosed. In the asynchronous mode circuit, the drooped signal can be restored by detecting the peak of the positive amplitude and the peak of the negative amplitude and take the difference between the two peaks. This difference signal is fed back the equalizer. In the synchronous mode circuit, the drooped signal is sliced and passed to a regeneration circuit. The regeneration circuit uses reference voltage signals and phase information from the slicer to generate a regenerated signal. The regenerated signal is compared with the equalized signal to generate a difference signal, again fed back to the equalizer. The sliced signal is also fed to a clock recovery circuit which recovers the clock signal embedded in the received signal. The two circuits can be combined to provide an optimal circuit for the restoration of a drooped signal.

Abstract: A pair of synchronized clock sources provides phase and frequency synchronous first and second clocks accompanied by first and second control signals to a clock selection circuit having a data selector comprising a first synchronizer and a second synchronizer which re-times the first and second control signals, and these re-timed outputs that are coupled to an asynchronous state machine. The asynchronous state machine changes state by logically operating on the re-timed control signals in conjunction with a state bit. This state bit is used to control the multiplexer, which achieves glitch-free switching between the first clock source and the second clock source.

Abstract: A multiplexer selects multiple input signals to produce an output in which the distortion associated with switching is minimized. Selection of the multiple input signals is performed within a multiplexing operational amplifier. The operational amplifier includes differential amplifiers that receive the respective input signals at their respective noninverting nodes. The differential amplifiers are connected to a feedback signal at their respective inverting nodes. The input signals are selected for output by turning on selection switches within the operational amplifier, causing the respective differential amplifiers to be selected. This minimizes non-linearities in the output due to capacitive coupling and eliminates unwanted resistive effects without requiring complicated circuitry. The selection switches may include complementary back-to-back MOSFETs, or alternatively, same-channel MOSFETs connected in series to cancel capacitive coupling and switch feedthrough within the multiplexing op-amp.

Abstract: A digital multiplexer with low power consumption and a data to output propagation delay of about one gate includes a plurality of pairs of emitter coupled input transistors. The emitters of each pair of input transistors are connected to the collector of a corresponding selection transistor. The emitters of the selection transistors are connected to a main current source. The data at a selected pair of complimentary data inputs is transmitted to complimentary outputs by activating the selection transistor connected to the pair of input transistors corresponding with the selected inputs, thereby connecting the current source in series with those input transistors. The power consumption of the multiplexer is low because the single main current source is used for all of the inputs. Cascode transistors are connected between the collectors of the input transistors and the bases of output transistors.

Abstract: A current sorter for sorting a plurality of currents is disclosed. The current sorter comprises an input circuit unit for receiving a plurality of input currents to be sorted, a winner-take-all (WTA) circuit unit for finding the maximum current, a feedback control and voltage output circuit unit for generating feedback control signals and output voltages indicating the maximum current, and an output circuit unit for outputting sorted currents. A plurality of input currents are simultaneously input to the input circuit unit and the sorted results are output in a time-shared manner on the output circuit unit.

Abstract: A method and apparatus for selectively sending a first signal or a second signal to an output signal are described. An electrical characteristic of a device coupled to the output is determined, and, in the event the electrical characteristic is determined to be a predetermined value, the first signal to the output, otherwise, the second signal is sent. A detector coupled to the output of an information handling system detects a characteristic of a device coupled to the output. The characteristic is indicative of the type of signal sent to the output. A first type of signal is sent to the output when the characteristic has a predetermined value and a second type of signal is sent to the output when the characteristic does not have the predetermined value. Whether a speaker is an analog speaker or a digital speaker may be automatically determined, and an appropriate analog or digital signal is sent to the speaker depending upon its type.

Abstract: A semiconductor device has a DLL circuit or the like for adjusting the phase of an external clock and producing an internal clock that lags behind by a given phase. The semiconductor device further includes a clock frequency judging unit for judging the frequency of a first clock on the basis of an indication signal indicating a delay value of the first clock in the DLL circuit or the like to output a control signal; and a clock selecting unit for selecting either one of the first clock and the second clock, in response to the control signal.

Abstract: The selector circuit rapidly steers an event from a single input to one of two outputs depending on the binary value of a data signal controlling the selector, where events are received at an event input. A selection value, placed at a control input causes the selector circuit to steer the event to one of the outputs. For each change of value at the event input, one or the other of the outputs will change. Which output changes is determined by the selection value applied to the control input. The selector circuit uses variable or dynamic capacitances at the outputs to control which one of the outputs changes in response to an input event. Each node of the selector circuit includes a true line and a complement line. Pass gates are used to either couple the true lines of the outputs together or to couple the true line of each output and the complement line of the other output.

Abstract: A circuit to vary a frequency of an input clock is disclosed. The circuit includes a delay generator to generate at least two delayed clocks from the input clock and a select circuit coupled to receive the at least two delayed clocks and provide an output clock from one of the at least two delayed clocks. The select circuit switches the output clock from the one of the at least two delayed clocks to the other of the at least two delayed clocks on a first edge.

Abstract: A pulse generating circuit for a dynamic random access memory includes a fixed pulse generating unit receiving an input signal and generating an output pulse signal of a fixed width, a pulse delay unit receiving the input signal and delaying an output pulse signal of a variable width, a pulse width detecting unit receiving the input signal and an inverted input signa, outputting a first flag signal displaying a low pulse width by detecting the low pulse width of the input signal, and outputting a second flag signal displaying a high pulse width by detecting the high pulse width of the input signal, a NOR gate performing a logical operation on the first flag signal and the second flag signal and outputting a third flag signal, and a multiplexer coupled to the fixed pulse generating unit, the pulse delay unit, and the pulse width detecting unit and outputting an output pulse signal in accordance with the third flag signal.

Abstract: A clock switching system for providing synchronous glitch-free switching of a clock source from among one or more asynchronous clock sources comprises a multiplexor device for providing a system clock output signal corresponding to a first asynchronous clock source input, and a switch control circuit for generating first and second control signal. In response to the first control signal, the multiplexor device enables simultaneous coupling of a selected second asynchronous clock source to be switched to the multiplexor circuit, and decoupling the first asynchronous clock source input. Further in response to the first control signal, the system clock output is held at a first output level. In response to the second control signal, the second asynchronous clock source is coupled to the system clock output while both signals are at the first output level.

Abstract: A phase-enable circuit clocks a first functional unit at a first frequency and a second functional unit at a second frequency. Each of the first and second functional units is provided with a first clock signal of the first frequency. A phase-enable generator then uses the first clock signal and a second clock signal of a second frequency lower than the first frequency to develop a phase-enable signal that periodically disables a clock input terminal of the second functional unit so that the second functional unit is clocked at the second frequency. Changing the frequency of the second clock to zero switches the phase-enable circuit into another mode of operation. In that mode, the clock input terminal of the second functional unit is constantly enabled and the first and second functional units are each clocked at the first frequency.

Abstract: A data processing apparatus functions as a timer or counter by counting clock pulses of a system clock signal to generate a timing signal. The system clock signal is generated as one of either a first or a second basic clock signal generated by two respective oscillators. Even if the second basic clock signal which has a lower frequency fluctuates, the data processing apparatus can accurately generate a pulse signal having a desired period. When the first basic clock signal is selected as the system clock signal, the second basic clock signal is measured with the system clock signal. When the second basic clock signal is selected as the system clock signal, a numerical value up to which the clock pulses of the system clock signal are counted is corrected on the basis of the measured second basic clock signal.

Abstract: A circuit for the glitch-free changeover between digital signals includes a multiplexer having a multiplicity of signal input terminals, signal select terminals and a signal output terminal. Furthermore, the circuit includes a counter logic unit for counting pulses in the output signal of the multiplexer and for outputting a count signal when a specific count value is reached. A delay logic unit delays a multiplexer select signal and outputs a switching signal and a delayed multiplexer select signal. During a set switching signal the counter logic unit is activated and the circuit output is deactivated.

Abstract: An operation speed measuring circuit measures a difference in propagation delay time between first and second path 2, 3 including logic gates connected in series and thus confirms that an element provided on a chip obtains a specified operation speed. This operation speed measuring circuit is so constructed as to be controllable by an input signal IN from one input terminal 1 and can be therefore disposed in such an area that the number of placeable terminals is restricted down to a small number. When this operation speed measuring circuit is provided with a power supply terminal independent of other circuits, constructions of other circuits can be independently designed. When the operation speed measuring circuit is disposed in the area independent of an intra-chip integrated circuit design area, a degree of freedom of designing other circuits is improved.

Abstract: A clock distribution circuit and method for programmable ICs whereby the incoming clock frequency is optionally divided by two and distributed at the new, lower frequency. Programmable dual-edge/single-edge flip-flops are provided that optionally operate at twice the frequency of the distributed clock, being responsive to both rising and falling edges of the distributed clock. When the clock divider is enabled and the flip-flops are programmed as dual-edge, the operating frequency is the same as that of the incoming clock; however, the frequency of the distributed clock is reduced by one-half. This reduction halves the frequency at which the clock distribution circuits operate, and consequently approximately halves the power dissipated by the clock distribution circuit, thereby providing a programmable power-saving mode.

Abstract: A semiconductor memory device including an operation control circuit for selecting between a single data rate (SDR) mode and a double data rate (DDR) mode. The operation control circuit includes a mode selector for generating a master signal which selects between the SDR and the DDR mode. The operation control circuit also includes a shift register, a repeater, and a pulse generator. When the SDR mode is selected, the shift register generates an output clock signal which changes states every period of the input clock signal. When the DDR mode is selected, the repeater generates an output clock signal which changes states with every state change of the input clock signal. Productivity efficiency is enhanced and production costs are reduced by providing both the SDR and the DDR mode circuitry and the operation control circuit on a single chip.

Abstract: A method and system for a clock driver is described which can buffer an master clock directly, or generate a output clock signal having a balanced duty cycle which is the input clock frequency divided by a predetermined value. When a frequency control input, such as a rate signal, is switched, the clock output makes a glitchless transition from one frequency to the other. The clock driver includes a counter divider circuit with feedback to produce two signals related by a predetermined phase difference. The counter divider circuit employs predetermined logic delays by buffered gating controlled by the master clock, which produces two signals. These two signals act as "enable" control signals such that the timing of their rising and falling edges is arranged to never propagate through the clock divider circuit to become the edges of output clock. The master clock is gated with these two signals to provide two unbalanced signals which are synchronous to the input clock signal.

Abstract: Multiplexers are used to generate synchronized slave clocks from a common master clock. A first multiplexer and a second multiplexer generate a first slave clock and a second slave clock, respectively, from the common master clock. A third multiplexer and a fourth multiplexer are configured as a divide-by-n circuit for providing a third slave clock that is a divided version of the second slave clock. A fifth multiplexer provides a matching delay to preserve the synchronization between the first slave clock and the other slave clocks. A sixth multiplexer is used to select between the second slave clock and the third slave clock in response to a select signal. A flip-flop may be used to provide the select signal and to guard against false selection of slave clocks.

Abstract: In a multiplexor, respective outputs of two latches alternately brought into a dynamic holding condition at phases opposite to each other, respectively, are connected in common in a wired connection. Thus, a selector becomes unnecessary, with the result that the number of transistors driven with a clock signal can be reduced, and the electric power consumption is correspondingly reduced.

Abstract: A circuit and method are shown for a continuously adjustable delay circuit. The present invention utilizes two signal delay paths controlled by a tuning signal wherein each delay path receives a reference signal. The first delay path delays the reference signal in response to the tuning signal in a manner that is complementary to the manner in which the second delay path delays the reference signal in response to the tuning signal. By selecting one of the signal output by the first delay path and the signal output by the second delay path and switching between the two signals at a point when the two signals are separated by a period of the reference signal, a delay of the reference signal can be continuously adjusted.

Abstract: A method and apparatus for sequencing an integrated circuit which receives an external clock signal consists of the use of an internally generated random clock signal and of the use of either of these clock signals depending on the instruction to be performed.

Abstract: A first amplifier circuit having a high frequency characteristic and a second amplifier circuit having a low frequency characteristic have first and second input terminals, respectively. The first and second amplifier circuits have first and second feedback resistors for self-bias and first and second switching elements capable of interrupting outputs of the amplifier circuits, respectively. Between the first and second input terminals, a third switching element is connected. A device for controlling on and off of the switching elements is provided in order that according to a signal input to the first and second input terminals, the signal is transmitted to either the first amplifier circuit or the second amplifier circuit. As a result, irrespective of whether the front end has one output terminal or two output terminals, the input circuit can be connected to the PLL synthesizer IC as it is by connecting the output to the first input terminal or to the two input terminals.

Abstract: A multiplexer circuit in which high speed operation and high integration can be achieved by distributing the parasitic capacitance generated in the common output stage of pass transistor. A multiplexer circuit which outputs any one of input signals of 1 to n, input to the n pass transistors after selecting it at the common output stage, in response to the the selection signal of 1 to n (n=a natural number), comprising; input means receiving 1 to i input signals (1<i<n); a first switching means which select any one of the input signals in response to the 1 to i selection signals and output it to a first common output stage; a second switching means which select any one of the i+1 to n input signals in response to the i+1 to n selection signals and output it to a second common output stage; and an output means which has input stage connected to the first common output stage and output stage connected to the second common output stage and outputs the final output signal to the external circuit.

Abstract: An auto mode selector for a semiconductor memory device having a reference voltage selection switching circuit connected between a reference voltage pin and an internal reference voltage terminal, for selecting one of CTT and LVTTL in response to a reference voltage selection signal. The auto mode selector further includes an input leakage current controller for allowing current to flow through a resistor between a supply voltage source and the reference voltage pin only for a predetermined time period in response to an input leakage current control signal from an input leakage current control signal generator. According to the present invention, the amount of input leakage current and standby current can be reduced.

Abstract: A method and apparatus are provided which are implemented in a chip I/O buffer-multiplexor circuit or I/O buffer cell 201. The I/O buffer portion includes a receiver circuit 205 for receiving bus input signals to the buffered chip, and a driver circuit 203 for driving output signals from the buffered chip to a data bus. An integrated multiplexor or MUX circuit 207 selectively gates one of three possible signals to chip internal logic. The three signals applied to the MUX circuit include a boundary scan test signal BS MUX for testing scan points in an integrated circuit, a bypass Data In signal DI which is generated by chip internal drive logic, and a DQ signal received by the I/O buffer receiver circuit from a data bus. The data input node of the I/O buffer is wired directly to the new multiplexor data input. Additional control signals are provided for orthogonal selection of the three multiplexor data inputs.