Abstract: A six-input multiplexer is disclosed using only two transistors in the signal path from an input port to the output port. The multiplexer uses control signals that are not decoded. The multiplexer uses three control signals and requires that the control signal combinations 000 and 111 not be used. The other six control signal combinations 001, 010, 011, 100, 101, and 110 can be used to select between six input signals by placing only two transistors in the signal path, taking advantage of the fact that two of the three control signals are the same and the third is different from the other two. A compact layout results when two multiplexers use common input signals. According to another aspect of the invention, an interconnect structure is provided that includes two multiplexers, each multiplexer receiving an input signal from a buffered output of the other multiplexer.

Abstract: After a level of a selection signal C is changed, a currently output clock signal present at an output line is interrupted (set to be a low level) at the fall of the level of the currently output clock signal (A or B), and a switching operation is started. After the switching, the supply of an extracted clock signal to the output line is resumed when the level of the extracted clock signal (A or B) is changed. The best clock signal, which is synchronized with a plurality of source clock signals, can be provided to another system such as an IC card without increasing the number of parts. No noise is generated at a clock signal switching time, and the time required for switching can be kept to a minimum.

Abstract: An internal power control circuit for a semiconductor device allows easy testing of the internal circuit blocks or memory arrays at various voltage levels. In the semiconductor device, internal voltage switching circuits connected between the internal power supply line and each array power supply line are switched ON or OFF according to signals applied to control pads coupled to each internal voltage switching circuit. During normal operation, a power voltage generated by the internal voltage generator is applied through an internal power supply line to each array power supply line coupled to the internal circuit blocks. During a test operation, different power voltages may be applied to the control pads to selectively decouple individual array power supply lines from the internal power supply line, and selectively couple the power voltages applied to the control pads to the corresponding array power supply lines and internal circuit blocks.

Abstract: A differential comparison circuit obtains an improved common mode range with respect to the voltages on first and second inputs. A first comparator is activated when the first and second input voltages are above a first level. A second comparator is activated when the first and second input voltages are below a second level. The output of the comparator that is activated is selected for providing the comparison output signal. In this manner, the comparator having improved performance, typically in terms of differential input voltage sensitivity, may be selected for the voltages present at the inputs. In a typical embodiment, the first comparator uses n-channel input devices, and the second comparator uses p-channel input devices. The activation is provided by voltage level-sensing circuitry, and may include hysteresis to help ensure reliable operation.

Abstract: A method and a completely integrable circuit arrangement are proposed for recovery of a timing signal from a data stream. Two groups of phase regulators are supplied with a locally existing reference timing signal, preferably in each case one of mutually complementary reference timing signals. One phase regulator in each case, which has assumed a state within its operating range, is selected to provide the recovered timing signal, while a phase regulator which is currently not selected is kept in the state within its operating range which is diametrically opposite to the state of the currently selected phase regulator. On reaching the limit of the operating range of the currently selected phase regulator, a changeover is made to the phase regulator which has been kept ready until this point.

Abstract: A clock circuit for generating alternate clock phases (P.sub.1, P.sub.2) whose trailing edges define sampling points of an analog-to-digital converter (106). Complementary signals (CLOCK0, CLOCK1) are generated from a system clock (F.sub.SYS) and switched through transmission gates (340-341, 342-343) when an enable signal (V.sub.EN) is applied. The system clock (F.sub.SYS) is delayed by a delay circuit (316) to produce the enable signal (V.sub.EN) after the complementary signals (CLOCK0, CLOCK1) are stable, thereby synchronizing the complementary signals (CLOCK0, CLOCK1) with the enable signal (V.sub.EN).

Abstract: A clock distribution system in a reliable electronic system includes a predetermined number of clock signal load circuits, each having a clock signal input terminal. A first clock signal generator has the same predetermined number of clock signal output terminals coupled to the clock signal input terminals of the clock signal load circuits. A second clock signal generator also has the same predetermined number of clock signal output terminals which are also coupled to the clock signal input terminals of the clock signal load circuits.

Abstract: An input signal from a Dsub connector and BNC connectors is selected by an analog switch. The frequency of horizontal and vertical synchronizing signals applied from one connector end is measured by a synchronizing frequency detection circuit. The frequencies of horizontal and vertical synchronizing signals applied from the other connector end are converted into voltage values by F/V converters. A microcomputer determines the presence of a synchronizing signal and selects an input signal from the connector end of a high priority level set in a non-volatile memory.

Abstract: A switching circuit for switching between a main power supply and a battery power supply includes a comparator, a p-channel battery power transfer transistor, a p-channel main power transfer transistor and an inverter. The comparator operates on the main power supply and is connected on input to the main power supply and to the battery power supply. The comparator compares the voltage level of the main power supply with the voltage level of the battery power supply and provides a selection signal which is low when the voltage level of the battery power supply is higher than the voltage level of the main power supply. The p-channel battery power transfer transistor is controlled by the selection signal and transfers the battery supply signal to a switched power supply node. The inverter operates on the battery power supply and inverts the voltage level of the selection signal.

Abstract: An apparatus for multiplexing a pair of test clock signals and a pair of system clock signals onto a pair of output clock signals includes a first means for coupling a first test clock signal to a first output clock signal when a test mode control signal is active, for driving the first output clock signal to an inactive clock signal level when the test mode control signal transitions to an inactive state, and for coupling a first system clock signal to the first output clock signal beginning with a first full clock pulse of the first system clock signal which occurs after the test mode control signal transitions to the inactive state.

Abstract: A system for switching between a signal having delay paths of differing magnitudes without generating any glitches and false edges uses a no delay circuit for outputting a signal having no delay and a delay output circuit for outputting a delayed form of the signal. The signals are inputted to a multiplexer. The multiplexer will output at least one of the signals. Control circuitry is coupled to the multiplexer for signalling the multiplexer to output at least one of the signals. The control circuitry will control the switching of the multiplexer so that when the output of the multiplexer switches from a signal having no delay to a delayed form of the signal, or when the output of the multiplexer switches from a delayed form of the signal to a signal having no delay, no glitches or false edges are generated.

Abstract: A bi-directional high-voltage RESURF EDMOS (REduced SURface Extended Drain MOS) transistor which can endure a high voltage at its source by providing drift regions at both sides, i.e., the source and drain of the conventional RESURF LDMOS (Lateral DMOS) transistor, and exchanging the drain and the source when an analog signal of high voltage is inputted. Further, the bi-directional high-voltage RESURF EDMOS transistor provides a high-voltage analog multiplexer circuit employing a RESURF EDMOS transistor which is capable of reducing the number of necessary high-voltage elements and performing a stable operation, by constructing a high-voltage analog multiplexer having at least three inputs and a multistage high-voltage multiplexer circuit of push-pull type, pass transistor type, and combined form of push-pull type and pass transistor type by using the bi-directional high-voltage RESURF EDMOS transistor.

Abstract: An internal clock generating circuit for data output buffers of a synchronous DRAM device, which produces an internal clock with reference to either the positive edge or the negative edge of the system clock CLK by comparing the reference time t.sub.CLref(OH) for insuring a low level time tCL of the system clock CLK and output hold time t.sub.OH, and which can sufficiently insure the data output setup time t.sub.OS and data output hold time t.sub.OH regardless of the frequency of the system clock by making the generation points of the internal clock to be varied depending on the frequency of the system clock.

Abstract: A clock circuit for providing an integrated circuit with a high accuracy, crystal oscillator clock which interfaces to an "off-chip" crystal to provide a high accuracy clock signal while an internal, low power oscillator provides a low power clock source. Either clock may be selected to drive a programmable processor under program control. When high accuracy and stability are required, the crystal oscillator may be chosen as the processor clock, and when lower power is desired, the low power oscillator may be chosen as the processor clock while the high accuracy clock is disabled. The high accuracy oscillator is used to clock a first timer circuit, while the low power oscillator is used to clock a second timer circuit. The second timer circuit output, in turn, is synchronized to the processor clock so that the programmable processor can utilize the second timer circuit even when the processor clock is asynchronous to the second timer circuit.

Abstract: A dynamic latching arrangement with a conditional driver, a system, and a method reduce power consumption, increase operating speed, and reduce the number of discrete components. The conditional driver selectively impresses a signal on an internal node of the circuit such that when a control signal is asserted, a signal related to the clock signal is generated, but when the control signal is not asserted, a different signal related to the clock signal is generated.

Abstract: A clock failure detection circuit which monitors a clock by comparing the clock to at least one delayed version of itself is provided. The original clock and the delayed version will be offset, such that an edge of one of them can clock a logic circuit to determine if the clock is at the proper level. By setting up the delay so that a clock edge is generated when the clock signal should be low, for instance, a bad output signal will be provided whenever the clock is high instead. This could be caused by the clock being stuck high, or by an irregular pulse width.

Abstract: Generator of clock pulses having a period selectable between a first period, a second period of greater duration than that of the first period and a third period, with duration imposed by the transitions of a synchronization signal (SYNC) from a first to a second logic level, comprising: a resettable oscillator controlled by a binary selection signal having a first and second logic level, in order to generate periodic pulses having the first or second period depending on the logic level of the said selection signal, the oscillator comprising a pulse extractor triggered by the periodic pulses and by the transitions from first to second logic level of the synchronization signal in order to generate, with each pulse and transition received as input, one of the said periodic clock pulses, acting as reset signal for the oscillator, and a finite state logic machine, having at least two states A, B and inputs for receiving the synchronization signal and the periodic pulses, and generating the selection signal at a f

Abstract: A quadrant detector circuit (400) has a comparator (442) having a pair of inputs (438, 440). A first (438) of the pair of inputs (438, 440) is coupled to an in-phase signal (434) and a second (440) of the pair of inputs (438, 440) is coupled to a quadrature phase signal (436). A sample counter (448) has a reset (446) coupled to an output (444) of the comparator (442). A controllable switch (456) has a selection input (454) coupled to an output (452) of the sample counter (448). The controllable switch (456) is capable of switching between a local oscillator signal (458) and an inverse local oscillator signal (460).

Abstract: A circuit and method for switching between different frequency clock domains that are out of phase. The circuit has a select input for selecting which frequency domain is to be output, a first circuit associated with the first clock domain, and a second circuit associated with the second clock domain. The first and second circuits are responsive to the select input and work together to disengage the first clock before the second clock is engaged.

Abstract: A current mode analog signal multiplexor includes multiple input multiplexed differential amplifiers, and an output differential current amplifier. An input multiplex control signal selects and enables one of the input multiplexed differential amplifiers for buffering and steering the input signal current to one side of the output differential current amplifier. The reference amplifier drives the other side of the output differential current amplifier. The output node of the output differential current amplifier remains at a substantially constant voltage potential while providing an output current which varies in relation to the selected input signal.

Abstract: The clock rate for a device is controlled through the use of integrated circuits which respond to the temperature of the device. Circuitry is added to the integrated circuit device being controlled which changes the clock rate of the device as the device temperature changes. The device clock is thus regulating by the temperature of the device. The way in which the regulation is implemented can be varied, from slowing an internally generated clock rate, or by digitally scaling an external clock input. Synchronous scaling is also provided, such that devices which are connected external to the CPU can still be clocked at the same external rate, but CPU transactions within the CPU may occur at a different rate depending on the CPU's measured temperature. This invention also provides the ability to selectively reduce or stop certain areas of an integrated circuit relative to pending operations or instructions being executed.

Abstract: A minimal logic multiplexer system using tri-state drivers with one-hot enabling lead, provides high-speed access to processor elements by any one of a plurality of control units. The multiplexer system is implemented in a manner that minimizes the circuit implementation, minimizes gate delay within the circuit implementation, and allows processing instructions to pass from a control unit to the processor elements by way of multiplexed control lines therebetween. The multiplexer system contains control unit gate groups that are enabled and disabled in parallel by a select lead. Each control unit gate group can be implemented internal to the respective control unit or external in a common intermediary multiplexer circuit location.

Abstract: A switching circuit for switching between a main power supply and a battery power supply only after first power up includes a switch, a first power up transfer transistor and a first power up latch. The switch switches between the main and battery power supplies and provides one of the main and battery power supplies to a switched power supply node. The first power-up transfer transistor is connected on input to the switched power supply node. The first power up latch is powered by a switched power supply from the switched power supply node and is connected on output to a gate of the first power-up transfer transistor. The first power up latch produces an activation signal to the gate upon and after first power up of the main power supply.

Abstract: A configurable circuit includes a first subcircuit (206) and a second subcircuit (410) each having a static power dissipation. A first bias circuit (402), coupled to the first subcircuit (206), provides a first bias level to the first subcircuit (206). Similarly, a second bias circuit (412), coupled to the second subcircuit (410), provides a second bias level to the second subcircuit (410). A logic circuit (403) is coupled to the first bias circuit (402) and the second bias circuit (412) and selectively provides a first signal to the first bias circuit (402). In response to the first signal, the first bias circuit (402) changes the bias level provided to the first subcircuit (206). The changed bias level disables the first subcircuit (206), substantially reducing the static power dissipation of the first subcircuit (206) while allowing the second subcircuit (410) to continue operating. In one embodiment, the circuit is a crosspoint switch with multiplexer subcircuits.

Abstract: A timer which provides both the surveying and counting functions. It contains a counter, a multiplexer, an edge-triggered controller, a time-base latching circuit, and a pulse-detecting circuit. It not only can be used as a timer, but can also be used as a counter to count the number of the external signals so as to detect the width of an external signal.

Abstract: This invention provides a frequency converting circuit that does not require balance adjustment, can be used in a broad frequency band, and is well-suited to implementation in the form of an integrated circuit. A first input signal undergoes a phase shift into 2.sup.o (where n is a natural number of 2 or greater) respective channel signals, each with a different phase, for output. A second input signal is used to generate switch signals 10 numbered 1 . . . n. The 2.sup.n channel signals are switched according to the first switch signal, reducing the number of channels by 1/2, for output. The output of the (m-1) th switch (where m is a natural number of 2 . . . n) is switched according to the mth switch signal, reducing the number of channels by 1/2 for output, at switch m. This process is repeated continuously from switches 2-n until the signal is output as a single channel signal.

Abstract: A pin-configurable frequency synthesizer for providing a choice of physical pin assignments/configurations without costly design and/or bonding changes. A functional block, having a plurality of functional conductors, is provided. The pin-configurable frequency synthesizer is housed in a chip package that includes a plurality of physical pins. A configuration matrix having a plurality of transmission circuits for connecting the functional conductors to the physical pins is also provided. A control circuit for controlling the transmission circuits of the configuration matrix is further provided. This control circuit includes programming logic and a logic array for generating control signals for each of the transmission circuits of the configuration matrix. These control signals direct the transmission circuits to selectively couple each functional conductor to a respective physical pin in accordance with a desired pin assignment.

Abstract: A circuit for detecting timing errors and for selecting the correct clock edge for mid-point data sampling, includes a rising edge sampling device for sampling an input data signal at a rising edge of an input clock and generating a first interim data signal. A falling edge sampling device samples the input data signal at a falling edge of the input clock and generates a second interim data signal. An error signal generation devise, arranged in each of the rising edge and falling edge sampling devices, generates an error signal if designated setup time and hold time requirements are not met. The error signal is one of an error-rise or error-fall signal. A state machine receives the first and second interim signals and the error signal. The state machine automatically outputs the first interim data signal to a logic device if the error-fall signal is detected, and outputs the second interim data signal to the logic device if the error-rise signal is detected.

Abstract: An apparatus controls the operation mode of a time division switching device selected from two incorporated in an electronic switching system for reliability thereof. Mode information representing previous operation modes of the two time switching devices is received and processed to issue a first and a second mode control signals. Thereafter, status of each component in the selected switching device and a power from a power supply in the unselected switching device are analyzed to produce each component status information and power status information. Next, an initial duplexing control signal is obtained based on each component status information, the first and the second mode control signals, and the power status information.

Abstract: A method and circuit in which one of at least two asynchronous constant frequency input clock signals is selected for being used as an output clock signal by use of a separate selection signal for providing redundancy for an asynchronous clock signal.

Abstract: A voltage reference circuit includes at least a first and a second voltage supply having different operating temperature ranges. Output voltages of the two voltage supplies are compared and one of the supplies is selected to provide an optimum voltage reference.

Abstract: A signal reception apparatus has an automatic level selection function. A comparing circuit compares a level of an input signal with a plurality of sensing levels and outputs a plurality of sensing signals in accordance with the compared result. An auto select level controller receives the plurality of sensing signals from the comparing circuit and selects one of the plurality of sensing levels in response to the plurality of sensing signals. The auto select level controller includes a plurality of flip flop stages. Each of the plurality of flip flop stages has a plurality of flip flops connected in series and is coupled to a corresponding one of the plurality of sensing signals from the comparing circuit. A circuit receives the output signals from the plurality of flip flop stages and selects one of the plurality of sensing levels in response to the inputted sensing signals.

Abstract: Several users emit their own selection signal and clock signal to their respective selection circuits. The selection circuits send selection criteria to all other selection circuits and the clock switching stage. The selection circuit sends an activity signal to a digital circuit based on the allocated user's selection signal, the selection criteria of all the other selection circuits and the selected clock signal.

Abstract: A clock signal generator can prevent unnecessary power consumption and can lower the power consumption of a system or a chip as a whole. A clock generator has a plurality of multipliers having variable multiplying factors and multiplying a single input reference clock signal by a designated multiplying factor. A plurality of frequency dividers have variable divide factors and divide a clock signal by a designated dividing factor. A clock selector selects a clock signal which has a required frequency according to a status signal STS from each of the functional locks from among the clock signals having a plurality of frequencies generated by the clock generator. The clock selectors stops the operation of the multipliers or the frequency dividers which are generating unused frequencies by switching clock signals.

Abstract: A satellite broadcast receiving system in which, when each receiver transmits a control pulse to a change-over divider via a signal cable, the change-over divider selects a desired broadcast signal in response to the control pulse, which is led to its output terminal, then transmitted to each receiver via the signal cable.

Abstract: A high input impedance CMOS multiplexor. A buffer stage is connected to common outputs of a plurality of N-channel multiplexor switches. A pull up P-channel transistor in this buffer is connected to a voltage source which is equal to the maximum voltage output from one of the plurality of N-channel multiplexor switches. As such, the buffer output can be fully shut off when a logic "1" is output by one of the multiplexor switches. The input impedance of the multiplexor is approximately the input impedance of the buffer or approximately 10.sup.14 ohms.

Abstract: A clock switching circuit responsive to at least one clock select signal switches to a selected one of a plurality of clock signals while minimizing transients generated during the switching. The circuit includes at least one flip-flop receiving a corresponding one of the at least one clock select signal; a plurality of flip-flops individually receiving an output of a corresponding one of the at least one flip-flop, and an inverted version of a corresponding one of the clock signals; a plurality of AND gates individually receiving the output of a corresponding one of the at least one flip-flop, the output of a corresponding one of the plurality of flip-flops, and a corresponding one of the plurality of clock signals; and an OR gate receiving the outputs of the AND gates so that the selected one of the plurality of clock signals is provided at an output of the OR gate, and fed back to an inverted clock input of the at least one flip-flop.

Abstract: A time domain multiplexer system with automatic determination of acceptable multiplexer output limits, error determination, or correction is comprised of a time domain multiplexer, a computer, a constant current source capable of at least three distinct current levels, and two series resistances employed for calibration and testing. A two point linear calibration curve defining acceptable multiplexer voltage limits may be defined by the computer by determining the voltage output of the multiplexer to very accurately known input signals developed from predetermined current levels across the series resistances. Drift in the multiplexer may be detected by the computer when the output voltage limits, expected during normal operation, are exceeded, or the relationship defined by the calibration curve is invalidated.

Abstract: A system clock generating circuit for supplying a system clock to a microproeessor, includes a first oscillator for generating a main clock, and a second oscillator for generating a sub clock which is lower in frequency than the main clock. A twin-clock control circuit receives the main clock and the sub clock and is controlled by the microprocessor. When the microprocessor is in an ordinary operating condition, the twin-clock control circuit generates a (n)-phase system clock which is composed of (n) clocks for each one instruction cycle, where "n" is a positive even number. When the microprocessor is in an electric power saving mode, the twin-clock control circuit also generates a (n/m)-phase system clock which is composed of (n/m) clocks for each one instruction cycle, where "m" is a positive even number but is smaller than "n".

Abstract: A glitchless clock switching circuit utilizes a clock select input signal to determine which one of a plurality of clock input signals will be switched onto a clock output line. The clock select input signal and the multiple clock input signals may be completely asynchronous to each other.

Abstract: A simple structure for switching between two clock signals to produce an output without a glitch or short pulse. The invention is basically a three-input multiplexer controlled by a modified two-bit state machine. The state machine includes flip-flop memories which are driven by the two different clocks, as opposed to using a single clock as in a traditional state machine. The state machine output is used to control the three-input multiplexer, selecting between the first clock, the second clock and an intermediate high level signal during transition. The intermediate high level signal bridges the gap between pulses, eliminating any short glitches.

Abstract: A multi-clock controller circuit includes first and second inputs to which two different types of clocks, such as a crystal oscillator clock and a TTL clock, can be applied. The circuit automatically senses which of the two input clock signals is active and provides that clock signal to an output of the circuit. Power up and power down conditions are achieved without generating non-standard clock pulses on the output through use of a synchronizer stage comprising a plurality of flip flops which determines the number of input clock cycles which are received by the circuit before output clock signals for power up or power down conditions commence.

Abstract: An internal clock generation circuit is provided for receiving an external clock signal. Based upon the duration of each high and low pulse width of the external clock signal, the internal clock generation circuit selects one of two possible clock signals as an internal clock signal for connection to a load device. Selection is based upon whether the high and low pulse durations of the external clock signal exceed or are less than a threshold amount. If exceeded, the external clock signal connects a longer duration pulse width internal clock signal to the load device. If less than, the internal clock signal connects a shorter duration internal clock signal to the load device. Accordingly, the internal clock generation circuit allows for variability in the external clock signal frequency and duty cycle and correspondingly selects one of two (and possibly more) clock signals for connection to the load device.

Abstract: A clock change circuit contains: a clock gate unit for receiving first and second clock signals, and detecting a timing at which both the first and second clock signals are at an inactive level to output an active timing signal indicating the timing; a delay unit for inputting a select control signal and the timing signal, and outputting a delayed select control signal the state of which is changed to the same state of the select control signal after the active timing signal is received from the clock gate unit; and a select unit for inputting the first and second clock signals, and selects one of the first and second clock signals according to the delayed select signal to output the selected clock signal.

Abstract: A memory device, with increased storage speed and enhanced memory utilization, can be implemented by using multiplex clocking and efficient device design and enhanced flip-flop utilization. Transit time through the circuit, and hence circuit speed, can be controlled through multiplexed clock signals, and is increased by using fewer transistors in the signal path and allowing data to be transmitted directly to the flip-flop output by bypassing the flip-flop's master latch input.

Abstract: A multiplexer includes three switching divisions each of which has one terminal connected to each of the signal terminals and the other terminal connected to a fourth switching division. A signal inputted through the selected signal terminal is outputted from the other signal terminal to the exterior by operating the fourth switching division.

Abstract: A satellite broadcast receiving system is disclosed, in which when each receiver transmits a control-pulse to a change-over divider via a signal cable, the change-over divider selects a desired broadcast signal in response to the control pulse, which is led to its output terminal, then transmitted to each receiver via the signal cable.

Abstract: A digital input circuit including a first digital buffer for receiving a digital data signal and for providing a first buffered digital data output, the first digital buffer having a first switching threshold voltage; a second digital buffer for receiving the digital data signal and for providing a second buffered digital data output, the second digital buffer having a second switching threshold voltage that is greater than the first predetermined switching threshold voltage; a selection circuit responsive to the first buffered digital data output and the second buffered digital data output for providing a selection circuit output that is a replica of the first buffered digital data output or the second buffered digital data output; and a flip-flop for receiving the selection means output and providing a flip-flop output that is indicative of the logical state of the digital data signal.

Abstract: A signal switching circuit is provided to output signal switching between a first and a second input signal. The circuit includes a first analog switch transistor, a first switch transistor, a second analog switch transistor, a second switch transistor and a third switch transistor. The interference between the first input signal and the second input signal is reduced to a possible minimum through the invention.

Abstract: A circuit for selecting between two states and using the same pin as an input and an output. On power-up, the pin can be connected to either a grounded resistor (to select the first state) or the power supply (to select the second state). The input signal generates a logic select signal. The logic select signal selects between first and second logic formats. If the first format is selected, the pin is used to output a reference voltage for that format. If the second format is selected, the logic select signal also provides a disable signal, that prevents the reference voltage output from appearing on the pin.