Abstract: The invention relates to a method for the closed-loop control of a proportional integral-type controller (2) in an instrumentation and control device (1) of a closed-loop control system (3), in particular a servovalve-actuator system, said controller (2) including a setpoint-weighting coefficient (?), said closed-loop control method comprising the consecutive steps of assigning (11) a unit value to the set-point weighting coefficient (?), optimizing (12) a closed-loop control of the controller (2) satisfying at least one predefined performance criterion, defining a characteristic tracking error (?TC) making it possible to respond to the performance constraints of the system to be closed-loop controlled, and assigning (132) a setpoint weighting coefficient (?) value, depending on the characteristic tracking error (?TC) and the closed-loop control of the controller (2).

Abstract: A parallel phase shift circuit is configured to perform a phase shift process in parallel on an input signal pair including a first I signal orthogonal to a first Q signal, in accordance with a phase difference among a set of n multi-phase separation frequency signal pairs including a set of second I signals orthogonal to a set of second Q signals, to generate a set of n phase-shifted orthogonal signal pairs including a set of third I signals orthogonal to a set of third Q signals; and a phase discrete continuous measurement circuit configured to, based on the n phase-shifted orthogonal signal pairs from the parallel phase shift circuit, generate a set of discrete signals being n discrete values and generate a set of continuous tangent signals being a set of a desired number of signals interpolating the set of discrete signals.

Abstract: A filtering device includes a low-pass filter (LPF), a noise estimation circuit and a first combining circuit. The LPF receives and filters a pre-filtering signal to generate an output signal of the filtering device. The noise estimation circuit estimates an estimated noise signal according to the output signal and the pre-filtering signal. The first combining circuit subtracts the estimated noise signal from an input signal of the filtering device to generate the pre-filtering signal.

Abstract: A locator for locating power outlets and power receivers. A sensor is provided in a power receiver for detecting a detection signal emitted by a remote power outlet. A processor uses the detected signal to compute location coordinates of the power outlet.

Abstract: A crystal-free radio includes an antenna; a receiver configured to communicate with the antenna; a local radio frequency (RF) oscillator configured to communicate with the receiver; and a clock circuit configured to communicate with the receiver and the local RF oscillator, the clock circuit having an electronic circuit oscillator. The local RF oscillator is a free-running oscillator. The clock circuit is configured to receive a calibration signal via a wireless network and calibrate the electronic circuit oscillator based on the received calibration signal, and the clock circuit is a crystal-free clock circuit.

Abstract: An integrated circuit is described herein. In accordance with one embodiment, the circuit includes a voltage controlled oscillator (VCO) that is configured to receive a tuning voltage at a tuning input and to provide an RF oscillator signal at an oscillator output. The circuit further includes a first and a second switchable resistor network. The first switchable resistor network includes at least a first resistor and at least a first switch and is connected between the tuning input of the VCO and a first node, which operably provides a first voltage. The second switchable resistor network includes at least a second resistor and at least a second switch and is connected between the tuning input of the VCO and a second node, which operably provides a second voltage.

Abstract: A technique that reduces or eliminates trading-off power amplifier efficiency and costly external filtering in amplitude and phase modulated sinusoidal signal generation uses multi-phase outphasing and a multi-phase switching mode power amplifier to generate the amplitude and phase modulated sinusoidal signals. The technique combines multiple clock phases with sinusoidally weighted circuits of the switching mode power amplifier to improve amplitude and phase modulated sinusoidal signal generation.

Abstract: A reference oscillator arrangement is provided for a communication apparatus capable of communicating according to a plurality of transport formats. The reference oscillator arrangement comprises a reference oscillator controller; a resonator core comprising a reference resonator and a driving circuit for the reference resonator, wherein the resonator core is arranged to provide an oscillating signal at a frequency of the reference resonator; and a reference oscillator buffer arrangement, connected to the resonator core, comprising an active circuit arranged to provide a reference oscillator output based on the oscillating signal. The reference oscillator controller is arranged to receive information about an applied transport format and control the driving circuit and/or the active circuit based on the information about the applied transport format. An oscillator arrangement, a communication device, methods therefor and a computer program are also disclosed.

Abstract: A phase lock loop (PLL) includes: a binary phase detector configured to generate a first and second polarity signals that respectively indicating whether an incoming data stream is leading a feedback signal, or whether the feedback signal is leading the incoming data stream, wherein a difference between the first and second polarity signals does not represent an amount of phase difference between the incoming data stream and the feedback signal; a digital filter configured to: generate filtered first polarity signal on a first path and a second path that are different; and generate filtered second polarity signal on a third path and a fourth path that are different; a charge pump coupled to the digital filter and configured to: integrate the filtered first polarity signal and the filtered second polarity signal; and an oscillator configured to generate the synthesized clock signal serving as the feedback signal.

Abstract: The present application relates to a near field communications (NFC) reader which includes an amplifier that drives an antenna. Capacitors of fixed value are connected in series between differential outputs of the amplifier and inputs of the antenna and form a series resonant circuit with the impedance of the antenna. Variable capacitances are provided in series with the fixed value capacitors, and the capacitance of these variable capacitances can be adjusted to compensate for manufacturing tolerances in the fixed value capacitors which cause a frequency offset between a desired resonant frequency of the series resonant circuit its actual resonant frequency, and to compensate for changes in the input impedance of the antenna that occur as the distance between the antenna of the reader and an antenna of an NFC tag changes.

Abstract: An inductive power receiver configured for receiving power transferred from an inductive power outlet having a primary coil includes a secondary coil configured to form an inductive couple with the primary coil thereby facilitating the power transfer. The inductive power receiver further includes a transmission circuit having a variable amplifier configured to vary the voltage of the power drawn by the secondary coil, and a modulator configured to control the variable amplifier. The inductive power receiver is configured to modulate a signal by the varying of the voltage. An inductive power outlet configured for transferring power to the inductive power receiver includes a primary coil and a receiving circuit configured to detect changes in voltage of the power transferred and to produce an output signal based on the changes.

Abstract: An on-chip frequency calibration apparatus is described. A ring oscillator generates a clock signal. A trimmable resistor is coupled to the ring oscillator. A frequency detector detects the frequency of the clock signal generated from the ring oscillator. The frequency detector includes a frequency divider component that divides the frequency of the clock signal by a predetermined number to derive an output signal having a pulse duration that is equal to at least one period of the clock signal, a capacitor, a capacitor charging current source, and a capacitor charge transistor directs a charging current generated from the capacitor charging current source to the capacitor as a function of the output signal generated from the frequency divider component. A resistor trimming unit trims the trimmable resistor in response to determining that the frequency detected by the frequency detector is less than a target frequency threshold.

Abstract: A soft error protection device includes a soft error resilient latch (SERL) and a latch coupled to a detection device and receiving a soft error pulse and a clock (CLK) signal respectively outputted by an electronic element and a CLK generator. The SERL delays the soft error pulse. In the period of a negative level of the CLK signal, the SERL stores the delayed soft error pulse corresponding to the negative level and used as a first detection data. Meanwhile, the latch stores the soft error pulse as a second detection data. The detection device receives the CLK signal, the first and second detection datum, and compares the first and second detection datum to send out a detection signal when the CLK signal rises from the negative level to a positive level.

Abstract: Circuit for processing an input signal based on at least one reference signal, comprising a phase locked loop demodulator configured to receive a speed control signal and said input signal and further configured to follow a frequency and/or a phase of said input signal at a speed, wherein said speed depends on said speed control signal; and a reference signal detector configured to determine said at least one reference signal and to set said speed by outputting said speed control signal to said phase locked loop demodulator, wherein, if said reference signal detector detects said at least one reference signal, said reference signal detector decreases said speed.

Abstract: A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a Digitally Controlled Oscillator (DCO) output signal and a reference clock and outputs a first stream of digital values. The TDC is clocked at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate.

Abstract: A receiver is provided. The receiver includes a differential amplifier amplifying differential input signals input to input terminals and outputting differential output signals through output terminals and an oscillator connected to the output terminals of the differential amplifier. The differential amplifier and the oscillator operate alternatively in response to an enable signal.

Abstract: An oscillator unit is configured such that a frequency adjustment unit of a synthesizer used by a controller is smaller than a frequency variation tracking capability of a demodulator connected to an output side of a frequency converter. This structure successfully combines the temperature compensation control of an oscillator unit and the receiving process of a high-frequency receiving device. Accordingly, an oscillator unit with large temperature coefficient is applicable to high-frequency receiving devices.

Abstract: A receiver includes a band-pass filter that limits a passband of an IF (Intermediate Frequency) signal, an FSK detector that detects the IF signal passing through the band-pass filter to generate a detection signal, and a control block that controls a modulation sensitivity of the FSK detector and a pass bandwidth of the band-pass filter, in which the control block controls the modulation sensitivity of the FSK detector according to the pass bandwidth of the band-pass filter.

Abstract: In one implementation an output signal of an oscillator is varied to be within a desired frequency band with respect to a reference signal, the output signal having a plurality of phases. The implementation may include comparing the output signal with the reference signal, counting falling edges about each phase of the number of phases in a predetermined time period and summing to define a count output; comparing the count output with a product of the number of phases of the output signal and the factor to define a comparison, generating a control signal based upon the comparison, and inputting the control signal to the oscillator to alter the output signal thereof.

Abstract: A reception device that receives a modulation signal being a result of digital modulation of a carrier is disclosed. The device includes: a demodulation section that demodulates the modulation signal into a demodulation signal including an I component and a Q component; a numerically controlled oscillation section that generates a signal of predetermined phase; a phase error detection section that detects a phase error between a phase of a symbol of the demodulation signal and the predetermined phase of the signal generated by the numerically controlled oscillation section; a phase rotation section that rotates the phase of the symbol of the demodulation signal in accordance with the phase error; a loop filter that filters the phase error, and controls the numerically controlled oscillation section; and a gain control section that controls a gain of the loop filter based on a modulation technique of the modulation signal.

Abstract: An oscillator unit is configured such that a frequency adjustment unit of a synthesizer used by a controller is smaller than a frequency variation tracking capability of a demodulator connected to an output side of a frequency converter. This structure successfully combines the temperature compensation control of an oscillator unit and the receiving process of a high-frequency receiving device. Accordingly, an oscillator unit with large temperature coefficient is applicable to high-frequency receiving devices.

Abstract: An oscillator unit is configured such that a frequency adjustment unit of a synthesizer used by a controller is smaller than a frequency variation tracking capability of a demodulator connected to an output side of a frequency converter. This structure successfully combines the temperature compensation control of an oscillator unit and the receiving process of a high-frequency receiving device. Accordingly, an oscillator unit with large temperature coefficient is applicable to high-frequency receiving devices.

Abstract: A communication device uses a local clock generator to regenerate the carrier frequency of the reference signal from a remote communication. In particular, a closed loop is used to self-calibrate the local pulse till the frequency is fixed to be within a fixed frequency margin. Once the local pulse is obtained, the demodulator will use the local pulse to demodulate the reference signal to generate the data signal.

Abstract: A method and apparatus for demodulating an input signal in a selectable intermediate frequency system is disclosed. The apparatus includes a front end module, a filter, and a phase lock loop (PLL). The front end module mixes the input signal with an oscillating signal. The filter includes at least one characteristic that is selectable to configure an intermediate frequency. The PLL demodulates an output frequency based on the output of the filter.

Abstract: A method and apparatus for automatic frequency correction in a demodulation circuit. The apparatus includes a demodulator, a frequency offset estimator, a frequency controller, and an oscillator. The oscillator provides a receiver clock signal which the demodulator employs to demodulate a modulated signal. The frequency offset estimator estimates an offset between a carrier wave frequency of the modulated signal and a frequency of the receiver clock signal. The frequency controller provides a frequency control signal to the oscillator for adjusting the frequency of the receiver clock. While the estimated offset is outside of an adjustment range, the frequency controller maintains the frequency control signal at its previous value. The frequency controller also adjusts the adjustment range based on past error signal values.

Abstract: A technique includes providing a plurality of local oscillator signals such that each of the local oscillator signals has a different phase. The technique includes providing scaling units to scale the input signal pursuant to different scaling factors to generate scaled input signals. The scaling factors are selected on a periodic function of the phases. The technique also includes providing mixing circuits to mix the local oscillator signals with the scaled input signals to generate mixed signals and providing an adder to combine the mixed signals to generate an output signal.

Abstract: A method and apparatus for demodulating an input signal in a selectable intermediate frequency system is disclosed. The apparatus includes a front end module, a filter, and a phase lock loop (PLL). The front end module mixes the input signal with an oscillating signal. The filter includes at least one characteristic that is selectable to configure an intermediate frequency. The PLL demodulates an output frequency based on the output of the filter.

Abstract: A combined PLL and ALL module for switching FM signals includes a PLL unit and an ALL unit electrically connected therewith. The PLL unit is used to initially process FM signals received from a co-channel. Outputs of the PLL unit are sent to the ALL unit and processed therein. The PLL unit and the ALL unit are controlled to process the FM signals by adjusting the ratio of second amplitude to first amplitude to closely approach a predetermined value such that the two FM signals are switched.

Abstract: Digital data receiver synchronization is provided with composite phase-frequency detectors, mutually cross-connected comparison feedback or both to provide robust reception of digital data signals. A single master clock can be used to provide frequency signals. Advantages can include fast lock-up time in moderately to severely noisy conditions, greater tolerance to noise and jitter when locked, and improved tolerance to clock asymmetries.

Abstract: A receiver to process a RF input signal having a plurality of channels includes a direct down conversion circuit, a demodulation circuit, and a local oscillator circuit. The direct down conversion circuit provides a downconverted signal based on the RF input signal and a local oscillator signal. The demodulation circuit receives the downconverted signal and provides a demodulated signal. The local oscillator circuit sets a frequency of the local oscillator signal based on a selected channel of the plurality of channels.

Abstract: A multi-band electronic apparatus and method thereof is provided. The method comprises outputting a first output signal in the first band by a first voltage controlled oscillator according to a switch control signal and a control voltage, outputting a second output signal in the second band by a second voltage controlled oscillator according to the switch control signal and the control voltage, the second band being not completely overlapped by the first band, performing frequency division selectively on the first output signal or the second frequency divided signal according to the switch control signal, and outputting a first frequency divided signal, determining a phase difference between the first frequency divided signal and a reference signal to output a phase difference signal, outputting the control voltage according to the phase difference signal, and selectively driving the first or the second voltage controlled oscillators by the control voltage according to the switch control signal.

Abstract: In a timing component extractor for a digital modulated signal, a frequency converting section 30 receives a complex baseband signal having a symbol rate fs and formed from an I signal and a Q signal, and converts frequency components ±fs/2, which are present in the complex baseband signal as the data changes, to frequency components ±fs/4. The I signal and Q signal of the complex baseband signal are then nonlinearly processed. In other words, multipliers 31, 32 square the I signal and the Q signal, respectively, and an adder 33 adds the respective results of the multipliers 31, 32. A BPF 34 extracts the frequency components ±fs/2 from the output of the adder 33, and outputs the extracted frequency components ±fs/2 as a timing signal. Accordingly, processing can be conducted at a sampling frequency which is twice the symbol rate fs. Moreover, timing extraction can be stably conducted without being affected by a carrier frequency offset.

Abstract: A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase between a complex digital input signal and a complex digital feedback signal. The phase error is input to a controller, which multiplies the phase error by a gain factor selected to stabilize and optimize the phase locked loop and produces an output signal for use in extracting a frequency deviation present in the complex digital input signal. The output signal is also input to a numerically controlled oscillator that tracks the phase of the complex digital input signal based on the output signal and produces the complex digital feedback signal.

Abstract: Circuit for processing an input signal based on at least one reference signal, comprising a phase locked loop demodulator configured to receive a speed control signal and said input signal and further configured to follow a frequency and/or a phase of said input signal at a speed, wherein said speed depends on said speed control signal; and a reference signal detector configured to determine said at least one reference signal and to set said speed by outputting said speed control signal to said phase locked loop demodulator, wherein, if said reference signal detector detects said at least one reference signal, said reference signal detector decreases said speed.

Abstract: A demodulation device (1) in semiconductor technology is disclosed. The device (1) is capable of demodulating an injected modulated current. The device (1) comprises an input node (IN1), a sampling stage (DG1, IG1, GS1 IG2, DG2) and at least two output nodes (D1, D2). The sampling stage DG1, IG1, GS1, IG2, DG2) comprises transfer means (GL, GM, GR) for transferring a modulated charge-current signal from the input node (IN1) to one of the output nodes (D1, D2) allocated to the respective time interval within the modulation period. The small size and the ability to reproduce the device (1) in standard semiconductor technologies make possible a cost-efficient integration of the device (1).

Abstract: Systems and methods for aligning the phase of a PLL with an incoming data signal. In one embodiment, when a data signal is received in a PLL, a phase perturbation signal is generated and injected into the PLL. The PLL then performs a phase alignment procedure to lock on to the received data signal. The phase perturbation signal is a damped sinusoidal oscillation that is injected into the PLL when each of a plurality of data packets is received. The perturbation signal has an amplitude sufficient to bump the PLL out of a quasi-stable state around 180 degrees out of phase with the incoming data signal, but is damped to less than a degree of phase shift within 30 ns of being injected.

Abstract: The invention relates to a demodulator to demodulate frequency-modulated signals FM including a phase locked loop PLL including at least a phase detector, a loop filter and a voltage controlled oscillator function VCO?, characterized in that said voltage controlled oscillator function VCO? has modifiable gain. The invention allows to eliminate drawbacks presented by the conventional use of a complex gain modifiable amplifier at the input of demodulated signal processing means. Application: demodulation of modulated signals: wireless phone, home network.

Abstract: A phase locked loop circuit comprising a phase detector having a first input for receiving a first frequency signal and an output, a first filter adapted to filter the output electric signal of the phase detector, a voltage controlled oscillator adapted to generate a second frequency signal in response to the output filtered signal of the phase detector. The phase detector has a second input for receiving the second frequency signal and is adapted to compare it with the first frequency signal. The circuit comprises means adapted to amplify the difference between an electric signal coupled with the output of the phase detector and a reference electric signal and a second filter adapted to receive the output electric signal of the amplification means and to send an output electric signal to the voltage controlled oscillator. The circuit comprises further means adapted to modify the value of the electric signal in input to the second filter to decrease the response time of the second filter.

Abstract: The present invention comprises systems and methods for electrical power regulation and distribution. In an embodiment, a system includes a modulator coupled to the source that receives an unregulated output waveform and is operable to produce a first composite waveform, and a mixing unit that is operable to generate a second composite waveform by introducing a frequency modulated component into the first composite waveform. A demodulator is coupled to the mixing unit that demodulates the second composite waveform to generate a third composite waveform. A filter network is coupled to the demodulator that is configured to select a desired spectral portion of the third composite waveform.

Abstract: To provide a clock and data recovery circuit which facilitates alteration of the frequency range and adjustment of characteristics.

Abstract: A signal processing device includes a conversion device configured to output a differential current signal at two taps on the basis of an input signal and an oscillator signal. A respective controllable current source is coupled to one of the two taps. An amplification device having a current signal input has a first connection to the first tap and a second connection coupled to the second tap of the conversion device. The amplification device has two output taps; a first charge store is connected to a connection of the amplification device and to the second tap of the amplification device, and a first resistive load is connected in parallel with said first charge store. A second charge store is connected to the second connection of the amplification device and to the first tap of the amplification device, and a second resistive load is connected in parallel with said second charge store.

Abstract: The invention relates to a digital phase locked loop (PLL) 12 for demodulating an intermediate frequency signal. The digital phase locked loop 12 comprises two coordinate rotation digital computers 24 and 30 in its phase detector. The robustness the PLL 12 can be improved by means of a gain control circuit 27, a sign detector 20, a carrier monitoring circuit 28 and an adjustable loop filter 32.

Abstract: A frequency modulation system is disclosed which includes a voltage-controlled oscillator (VCO) 43 and a phase detector 47 configured to receive an output signal from the VCO. The phase detector is arranged to output an error signal representing the phase difference between the signal from the VCO and a reference signal. The system also includes control means 62 arranged to monitor the error signal to derive an indication of the frequency deviation of the VCO, and, in accordance with this derivation, to maintain the frequency deviation of the VCO substantially constant.

Abstract: In embodiment, the present invention is directed to a PLL phase demodulator that utilizes feed-forward error correction. The feed-forward error correction may occur by calibrating an equalizer to possess transfer function that emulates the modulation response curve of the VCO of the PLL phase demodulator. In operation, the equalizer may receive the filtered and integrated version of the error signal produced by the phase detector of the PLL. The equalizer filters the received signal according to the calibrated transfer function. The output of the equalized is provided to a adder to combine the equalized signal with the error signal produced by the phase detector. A similar arrangement including a suitably calibrated equalizer may be utilized to address phase tracking error in a PLL frequency demodulator.

Abstract: A method of receiving a signal and performing a carrier recovery, the method comprising the steps of: (a) receiving a signal Xk. (b) rotating Xk by a previous correction angle &thgr;k−1 to generate a rotated signal Qk, wherein the rotation is based upon a sine and cosine of the previous correction angle. (c) mapping the rotated signal Qk to a valid decision Ak out of a constellation. (d) generating a normalized error signal &Dgr;&thgr;k,k−1 that reflects an angular difference between a correction angle &thgr;k and the previous correction angle &thgr;k−1. (e) calculating and storing a sine and a cosine of the correction angle &thgr;k, wherein the calculation is based upon &Dgr;&thgr;k,k−1, the sine of the previous correction angle &thgr;k−1 and the cosine of the previous correction angle.

Abstract: When a clock reproduction circuit (6) is locked, a phase comparator (9) detects a level difference &Dgr;E between a zero crossing point and a true 0 level. The level difference &Dgr;E represents an offset level and is output as an offset detection signal. After being planarized in the LPF (12), the level difference &Dgr;E is input to adders (14) and (15) so as to cancel a DC offset.

Abstract: A digital FM demodulator employs a baseband phase lock loop (BBPLL), which is particularly effective for long range reception, for combining and demodulating a pair of signals represented by the mathematical expression A(t)ej&thgr;(t) to result in an approximation of d&thgr;/dt. This approximation is then subjected to an inverse of the linear approximation of the frequency response of the BBPLL that produces a very accurate &thgr;. This is conveniently achieved with a IIR filter whose transfer function happens to be the same as the inverse of the linear approximation of the frequency response of the BBPLL. The derivative is then taken of &thgr; to produce a very accurate d&thgr;/dt, the desired result for the output of an FM demodulator. To aid operation of the BBPLL, the incoming digital intermediate frequency is upsampled by a combination of sample and hold and FIR filtering prior to being processed by the BBPLL.

Abstract: A reproduced signal is adaptively equalized in an adaptive equalizer after going through an AD converter. The AD converter, the adaptive equalizer, a phase error detector, a phase shifter, a DA converter, a loop filter, and a variable frequency oscillation circuit, all of which structure a PLL circuit, and a clock signal phase-locked to reproduced data is fed back to the AD converter. The phase shifter slightly shifts, as appropriate, a phase error detected in the phase detector according to the change in a barycenter of tap coefficients detected in a tap barycenter detection circuit. With such structure, signals can be processed in an accurate manner without causing competition in operation between the PLL and adaptive equalization.

Abstract: A bandwidth stabilized PLL in an FPLL has an I channel including an I channel signal, having a pilot, and a Q channel signal. The DC offset, including the pilot, of the I channel signal is determined. The value of the pilot is found by subtracting the determined DC offset from the I channel signal. An error signal is developed from the known value of the transmitted pilot and the determined value of the pilot. The error signal is used to control a gain block for the Q channel for stabilizing the bandwidth of the PLL. Different embodiments are shown for controlling the gain of the PLL from both inside and outside of the PLL.

Abstract: A quadrature demodulator applicable to digital communication and digital broadcast is provided, which simplifies the circuit configuration of a quadrature demodulator section and which reduces the labor or man-hours and the time required for adjusting the demodulation characteristic.