Abstract: The demodulating device for a chrominance signal includes an oscillator with a controlled frequency, and an adjuster for adjusting the oscillator frequency as a function of a charge voltage of a memory capacitor. The adjuster preferably includes a fine adjustment channel to output a first adjustment value that depends on the charge voltage of the memory capacitor, and a coarse adjustment channel to output a second adjustment value. The second adjustment value is modified when the charge voltage of the memory capacitor is not within a given range. The device is used, for example, in integrated SECAM decoders.

Abstract: The present invention concerns a radio circuit including a local oscillator, a first receive frequency converter, a frequency divider and a demodulator. A receive signal and an output of the local oscillator are input to the first receive frequency converter. The receive signal is converted into a first intermediate signal by the first receive frequency converter, and the first intermediate frequency signal is input to the demodulator. The output of the local oscillator is frequency-divided by the frequency divider and also input to the demodulator. The signal converted into the first intermediate frequency is demodulated into a baseband signal by the demodulator.

Abstract: A device for reducing a lock-up time in a digital cordless telephone. The telephone includes a first frequency synthesizer for generating a reference frequency, a receiver having a first mixer for mixing the reference frequency with an input frequency to generate a first intermediate frequency and a second mixer to generate a second intermediate frequency, and a transmitter having a third mixer to generate a transmission frequency. The device includes: a band switching controller for receiving an inverse channel selection signal; and a second frequency synthesizer for generating third and fourth intermediate frequencies to the second and third mixers, respectively, according to a channel selection signal for setting transmission and reception modes.

Abstract: A novel phase detector for use in a timing recovery circuit of pulse amplitude modulation communication system. A filter internal to the phase detector as preliminary stage for operating on a signal stream of pulse-shaped symbols to reduce pattern-dependent jitter of the output of the phase detector. The filter may have plural taps, delays, multipliers, and summers.

Abstract: An optical disc apparatus has a demodulation circuit performing an FSK demodulation by being provided with a binary signal which is obtained by binarizing a signal reproduced from an optical disc on which an FSK modulation signal is previously recorded. An edge interval of the binary signal is measured. An FSK modulation component is obtained from a difference between a measured edge interval value and a previously determined edge interval reference value. A demodulation value is obtained based on a moving average of the FSK modulation component. A moving average of the demodulation value is compared with a reference value so as to obtain a binary FSK demodulation signal. Additionally, the optical disc apparatus includes a decode circuit for decoding binary data from a biphase code signal which is reproduced from an optical disc and to be inverted at an end of each bit.

Abstract: An AFC (Automatic Frequency Control) device and a method of controlling reception frequency in a dual-mode terminal. When a dual-mode terminal uses one or two AFC devices, the time required for acquiring tracking synchronization in a PLL circuit for a first frequency can be reduced using a test augmentation frequency which is an integer multiple of a tracking synchronization acquiring residual frequency of a PLL circuit for a second frequency to which the first frequency transitions for reliable synchronization acquisition. Errors with respect to an output dynamic range caused by use of two AFCs are reduced and thus the demodulation performance of a receiver is ensured by varying quantization bits of an A/D clock based on the dynamic range of residual errors in a frequency area. The demodulation performance can also be ensured by operating an ACPE circuit for an AFC device having many residual frequency errors.

Abstract: A demodulator circuit for demodulating a frequency modulated input, which includes a detector (14) that is operable to produce a demodulated signal from an incoming frequency modulated signal. A tuning circuit (19) is connected to the detector and operable to vary the frequency response characteristics of the detector. An auxiliary detector (25, 26) is connected to receive a reference frequency signal and to provide an auxiliary tuning signal to the detector on the basis of detection of the reference frequency signal.

Abstract: A quadrature demodulator applicable to digital communication and digital broadcast is provided, which simplifies the circuit configuration of a quadrature demodulator section and which reduces the labor or man-hours and the time required for adjusting the demodulation characteristic.

Abstract: A phase detector for controlling a phase locked loop having a voltage controlled oscillator. A counter is clocked by a clock signal produced by the voltage controlled oscillator. A latch coupled to the counter is clocked by a modulated clock signal to latch values output by the counter. The modulated clock signal is produced by a phase modulator which modulates a synchronization clock reference signal. An accumulator coupled to the latch and clocked by the modulated clock signal receives and averages the latch values to produce a phase error signal representative of phase difference between the voltage controlled oscillator clock signal and the synchronization clock reference signal. The phase error signal is coupled to the voltage controlled oscillator to reduce the phase difference. The phase modulator modulates a rising edge of the synchronization clock reference signal with a modulation signal having modulation frequencies outside the loop bandwidth of the phase locked loop.

Abstract: A method of demodulating an FM carrier wave and an FM demodulation circuit are described which use a phase locked loop. The phase locked loop is tuned to a selected carrier wave frequency including the step of selecting a setting of the variable gain circuit in the phase locked loop to select desired loop gain.

Abstract: An extended frequency lock range is achieved in a phase-locked loop (PLL) circuit based on sampled phase detectors by introducing frequency feedback into the PLL circuit. At least one data sampler samples adjacent bits of incoming data, such as data bits D.sub.X and D.sub.Y, and an edge detector samples an edge, E, of the incoming data signal between the two data bits, D.sub.X and D.sub.Y. Sequence values "101" or "010" for the data bits D.sub.X, E and D.sub.Y, are not valid and indicate that the VCO is sampling the incoming data stream too slowly. When sequence values of "101" or "010" are measured by the sampled phase detectors, the frequency of the VCO output, V.sub.O, is known to be too low, and a constant current is preferably injected by the sampled phase detector into the PLL, until the frequency becomes too high, upon which a constant current of opposite polarity is applied.

Abstract: The purpose of the present invention is to provide a frequency synthesizer which does not have spurious components. Automatic reference correcting circuit 4 is provided to frequency synthesizer 1 which changes the frequency division value of the divider and makes the frequency of external output signal (OUT) into a value equal to the frequency of the reference clock signal multiplied by the average frequency division value, charge pump circuit 35 measures the ripple component contained in the output control signal, and ripple correcting circuit 39 forms compensation current, which is superimposed on the control signal in order to minimize the ripple component. If composed for control circuit 55 to obtain the optimum compensation current and output to ripple correcting circuit 39 while negative feedback which minimizes the ripple component is being formed, output signal (OUT) which does not have spurious components can be obtained.

Abstract: An adaptable, variable rate symbol timing recovery system for a digital sal receiver comprises an analog to digital (A-D) signal converter having analog signal input and digital data signal output terminals. A source of selectable, substantially fixed rate, data sampling clock signals is coupled to the A-D signal converter for sampling a signal received at the input at a predetermined, substantially fixed clock rate, depending on data rate and modulation of the received signal. A digital signal processing loop is coupled to the digital data signal output terminal for adjustably producing interdependent signals in synchronism with the data signals at the output terminal which are asynchronous with respect to the fixed rate clock signals. A Controller is provided for selectively configuring the data sampling clock signal source and the digital signal processing loop according to the data rate and modulation characteristics of the received signal.

Abstract: An FM demodulator circuit includes a filter (10) and a detector (14) for receiving a frequency modulated input signal and for providing a demodulated output signal. A tuning circuit (19) is provided for tuning the frequency characteristics of the filter and of the detector. A DC offset estimator (18) is connected to the output of the detector to produce an offset signal representing the estimated DC offset of the demodulated output signal, and to provide the offset signal to the tuning circuit. The tuning circuit is operable to tune the frequency characteristics of the filter and detector in dependence upon the offset signal.

Abstract: A frequency stabilizer circuit in the form of a charge-pump phase-lock loop utilizing a MEMS capacitance device, preferably a tunable MEMS capacitor or a MEMS capacitor bank, which more rapid and with a greater precision determine the phase and frequency of a carrier signal so that it can be extracted, providing an information signal of interest. Such MEMS devices have the added advantage of providing linear capacitance, low insertion losses, higher isolation and high reliability, they run on low power and permit the entire circuit to be fabricated on a common substrate. The use of the MEMS capacitance device reduces unwanted harmonics generated by the circuit's charge pump allowing the filtering requirements to be relaxed or perhaps eliminated.

Abstract: Circuit and method for generating a signal for use in locking a second signal on a first signal. The first and second signals have an associated frequency. A first beat note signal and a second beat note signal are generated from the first and second signals, respectively, when the frequencies of the first and second signals are not equal. The circuit includes a first and second flip-flop and detector circuitry. The first flip-flop is configured to receive the first and second beat note signals for generating a first state signal. The first flip-flop generates the first state signal by sampling the second beat note signal at a first periodic interval of the first beat note signal. The second flip-flop is configured to receive the first and second beat note signals for generating a second state signal. The second flip-flop generates the second state signal by sampling the second beat note signal at a second periodic interval of the first beat note signal.

Abstract: A Steered Frequency Phase Lock Loop (SFPLL) comprises a phase loop that functions like a normal phase locked loop (PLL) and locks to the input signal, and a frequency loop that uses a reference frequency to influence the phase loop and effectively confines the output frequency of the phase loop and the SFPLL to be in a range of frequencies close to the reference frequency. The reference frequency is chosen to be very close to the input signal frequency that it is desired the SFPLL lock to. The SFPLL comprises a phase detector (10), a frequency detector (22), first and second gain components (12, 24), first, second and third filter components (14, 18, 26), a summer (16) and a voltage controlled oscillator (VCP)(20). By a judicious choice of the gains in the phase and frequency loops the SFPLL can be designed so that the range of frequencies to which the SFPLL will lock can be confined to an arbitrarily small region around the reference frequency (.omega.'.sub.r).

Abstract: For a possible simple structure, dispensing with ceramic filters, an FM demodulator for demodulating sound-FM signals comprises a controllable amplifier (1) which receives the sound signals converted to intermediate frequencies, said amplifier having a gain which is adjusted by means of an amplitude control circuit (4) and whose output signal is applied to the amplitude control circuit and to the phase-locked loop which supplies a demodulated sound signal in the locked-in state from its output, said phase-locked loop including a loop filter (7) which comprises a filter (8, 9, 10) of at least the second order with a pole at the frequency f=0, and a limit-detection circuit (13) which feeds back the operating frequency of the phase-locked loop to a predetermined frequency range when said phase-locked loop leaves this frequency range around a predeterminable nominal demodulation frequency, the amplitude control circuit (4) controlling the controllable amplifier (1) in dependence upon its output signal and a signa

Abstract: Receiver having an RF input for applying an RF input carrier-modulated modulation signal thereto, which receiver is coupled to a multiplier circuit and to a phase-locked loop (PLL) with a signal path incorporating a phase detector, a loop filter, a first dc decoupling circuit and a controlled oscillator having an in-phase and a quadrature output via which local in-phase and quadrature carriers are applied to the multiplier circuit and the phase detector, respectively, and a signal generator for generating a local auxiliary pilot and a pilot detector for detecting the local auxiliary pilot, an output of which is coupled to the controlled oscillator via a low-pass filter.

Abstract: A demodulator (200) including a phase detector (201) receiving a modulated signal and outputting a demodulated signal. The phase detector (201) also receives a reference signal. A programmable voltage circuit (203, 204) outputs an analog voltage. A reference signal generator (208) that is responsive to the programmable voltage circuit (204) and the demodulated signal has an output coupled to provide the reference signal to the phase detector (201). A window detect circuit (206) with an input coupled to the demodulated signal generates an inhibit signal when the demodulated signal is within preselected limits. The inhibit signal is coupled to latch the programmable voltage circuit (203, 204). Preferably, the programmable voltage circuit is implemented as a digital-to-analog converter (204) driven by a counter (203) or by a processor circuit (302).

Abstract: An apparatus is disclosed for processing an input signal. The apparatus includes two feedback loops for generating output signal components from the input signal. Each loop contains an oscillator, which has a frequency or phase which is variable in response to a control signal, and a comparator for generating the control signal. The oscillator generates a loop output signal which forms one of the components of the output signal. The apparatus also includes a combiner for combining the loop output signals to produce the output signal. For each loop, the apparatus also produces a feedback loop operating signal, these signals being dependent on the output signal and in phase quadrature with one another. One input of the comparator in each loop receives the feedback loop operating signal, and the other input of the comparator receives a component of the input signal.

Abstract: Digital information including a sync data field and a user data field subsequent thereto is read from a storage media as a digital information signal in an analog signal format. The obtained signal is sampled according to a clock signal and is thereby transformed into a digital information signal in a digital format. In the sync data field, the clock signal is synchronized with the digital information signal by an analog PLL circuit. Thereafter, in the user data field, the clock signal is synchronized with the digital information signal by a digital PLL circuit.

Abstract: A high-performance voltage controlled oscillator without use of variable capacitance (varicap) diodes which is easy in fabrication in an semiconductor IC form. The voltage controlled oscillator includes:a differential amplifier having a differential pair of transistors (Q.sub.1, Q.sub.2); an LC resonance circuit having a coil (L.sub.0) and a capacitor (C.sub.0); a phase shift circuit for receiving a differential output of the differential amplifier via a buffer of transistors (Q.sub.3, Q.sub.4) and for providing its output for the differential amplifier in a positive feedback mode; and a current control circuit for variably controlling an operating current (Ie) of the phase shift circuit according to a controlled voltage applied from a circuit other than those in the voltage controlled oscillator.

Abstract: The present invention concerns apparatus and method for setting up the tuning frequency of a PLL, demodulator that includes a VCO. Frequency synthesizing circuitry controls the VCO via a first switched control path. Comparison circuitry provides a first signal that corresponds to the difference between the output frequency of the VCO and a reference frequency. Control circuitry is provided that is responsive to a plurality of signals including the first signal for operatively controlling the apparatus. The apparatus further includes: a ceramic resonator oscillator for providing the reference frequency; a non-volatile memory for storing the value of the first signal; and comparison circuitry for comparing a stored value of the first signal with a current value of the first signal so as to produce a second signal for adjusting the tuning frequency of the frequency synthesizing circuitry in response to the second signal.

Abstract: A frequency synthesizer (100) is utilized for producing an output signal (124) which is phase locked to a reference signal (110) operating at a reference frequency. The frequency synthesizer (100) comprises a main phase lock loop (PLL) (102), and a tracker PLL (128). The main PLL (102) includes a phase detector (112), two frequency dividers (108, 126), a loop filter (116), a notch filter (118), and a controlled oscillator (122). The tracker PLL (128) phase locks to the reference signal (110), and biases the notch filter (118) in order to maintain an accurate lock on the notch frequency which is proportional to the reference frequency. All circuits are integrated in the same monolithic device in order to track parametric tolerances such as transconductances of the operational transconductance devices included in the tracker PLL (128) and the notch filter (118).

Abstract: Device of the phase-locked loop type for demodulating a frequency-modulated signal. Device for frequency demodulation, using a phase-locked loop. According to the invention, for linearizing the variation of the frequency of a local oscillator (11) as a function of its control signal (Vb), a variable capacitance (Cv) is formed by an electronic module (20) which supplies the equivalent of a capacitance whose variation as a function of the control voltage (Vb) has a linearity deviation which is established for compensating the linearity deviation of the frequency of the oscillator as a function of the value of the capacitance (Cv).

Abstract: A biphase stable FPLL includes a lock switch, operated in response to a frequency lock condition, that forces a predetermined voltage on the input of the third multiplier to guarantee that the loop locks up in a phase that produces a desired polarity of demodulated signal. A frequency lock indicator operates the lock switch to force the predetermined voltage on the third multiplier irrespective of the actual lock up phase of the loop. If the lock up phase is wrong, the voltage reversal causes the VCO to slip 180.degree. in phase and the loop locks up in its other bistable state.

Abstract: A highly efficient linear amplifier and/or modulator and demodulator comprising first and second feedback loops is provided. Each loop processes a component of the input signal and the component signals are recombined at, for example, a summing junction 18. The feedback signals for each loop are dependent upon the output signal and are in phase quadrature. The input signal is separated into I and Q signals, which are also in phase quadrature, by a component separator 10.

Abstract: A combination of two phase-lock loops, and a cancellation circuit are used to remove a dominant FM signal from within a signal environment. The two phase-lock loops together produce a replica of the highest power (i.e. dominant) FM signal. The cancellation circuit uses this replica in a demodulation, notch-filtering, and remodulation process to excise the dominant FM signal, leaving the other signal(s) undisturbed. Potential applications include co-channel FM signal/interference cancellation and optimizing utilization of RF spectrum.

Abstract: A FM (Frequency Modulated) DCFB (Deviation Compression Feedback) signal demodulator can be achieved by utilizing FM deviation compression feedback techniques. An FM signal is coupled to a mixer (10) wherein a signal from a local oscillator is mixed with the input signal. The output of the mixer is then coupled to a variable selective IF amplifier. The IF amplifier couples the signal to a limiter amplifier, the output of the limiter amplifier is FM demodulated and fed to an output. The output signal is simultaneously fed back through a variable Frequency Compensation Network (FCN) (Loop Filter). The output signal of the FCN is then fed back to a local oscillator (17). The output of the local oscillator (17) is in turn fed back into the original mixer (10). The improved demodulated signal is sampled at an output (26).

Abstract: An FM demodulator formed on a semiconductor chip generates a demodulated audio-frequency signal from an audio intermediate frequency signal through a phase locked loop constituted by a multiplier, a low-pass filter and a voltage-controlled oscillator. A variation of amplitude of the demodulated audio-frequency signal due to a temperature variation is compensated by a temperature compensating amplifier and a de-emphasis filter through first and second reference currents flowing out therefrom through an internal resistor fabricated on the same semiconductor chip and an external resistor.

Abstract: A biphase stable FPLL includes a polarity determination circuit that ascertains the lockup phase of the FPLL based upon the polarity of the pilot in the digital signal. A frequency lock circuit also determines from the recovered pilot when frequency lock has occurred and the polarity determination circuit is responsive thereto for inverting the phase of the incoming, or alternatively, of the outgoing signal, as determined in order to supply an output signal of predetermined polarity.

Abstract: A multi-level demodulator has a VCO (32) and two reference frequency sources (50, 41). A relatively long time-constant loop (45, 47) has an input coupled to the VCO, an input coupled to one of the reference frequency sources (41) and an output coupled to the VCO. A relatively short time-constant loop (51, 30) has an input coupled to the VCO, an input coupled to the other reference frequency source (50) and an output coupled to the VCO.

Abstract: A receiver comprises a demodulator for demodulating a received signal, a clock recovery circuit for regenerating a clock phase-synchronized with a symbol clock component included in the received signal and a frequency offset compensating unit for controlling a variable division ratio of a variable divider constituting a phase-controlled loop of the clock recovery circuit so as to compensate for a frequency offset corresponding to a difference between a frequency of the symbol clock component included in the received signal and a free-running frequency of the clock recovery circuit. The receiver is constructed such that the compensation for the frequency offset is performed with operation timing different from that of the clock recovery circuit.

Abstract: The invention provides a demodulation PLL wherein: the first position of a switch, which is controlled by a control circuit, respectively connects the outputs of a mixer and a LP filter to high gain and low gain inputs of an oscillator when frequency signals at the inputs of the mixer have not converged sufficiently, i.e. during the PLLs tuning mode; the second position of the switch respectively connects the outputs of the mixer and the LP filter to the low gain and high gain inputs of the oscillator when the frequency signals at the inputs of the mixer and the signal levels on the input and output of the filter have converged sufficiently, i.e. during the PLLs demodulation mode.

Abstract: A method of demodulating an FM carrier wave and an FM demodulation circuit are described which use a phase locked loop. An FM input signal including the carrier wave is supplied to a phase detector in the phase locked loop. The output of the phase detector is filtered and used to generate a signal for use in controlling a voltage controlled oscillator having an output also connected to the phase detector. The phase locked loop is tuned to a selected carrier wave frequency and a variable gain setting of a variable gain circuit in the phase locked loop is selected to select a desired loop gain. The signal for use in controlling the voltage controlled oscillator is varied by the variable gain circuit to alter the amount by which the frequency of the output of the voltage controlled oscillator changes in relation to a given output of the phase detector. The variable gain setting is selected to select a required bandwidth for demodulation.

Abstract: An FM demodulator demodulating an FM modulated input signal through a PLL circuit, which includes a phase comparator a loop filter, a DC amplifier, a BB amplifier, and a VCO, and outputting the demodulated signal further includes a feedback circuit connected in parallel to DC amplifier and having a resistance which is a function of an external control voltage. The feedback circuit may be connected in parallel to both DC amplifier and BB amplifier. A PIN diode is typically used as a resistance variable element in the feedback circuit.

Abstract: An FM detecting circuit using phase locked loop (PLL) is disclosed. A reference voltage unit generates a reference voltage. A phase detector detects a phase difference between an FM signal and another frequency signal. A low-pass filter receives the output signal from the phase detector, and outputs a detected signal by passing only low frequency signals. A DC component detector receives the output signal from the low-pass filter, and detects a DC component. A voltage controlled amplifier receives the reference voltage and the voltage output from the DC component detector, and outputs a constant level voltage by controlling a gain based upon the difference between the two received voltages.

Abstract: A zero-intermediate frequency receiver circuit (11) for receiving a radio frequency signal detected by an antenna (14). The receiver circuit (10) comprises a second local oscillator circuit (25) and an oscillator circuit (60) of a phase locked loop demodulator (36) which are identical and track each other so as to provide a more accurate reference for processing a demodulated signal. A current reference (39) providing a current reference signal utilized by the second local oscillator circuit (25) and the oscillator circuit (60) of the phase locked loop demodulator (36).

Abstract: The output frequency of a PLL frequency synthesizer and the output frequency of a fixed oscillator are mixed together in a mixer to produce sum and difference frequencies. The sum frequency is used as a local frequency, and the difference frequency is fed back to the PLL frequency synthesizer. In addition, the output frequency of the fixed oscillator is divided in a predetermined ratio to use it as a local frequency for the second or other subsequent frequency converting stage on the receiver or transmitter side.

Abstract: A high frequency television signal receiving apparatus providing excellent linear detection of output characteristics by improving the phase characteristic of the picture synchronous detector. A variable capacitive element is equivalently connected in parallel to a reference solid-state oscillation element. The reference solid-state oscillation element controls the frequency of a local oscillation device including a PLL circuit for feeding a local oscillation signal to a mixer for converting a high frequency signal into an intermediate frequency signal. A first low pass filter is connected between a phase comparator for detecting a phase difference of the intermediate frequency signal and the output of a detection oscillator for generating a detection oscillation signal with a specific phase difference. A second low pass filter having a larger time constant than the first low pass filter is connected to the variable capacitive element.

Abstract: Data terminal comprising a demodulator for a FSK phase-coherent modulated signal having at least two frequencies, comprising a PLL circuit (10) in which a phase detector is combined with a real-time integrator (15) and in which a sequencer (5) is included, so that the modulated signal is integrated around the zero crossings before a clock signal and digital data are extracted from this signal after a phase lock. As long as the PLL circuit (10) is in the unlocked state, the frequency with which the integrator (15) is driven by the sequencer (5) is equal to half the bit rate of the modulated signal while, for that matter, this frequency is equal to the bit rate.

Abstract: Receiver section (200) includes a compensation network (202) which compensates for undesired effects caused by synthesized LO (204). Compensation network (202) substantially duplicates the amplitude and phase delay of synthesized LO (204) allowing for a substantially flat demodulated frequency response to be achieved at output (122) which is independent of the bandwidth of synthesized LO (204).

Abstract: A heterodyne receiver including a frequency discriminator adapted such that a signal to be subjected to frequency discrimination is divided into two signals and mixed together after one of the divided signals has been given a delay time, and additionally provided with a filter, of which a cutoff frequency is determined according to the delay time, disposed in the front stage. This results in both improvement of accuracy in frequency identification and expansion of the capture range.

Abstract: A transceiver (10) includes a dual port phase and magnitude balanced synthesizer modulator (60). The modulator (60) couples a modulation input to a voltage controlled oscillator (40) and to a reference oscillator (42) that are coupled together in a phase locked loop (44). The modulator 60 includes a magnitude balancing circuit (64) that divides a modulation input representing data or the like into a first modulation input signal applied to the reference oscillator (42) and a second modulation input signal for the voltage controlled oscillator (40). A phase balancing circuit (68) induces a negative phase shift in the second modulation input signal that is coupled to the voltage controlled oscillator (40) in order to compensate for the phase lag of the reference oscillator loop (44).

Abstract: A demodulator receives a radio signal and causes a carrier signal reproducing circuit to reproduce the carrier signal of the received signal. One amplifier amplifies the amplitude of the reproduced carrier signal by K, and another amplifies the amplitude of the reproduced carrier signal by (K+2). An adder adds the reproduced carrier signal, amplified by K, and the received signal. A subtracter subtracts the received signal from the reproduced carrier signal amplified by (K+2). The output signal of the adder is demodulated by a first FM demodulator and the output signal of the subtracter is demodulated by a second FM demodulator. Another subtracter outputs the difference between the demodulated signals from the first and second FM demodulators as a demodulated signal of the received signal.

Abstract: A frequency modulation signal demodulator receives an intermediate frequency signal to demodulate a FM signal. The frequency modulation signal demodulator includes a voltage-controlled oscillator having variable capacitance diodes. The voltage-controlled oscillator varies the oscillating frequency of a signal by controlling a voltage across the variable capacitance diodes using a DC voltage. Also included is a phase comparator which produces a phase difference by comparing the phase of the intermediate frequency signal to the phase of the signal from the voltage-controlled oscillator and provides a direct current voltage signal corresponding to the phase difference. Also included is a differential amplifier which has an adjustable reference voltage source. The differential amplifier amplifies the direct current voltage signal to produce a demodulated signal. The demodulated signal is negatively fed back to the voltage-controlled oscillator as the direct current signal.

Abstract: A radio frequency (RF) transceiver for modulating and demodulating RF signals with a direct modulation transmitter and a dual intermediate frequency (IF) receiver, respectively, includes a local oscillator, three frequency converters, a demodulator, a carrier generator, a modulator, a controller and two signal switches. The local oscillator (e.g. phase lock loop PLL!) provides a first local oscillator (LO) signal. One frequency converter (e.g. mixer) frequency converts an incoming modulated RF signal with the first LO signal to provide a first modulated IF signal. A second frequency converter frequency converts the first modulated IF signal with a second LO signal to provide a second modulated IF signal. The demodulator also receives the second LO signal and demodulates therewith the second modulated IF signal. The carrier generator (e.g. voltage-controlled oscillator VCO!) receives a transmitter control signal and in accordance therewith generates a transmitter carrier signal.

Abstract: A method of demodulating an FM carrier wave and a demodulating circuit are described which utilize a gain control circuit. An output is supplied from the gain control circuit to a phase locked loop circuit tuned to a selected carrier wave frequency. A first output of the phase locked loop circuit is used to generate a tuned gain control signal dependent on the amplitude of the input FM carrier wave to which the phase locked loop is tuned and the tuned gain control signal is used to control the gain of the gain control circuit.

Abstract: An oscillator capable of setting a desired frequency by using only two resonators without setting up any additional adjustment processes, and a synthesizer tuner circuit with an AM synchronous detect circuit.