Abstract: To demodulate an analog signal having information modulated by a carrier, the analog signal is chopped by a chopper, the chopped signal is digitized by a sigma-delta analog-to-digital converter to produce a series of digital samples at a sampling frequency, the digital samples are filtered in a digital decimating filter to produce data words, and the data words are modulated by an intermediate frequency signal to produce a detected information signal. The various frequency signals are generated by a phase-lock loop so that the intermediate frequency is the difference between the carrier frequency and the chopping frequency, and both the chopping frequency and the intermediate frequency are sub-multiples of the sampling frequency.

Abstract: A demodulator circuit and a demodulating method are disclosed. A demodulator including a phase-locked loop for a receive carrier recovery or a phase lock recovery demodulates an input received signal and a band of a loop filter of the phase-locked loop is controlled by a control signal. A bit error rate monitor detects a bit error rate of a demodulated outputs the control signal on the basis of the bit error rate result of the demodulator, and a loop filter band controller output from the bit error rate monitor. Hence, the bit error rate of the demodulated signal is detected and the loop filter band of the phase-locked loop of the demodulator is controlled based on the detected bit error rate. As a result, an exact control of the loop filter band of the demodulator can be performed on the basis of the received signal state without using any received signal power detector, any C/N detector or the like.

Abstract: A data transmission system includes a source of a data signal and a modulator, responsive to the data signal, producing a first modulated signal representing the data signal and a second modulated signal representing a signal 180 out-of-phase with the data signal. The first and second modulated signals are transported via a transmission channel. A first demodulator demodulates the transported first modulated signal and a second demodulator demodulates the transported second modulated signal. A subtractor, responsive to the first and second demodulators, produces a signal representative of the data signal.

Abstract: Apparatus for setting up the tuning frequency of a phase locked loop is provided which utilises the voltage controlled oscillator of the phase locked loop itself. The apparatus includes signal translation circuitry which can provide a control voltage to the VCO of the phase locked loop dependent on a tuning voltage which is alterable in response to the frequency of the signal output by the VCO.

Abstract: The transmitter uses a synthesized oscillator (1A) whose reference (24) is provided by the clock (H) of the data (P, Q). The demodulation oscillator (13A) of the receiver is a synthesizer which is functionally identical to that (1A) of the transmitter, and its reference (23) is provided by the clock (H, 36) recovered from the received data.

Abstract: An FM demodulation circuit comprises, an oscillation circuit (3) whose oscillation frequency is varied by a control signal, a phase comparator means (2) for comparing phases of signals between an FM signal to be demodulated and the output signal of the oscillation circuit (3) and generating a comparison signal corresponding to the phase difference, an additional voltage determining circuit (7) for determining an additional voltage based upon the comparison signal, and an adder (5) for adding the comparison signal and the additional voltage, and supplying the added result as the control voltage. The additional voltage may be a value which makes the comparison signal level at a center level of the operable range of the phase comparator (2).

Abstract: A signal receiving device is kept tuned by a tuning signal, which supplied to a tuning input of a tunable circuit in the signal receiving device. The tuning signal is supplied from a memory. The signal receiving device has an operating state and a calibrating state. The calibrating state serves to determine the tuning signal and to store it in the memory. In the calibrating state, a broadband signal source supplies a broadband signal to a band-pass filter. The band-pass filter is tuned to and passes a reference signal to the tunable circuit which provides the signal receiving device with selectivity in the operating state. The response of the tunable circuit to the reference signal is monitored and a tuning signal is selected for which it is measured that the tunable circuit is tuned to the reference signal which is passed by the band-pass filter.

Abstract: A method and apparatus for digitally demodulating a phase or frequency modulated signal using a quadrature mixing circuit to mix the phase or frequency modulated signal with a frequency equal to the carrier frequency of the received modulated signal to produce in-phase component signal (I) and a quadrature component signal (Q) of the received phase or frequency modulated signal which differ in phase by 90 degrees. The I and Q signals are provided via respective low pass filters to a phase to digital converter for generating a digital output signal. The digital output signal is provided to an interface circuit which generates a plurality of phase-change information signals which are provided to a signal processing circuit. The signal processing circuit uses interpolation circuitry to produce a demodulated signal. A further output of the signal processing circuit, i.e. a D.C. signal, is fed back to provide automatic frequency control to an oscillator in the quadrature mixing circuit.

Abstract: An inertial measurement and navigation system using a multisensor which provides analog acceleration and rate information to an analog to digital converter whose digital output is processed by a digital demodulator and fed to an AHRS systems processor whose output is fed to a digital to analog converter. Output information from the digital to analog converter can be stored or used to provide information to the pilot oil cockpit displays. The digital demodulator includes a phase locked loop comprising a Hilbert transform phase detector, a first order IIR loop filter and a digital controlled oscillator which provides in-phase and quadrature reference signals used in demodulation.

Abstract: A timing circuit having an analog to digital converter to sample an analog signal, a controlled oscillator for controlling sample times of the analog to digital converter, a circuit to detect pulses in the analog signal, a phase error circuit to subtract one of two samples from the other to create a phase error measurement and a frequency error circuit to add two samples together to create a frequency error measurement. The two samples are taken from either side of a pulse. The phase error measurement is used by the controlled oscillator to adjust the sample timing to take samples at desired locations on the pulse. The circuit also contains constant values used to compensate for the pulse being asymmetrical and to compensate for other pulses that occur close to the detected pulse. The circuit also inserts a known frequency in place of the analog signal to establish a frequency of the controlled oscillator.

Abstract: There is described an electronic circuit which operates an Amplitude Locked Loop. The circuit comprises a voltage controlled amplifier, a modulus detector and an integrator combined in a feedback loop. An FM signal decoder is also described as are a number of applications of Amplitude Locked Loop.

Abstract: A non-coherent demodulator 1 multiplies a modulated intermediate frequency (IF) signal with a signal from a local oscillator 2 to produce a first pseudo baseband signal having frequency error. The first pseudo baseband signal is supplied to a wide band PLL type demodulator 15. A low-pass filter 26 removes noise component from a first control signal from a loop filter 19 in the wide band PLL type demodulator 15 to produce a second control signal. Multipliers 24 and 25 multiply the first pseudo baseband signal with an output of a voltage-controlled oscillator 27 controlled by the second control signal to produce a second pseudo baseband signal having smaller frequency error. The second pseudo baseband signal is supplied to a narrow band demodulator 14 and converted into a baseband signal.

Abstract: A phase-locked loop circuit and method for producing an output signal which is phase locked with respect to an input signal are disclosed. The circuit includes a phase detector responsive to the phase relationship between the input signal and the output signal. A controlled signal generator, which includes a voltage controlled oscillator, generates the output signal and includes coarse adjust circuitry and fine adjust circuitry. The coarse adjust circuitry causes the frequency of the output signal to fall within one of a selected group of frequency bands in response to the frequency of the input signal. Once the coarse adjustment is made, the fine adjust circuitry continuously changes the frequency and phase of the output signal in response to the phase detector so that the output signal will be phase locked to the input signal.

Abstract: Apparatus for demodulating information signals frequency-modulated on an RF carrier signal carrying spectral components within the audio frequency range, a pilot carrier signal having an imparted phase shift from the phase of the transmitted pilot carrier signal, and amplitude-modulated spectral components having another imparted phase shift in a subcarrier channel frequency range above the audio frequency range. The apparatus includes a demodulator for demodulating the frequency-modulated information signals to provide a detected composite signal which includes a detected pilot carrier characterized by an imparted phase shift due to the effects of multipath reception, and detected amplitude modulated spectral components exhibiting another multipath induced phase shift.

Abstract: A phase error processor interfaces a proportionate phase detector to a digital loop filter in a high frequency phase-locked loop (PLL). The PLL receives a high frequency stream of NRZI encoded data, which contains a variable density of data signal transitions. A phase detector in the PLL generates proportionate phase error information in the form of a phase error pulse signal PD1 and a reference pulse signal PD2 for each data transition in the incoming data s The phase error processor, using a "decimation" technique, integrates the proportionate phase error information from just one pair of adjacent positive and negative data transitions during each period of N clock cycles if the number of input data transitions which occur during that time period exceeds the expected minimum, otherwise the phase error processor passes no phase error information. The selection of window width is based on the coding scheme of the incoming data stream.

Abstract: An improved synthetic heterodyne demodulator circuit. The circuit is arranged to accept the output signal s(t) from an interferometric sensor with large amplitude sinusoidal phase modulation (phase-generated carrier). The phase modulation amplitude is adjusted such that a selected pair of odd and even carrier harmonics are equal. The quadrature signal components are first extracted from the phase-generated carrier using standard homodyne techniques. The quadrature signal components are then used to AM-modulate a pair of equal-amplitude quadrature carrier components at an arbitrary frequency .omega..sub.c, and summed. The result is a conventional PM modulated carrier which can be demodulated using standard FM techniques, followed by integration, to recover with high fidelity the sensed information.

Abstract: The order statistic signal processor obtains continuing estimates of amplitude, phase, or frequency of an input signal based on order statistics. By way of definition, the P'th order statistic for a set of samples from a continuously distributed process is the P'th largest of the samples. Where a signal parameter fluctuates with time as a result of contamination by noise and interference and where the noise fluctuation rate is much greater than the rate at which changes in a signal parameter occur, an order statistic associated with a set of signal parameter samples can serve as an estimate of the signal parameter. The order statistic signal processor is based on an iterative process whereby the prior estimate of a signal parameter, i.e. amplitude or phase, is subtracted from each of a plurality of signal parameter samples obtained over a period of time. The differences are converted to quantities of fixed magnitude with signs corresponding to the differences.

Abstract: A phase-locked loop demodulator comprises a mixer and a loop filter between an input and an output. A voltage-controlled oscillator is connected between its output and an input of the mixer. The demodulator further comprises a lock-on detector circuit whose output signal is adapted to increase the static loop gain after lock-on by modifying the characteristics of the filter.

Abstract: A frequency detection system is based on a digital phase locked loop, the detection system being especially suitable for use in noisy environments like supervisory audio tone (SAT) detection in AMPS and TACS mobile telephone systems. In addition to the digital phase locked loop (4), the frequency detection system according to the invention incorporates a detector circuit (5), which comprises a detection timer (6) and two phase detectors VI1 (7) and VI2 (8). The timer (6) forms a detection sequence of desired length, at the end of which the output signal (SATVAL) of the detector circuit is updated. The first phase detector VII (7) has a phase window in which it counts those falling edges of the synchronized input signal (SSAT) that coincide with the window. The second phase detector VI2 (8) also has a phase window of its own in which it counts those falling edges of the synchronized input signal (SSAT) that coincide with its window.

Abstract: A signal modulated by original data is received and demodulated to output demodulated data. A number representing the correspondence of the original data with the outputted demodulated data or the lack of correspondence of the original data with the outputted demodulated data is counted. The count result representative of the suitability of the reception state of the receiver is outputted to a data processing circuit.

Abstract: A conventional phase-locked loop is improved by replacing its phase detector with one comprising a linear ramp generator and a sample-and-hold circuit, thus eliminating the need for a lowpass loop filter, although the output of the sample-and-hold circuit may be filtered in the case of a very low level modulating signal on the incoming FM signal, but then filtering is not a difficult problem as in a conventional phase-locked loop. The result is FM demodulation by zero-order estimation. For FM demodulation by first-order estimation, the arithmetic difference between adjacent samples is formed, and using a second sample-and-hold circuit an arithmetic difference signal is produced as an input to a second ramp generator that is reset after each sampling cycle to generate a ramp the slope of which is a function of the arithmetic difference signal stored in the second sample-and-hold circuit.

Abstract: The invention provides a digital radio link receiving device consisting of a microwave frequency part with a device for signal downconversion to an intermediate frequency, an intermediate frequency part limited to direct demodulation of the signal at intermediate frequency, and a baseband part responsible for processing the signal.

Abstract: An arrangement for coherently demodulating PSK (phase-shift keying) signals, includes a quasi-coherent demodulator which implements coarse coherent demodulation on an incoming PSK-modulated IF signal using a variable frequency which is applied from a controllable local oscillator. The output of the quasi-coherent demodulator is applied to a coherent demodulator which also receives the output of a VCO (Voltage Controlled Oscillator). A phase detector receives the output of the coherent demodulator and applies the output thereof to the VCO via a loop filter. The output of the loop filter is applied to a local oscillator controller having an output which is used to control the controllable local oscillator.

Abstract: An improved frequency synthesizer 100 capable of producing true DC frequency modulation without the need to DC frequency modulate the reference oscillator. The synthesizer 100 includes a phase comparator 104 compares the reference signal 102 and the feedback signal 112. The output of said phase comparator 104 filtered and coupled to the main VCO 108. A balanced image mixer 200 mixes the two signals from the main VCO 108 and an offset VCO 300. The offset VCO 300 is a low frequency (e.g. 100 to 300 KHz) integrated offset VCO 308 whose center frequency is controlled accurately, by means of matching to a VCO 306 which is controlled by a feedback loop, and by using an image balanced mixer 200 to reduce the image response to substantially reduce or eliminate the filtering required at the mixer output. The configuration of the offset mixer within the synthesizer loop, any residual spurious content due to imperfect image balance or carrier feedthrough of the mixer is attenuated by the loop response.

Abstract: A phase loop demodulator, in particular for space telecommunications, comprises a primary phase loop, a locking detector circuit responsive to acquisition by the primary loop, and a secondary phase loop controlled by said detector circuit.

Abstract: A voltage-controlled delay is connected in series with a phase-locked loop. The voltage-controlled delay is controlled by the control voltage developed by the phase-locked loop amplifier and filter. With this arrangement, the amplifier and filter can be designed to have a transfer function that does not include an explicit zero. Consequently, the jitter transfer function of the overall structure can be designed to remain equal to or less than unity over all frequencies and jitter peaking is eliminated.

Abstract: An on channel frequency agile PLL demodulator is provided using a precise and stable oscillator, such as a VCXO having its output frequency variable over a limited range. The output of the oscillator is multiplied by a multiplication factor to produce a mixing frequency. The multiplication factor scales the limited range of the oscillator to produce a proportionate mixing frequency deviation. A frequency synthesizer is used to enable the demodulator to detect signals on different channels. In one embodiment, the output of the frequency synthesizer is mixed with the scaled oscillator output to provide a mixing frequency having a fixed deviation for all channels.

Abstract: A full threshold FM (Frequency Modulated) signal demodulator can be achieved by utilizing FM deviation compression feedback technics. An FM signal is coupled to a mixer (10) wherein a signal from a local oscillator is mixed. The output of the mixer is coupled to a selective IF amplifier. The IF amplifier couples the signal to a limiter amplifier, the output of the limiter is coupled to a parallel BPF and AM demodulator system. The output signal of the AM demodulators are summed by a summing amplifier. The output signal is simultaneously feed back through at least two frequency compensation networks. The output signal of the FCN is feedback to two BPFs (13 and 13'). Further, the output signal of the FCN is feedback to a local oscillator (17). The output of the local oscillator (17) is feedback into the mixer (10). The improved demodulated signal is sampled at an output (26).

Abstract: A FM signal is applied to a variable gain amplifier (5) of an FM demodulator. The gain of variable gain amplifier (5) is varied in response to a gain control signal. The output signal of variable gain amplifier (5) is applied to an FM demodulating circuit (7) constituting a PLL circuit via a BPF (6). The output signal of BPF (6) is also applied to a synchronous detector (12) via a 90.degree. fixed phase shifter (11). The output signal of a VCO (10) included in the PLL circuit is applied to synchronous detector (12) as the reference signal. The synchronous detector (12) is responsive to the reference signal for synchronous detecting the output signal of 90.degree. fixed phase shifter (11). The output signal of synchronous detector (12) is applied to variable gain amplifier (5) via a LPF (13) as the gain control signal. Thus, variable gain amplifier (5) is responsive to the output signal of synchronous detector (12) for making the amplitude of the FM audio signal included in the FM signal constant.

Abstract: A signal receiving system for receiving messages from each of several unequal amplitude FM carriers occupying the same portion of the frequency band. The signal receiving system receives power division multiplexed signals, each of which being allocated a portion of the total average power of an assigned FM band.

Abstract: A signal delay device comprises a CMOS gate circuit having an input terminal to which a binary input signal to be delayed is applied, an output terminal from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to various circuits including a FM modulator or FM demodulator. The signal delay device will assure undistorted signals.

Abstract: Phase detector having a first input for an angle-modulated input carrier to be detected, and a second input for a reference carrier having a phase shift which is dependent on the angle modulation with respect to the input carrier, the input and reference carriers being at least multiplied in the phase detector, and a frequency demodulator including such a phase detector. In order to inhibit signal distortion and notably second-order interference products in the demodulation of an angle-modulated input carrier, the phase detector according to the invention is adapted to derive an in-phase carrier A and a phase quadrature carrier B from the input carrier and to derive an in-phase carrier C and a phase quadrature carrier D from the reference carrier which has a phase which, at an average, is equal or opposite to that of the input carrier, while the phase detector is further adapted to supply from its output a signal which substantially corresponds to AC-BD.

Abstract: Self-adjusting frequency demodulation circuit comprising a frequency demodulator (13) which is designed as an integrated circuit, the adjustment being effected with the aid of a calibration signal source (7) of one single frequency and a measuring circuit (113, 35, 101) coupled to an output (113) of the frequency demodulator (13) by controlling the output signal amplitude of the frequency demodulation circuit with a multiplier (21) which is controllable by the measuring circuit and forms part of a tuning correction circuit which optionally may further include a level shifting circuit (57). The frequency demodulation circuit is particularly suitable for use in a SECAM color television receiver, only one frequency demodulator then being required for demodulating both the two color difference signals and the identification signal.

Abstract: A digital demodulator (10) operates by multiplying an input signal with first and second orthogonal demodulation reference signals (Loa, LOb) to generate respective product signals, which are then integrated to generate first and second integrated values (a, b) indicative of digital data encoded in the input signal. These integrated values (a, b) are digitized to generate first and second digital values (a, b). A first error signal a-a) indicative of the difference between the first integrated value (a) and the first digital value (a) is generated, and the first error signal (a-a) is combined with the second digital value (b) to generate a first feedback signal. This first feedback signal is utilized to generate a control signal (ab-ba) indicative of phase difference between the input signal and the demodulation reference signals (LOa, LOb).

Abstract: A PLL circuit comprises a variable frequency divider (7) for frequency-dividing a signal having a reference frequency f.sub.1 with a frequency dividing ratio n.sub.1 or n.sub.2, a fixed frequency divider (8) for further frequency-dividing an output of the variable frequency divider with a frequency dividing ratio n.sub.0, to generate a first output signal and a second output signal which is out of phase by 90.degree. from the first output signal, multiplier (10) for multiplying an input signal by the second output signal, a comparator (11) for comparing an output of the multiplier with a predetermined reference voltage, and a D-type flip-flop (12) receiving as a D input an output of the comparator and receiving as a clock input the first output signal, an output of the D-type flip-flop (12) being applied to the variable frequency divider (7). When the second output signal leads the input signal by 90.degree.