Having Push-pull Amplifier Stage Patents (Class 330/255)
  • Patent number: 11152899
    Abstract: A multi-stage amplifier including a pre-driver stage, and method of operating the same. In one example, the amplifier includes an output stage with a first output transistor coupled to an oppositely doped second output transistor and to an output terminal. The pre-driver stage includes with a first driver transistor coupled to the first output transistor, and a second driver transistor coupled to the second output transistor. The pre-driver stage also includes a first current mirror and a second current mirror coupled to the first driver transistor and the second driver transistor. The pre-driver stage also includes a first translinear loop having a first translinear loop transistor and a second translinear loop having a second translinear loop transistor coupled to the first output transistor and the second output transistor.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: October 19, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Ravpreet Singh
  • Patent number: 11121688
    Abstract: An amplifier includes a first input transistor, a second input transistor, a first current mirror circuit, and a second current mirror circuit. The first input transistor is coupled to a first input terminal. The second input transistor is coupled to a second input terminal. The first current mirror circuit is coupled to the first input transistor and the second input transistor. The second current mirror circuit is coupled to the first input transistor, the second input transistor, and the first current mirror circuit.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: September 14, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Ravpreet Singh
  • Patent number: 11070180
    Abstract: A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Nitin Agarwal, Aniruddha Roy
  • Patent number: 11067609
    Abstract: A method of resistance compensation for measuring output current includes the following steps: (a) providing a secondary side loop of a conversion unit, and the secondary side loop includes a sense resistor and the first line. (b) providing a control unit for controlling the conversion unit, and the control unit is coupled to the first line and the sense resistor. (c) utilizing a first current to flow through the secondary side loop to obtain a first equivalent line resistance of the first line. (d) providing a second current by the control unit flowing through a loop of the sense resistor, the first line and the control unit to obtain a second equivalent line resistance of the second line. (e) compensating the sense resistor by the control unit according to the first equivalent line resistance and the second equivalent line resistance.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: July 20, 2021
    Assignee: CHICONY POWER TECHNOLOGY CO., LTD.
    Inventors: Tso-Jen Peng, Ssu-Hao Wang
  • Patent number: 11070181
    Abstract: A voltage driver circuit for an output stage of an operational amplifier, or other circuits, includes a level shifter and an output driver including a source follower and a common source amplifier in a push-pull configuration. The level shifter generates a node voltage as a function of an input voltage on the input node. The output driver including a first transistor having a control terminal receiving the node voltage, and connected between a supply voltage and an output node, and a second transistor having a control terminal receiving the input voltage from the input node, and connected between the output node and a reference voltage, wherein the first and second transistors have a common conductivity type.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: July 20, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Yih-Shan Yang
  • Patent number: 11068003
    Abstract: There is provided a differential amplifier including: an inverting input terminal to which a first voltage is applied; a non-inverting input terminal to which a second voltage proportional to the first voltage is applied; and an offset part configured to generate a predetermined input offset voltage between the inverting input terminal and the non-inverting input terminal.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: July 20, 2021
    Assignee: Rohm Co., Ltd.
    Inventors: Isao Takobe, Yuhei Yamaguchi, Tetsuo Tateishi
  • Patent number: 11054849
    Abstract: A source driver including an output buffer and a feedback circuit is provided. The output buffer includes an input stage circuit, an output stage circuit, a rising control circuit, and a falling control circuit. The input stage circuit correspondingly generates a first gate control voltage and a second gate control voltage according to an input voltage and a first feedback voltage. The output stage circuit correspondingly generates an output voltage according to the first gate control voltage and the second gate control voltage. The feedback circuit generates and outputs the first feedback voltage corresponding to the output voltage to the input stage circuit. The rising control circuit and the falling control circuit compare the input voltage with the first feedback voltage, and pull down (or pull up) the first gate control voltage and the second gate control voltage according to the comparison result.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: July 6, 2021
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventor: Chia-Chu Chien
  • Patent number: 11050413
    Abstract: A latched comparator includes a first amplification circuit, a second amplification circuit and a latch circuit. The first amplification circuit changes voltage levels of first and second output nodes based on first and second input signals when an operation speed of a semiconductor apparatus is relatively slow. The second amplification circuit changes voltage levels of third and fourth output nodes based on the first and second input signals when the operation speed of the semiconductor apparatus is relatively fast. The latch circuit generates first and second latch signals based on the voltage levels of the first and second output nodes or based on the voltage levels of the third and fourth output nodes according to the operation speed of the semiconductor apparatus.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventors: Gyu Tae Park, Young Ouk Kim
  • Patent number: 11012264
    Abstract: A line driver circuit includes a first input terminal, a second input terminal, a first input stage, a second input stage, a first output stage, and a second output stage. The first input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The second input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The first output stage includes a first input coupled to a first output terminal of the first input stage and a second input coupled to a first output terminal of the first input stage. A second output stage includes a first input coupled to a second output terminal of the first input stage and a second input coupled to a second output terminal of the first input stage.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: May 18, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rama Santosh Neelim Kumar Kattamuri, Sumantra Seth, Vikram Sharma
  • Patent number: 11004421
    Abstract: An operational amplifier circuit in a display apparatus which is fast-acting to prevent voltage overshoot comprises a pre-operational amplifier module, an output operational amplifier module, and an output module. Driving current from the pre-operational amplifier module is the basis of the output operational amplifier module generating a dynamic bias voltage to the output module. The output operational amplifier module detects the dynamic bias voltage and adjusts the bias voltage to be level with a specified voltage based on at least one control voltage. When the dynamic bias voltage is less than the specified voltage, the output operational amplifier module pulls up the bias voltage and when the bias voltage is larger than the specified voltage, the output operational amplifier module pulls down the bias voltage. The pull up and pull down speeds are proportional to the at least one control voltage.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 11, 2021
    Assignee: Fitipower Integrated Technology, Inc.
    Inventor: Kun-Tsung Lin
  • Patent number: 11005462
    Abstract: An interface device, including a plurality of interface circuits, wherein each interface circuit of the plurality of interface circuits includes a first switching element connected in series to a second switching element, and a first capacitor and a second capacitor connected to an output terminal to which the first switching element and the second switching element are connected; and a controller configured to determine a plurality of output signals corresponding to the plurality of interface circuits by controlling the first switching element and the second switching element, and configured to adjust a slew rate of the plurality of output signals by charging and discharging the first capacitor and the second capacitor.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jongmin Park
  • Patent number: 10985723
    Abstract: An electronic device for receiving a radio signal includes an upstream amplifier configured to amplify a received radio signal, a control module configured to control a gain of the upstream amplifier, and a mixer connected at the output of the upstream amplifier and configured to mix the signal from the upstream amplifier with a reference signal. The control module is further configured to perform an intermodulation detection, by commanding the generation by the upstream amplifier of a gain increase and comparing a first power with a second power, the first and second powers being respective powers of a signal at the output of the mixer, the first power being measured in the absence of gain increase and the second power being measured in the presence of the gain increase.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: April 20, 2021
    Assignee: Faurecia Clarion Electronics Europe
    Inventor: Cyril Laury
  • Patent number: 10924074
    Abstract: A differential input stage of a circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Drains of the first and third transistors couple together at a first node, and drains of the second and fourth transistors couple together at a second node. A first slew boost circuit includes a fifth transistor and a first current mirror. A gate of the fifth transistor couples to the second node. A source of the fifth transistor couples to the first node. The first current mirror couples to the fifth transistor and to the second node. A second slew boost circuit includes a sixth transistor and a second current mirror. A gate of the sixth transistor couples to the first node. A source of the sixth transistor couples to the second node. The second current mirror couples to the sixth transistor and to the first node.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: February 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Suresh Mallala, Nitin Agarwal
  • Patent number: 10902806
    Abstract: A half-power buffer amplifier is disclosed. The amplifier includes an amplification unit configured to differentially amplify differential input signals, the amplification unit including nodes configured to output differentially amplified first to fourth output signals, a first output buffer unit including first and second transistors, and an output node to which the first and second transistors are connected, a second output buffer unit including third and fourth transistors, wherein the third and fourth transistors are connected to the output node, a first control switch between the first output node and the second transistor and controlled by a polarity control signal, and a second control switch between the second output node and the third transistor and controlled by a complement of the polarity control signal.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: January 26, 2021
    Assignee: DB HiTek Co., Ltd.
    Inventors: Dong Gwi Choi, Mun Gyu Kim
  • Patent number: 10895604
    Abstract: Systems and methods to provide a low voltage interface coupleable between an energy storage device or a DC power source (e.g., fuel cell stack, battery) and one or more AC signal diagnostic systems. The low voltage interface reduces a voltage of the DC power source and supplies the reduced voltage to the one or more AC signal diagnostic systems without affecting the results of the measurements obtained by the one or more AC signal diagnostic systems. Such functionality provides a safer method for performing advanced analysis (e.g., EIS, frequency analysis) while utilizing lower cost and/or smaller components.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: January 19, 2021
    Assignees: Ballard Power Systems Inc., Simon Fraser University
    Inventors: Jacob W. Devaal, Hooman Homayouni, Farid Golnaraghi
  • Patent number: 10790916
    Abstract: A wireless communication unit (100) is described that comprises: at least one receiver configured to receive a radio frequency signal on at least one receiver channel (262, 264, 266, 268) and comprising a plurality of receiver circuits; at least one interference detection circuit (244, 248, 252) coupled to an output of at least one of the plurality of receiver circuits and configured to detect a saturation event of a signal output from the at least one of the plurality of receiver circuits; and a controller (114) configured to identify interference in a received signal.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 29, 2020
    Assignee: NXP B.V.
    Inventors: Gustavo Guarin Aristizabal, Arnaud Sion, Ralf Reuter, Marcel Welpot
  • Patent number: 10777119
    Abstract: A current corresponding to the difference between an input signal voltage and an output signal voltage is generated as an amplification acceleration current. The amplification acceleration current is sent to an output node of a current mirror, which drives a transistor in an output amplifier stage, and therefore added to a current to drive the transistor in the output amplifier stage.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 15, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hiroshi Tsuchi, Manabu Nishimizu, Yuushi Syutou
  • Patent number: 10694134
    Abstract: A comparison device includes a comparison circuit including input ports to receive a pixel signal and a ramp signal, respectively, and structured to compare the pixel signal and the ramp signal to output a comparison signal; a sensing circuit coupled to the comparison circuit and structured to sense a common voltage variation amount from the comparison circuit, wherein the common voltage variation amount depends on the pixel signal such that the common voltage variation amount increases as the pixel signal increases; and a tail current control circuit coupled to the sensing circuit and structured to control a tail current amount of the comparison circuit based on the common voltage variation amount.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 23, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyeon-June Kim, Hoe-Sam Jeong
  • Patent number: 10594277
    Abstract: An apparatus is provided which comprises: a differential input amplifying stage including a current source and a first node; a first matched pair of transistors coupled to the first node, wherein one of the transistors of the first matched pair is coupled to an output node of a driving stage; a second matched pair of transistors coupled to a second node to bias the second matched pair of transistors, wherein one of the transistors of the second matched pair of transistors is coupled to the output node of the driving stage, and wherein the second node is to be charged according to a first bias of the current source; and a resistive device coupled to the first and second nodes.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: March 17, 2020
    Assignee: Intel IP Corporation
    Inventor: John G. Kauffman
  • Patent number: 10594263
    Abstract: In an embodiment, a differential amplifier includes: an input stage; an output stage coupled to the input stage, the output stage having first and second output terminals; and a feedback circuit coupled to the output stage, where the feedback circuit is configured to dynamically adjust a bias current of the output stage based on voltages of the first and second output terminals.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: March 17, 2020
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Flavia Amorosa, Serge Ramet, Daniel Subiela
  • Patent number: 10574193
    Abstract: The present invention provides a class AB amplifier, wherein the class AB amplifier includes a cascode stage with a filter and an output stage. The cascode stage with the filter is arranged for receiving an input signal to generate a first driving signal and a second driving signal, wherein the filter filters the input signal to generate an filtered input signal, and at least one of the first driving signal and the second driving signal is generated according to the filtered input signal. The output stage is coupled to the cascode stage, and is arranged for generating an output signal according to the first driving signal and the second driving signal.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 25, 2020
    Assignee: MEDIATEK INC.
    Inventors: Jui-Yu Hsu, Yuan-Fu Lyu, Sheng-Hao Chen
  • Patent number: 10504471
    Abstract: A half-power buffer and/or amplifier is disclosed. The half-power buffer and/or amplifier includes an amplifying unit including first and second transistors connected between a first voltage source having a first voltage and a third voltage source having a third voltage, and a first output node configured to connect the first and second transistors and to output a voltage over a first voltage range between the first and third voltages, a second output buffer unit including third and fourth transistors connected between a second voltage source having a second voltage and the third voltage source, and a second output node configured to connect the third and fourth transistors and to output a voltage over a second voltage range between the second and third voltages, and a first charge share switch unit connected between the gate of the second transistor and the first voltage source, and configured to perform a charge share and/or equalization operation.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: December 10, 2019
    Assignee: DB HiTek, Co., Ltd.
    Inventors: Mun Gyu Kim, Seung Jin Yeo, Dong Gwi Choi, Kyoung Tae Kim
  • Patent number: 10491167
    Abstract: Methods, circuits, and apparatuses are disclosed that provide a buffer amplifier with lower output noise by narrow banding the amplifier. To reinvigorate the speed of the narrow-banded amplifier, a boost-on signal is initiated. The boost-on signal dynamically and rapidly injects a substantial current into the amplifier's bias current network to speed up its slew rate, when the amplifier's inputs get unbalanced when being subjected to a large transient differential input signal. Subsequently, after the amplifier regulate itself and as the amplifier's inputs approach substantial balance, a boost-off signal dynamically injects a slow and decaying current (that converges to the level of static steady-state bias current) into amplifier's bias circuitry, instead of turning off the boost current rapidly, which improves the amplifier's settling time.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: November 26, 2019
    Inventor: Ali Tasdighi Far
  • Patent number: 10454430
    Abstract: A circuit comprises: a circuit input; a circuit output; at least one passive feedback loop coupled between the circuit output and the circuit input; an active element, coupled in a feed-forward path of the circuit between the circuit input and the circuit output and configured to drive the at least one feedback loop in order to establish a function of the circuit, wherein the feed-forward path of the circuit comprises a second node (Vx) and a first node which are internal nodes of the active element and which are coupled between the circuit input and the circuit output, wherein the first node is configured to have a first voltage, the first voltage being a function of the circuit output, wherein the active element comprises a first voltage drop element coupled between the second node (Vx) and the first node.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: October 22, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Giuseppe Gramegna
  • Patent number: 10447210
    Abstract: Metal pillars are placed adjacent to transistor arrays in the power amplifiers that can be used in wireless devices. By placing the metal pillars in intimate contact with the silicon substrate and not over a substantial portion of the transistor arrays, the heat generated by the transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar forms a solder bump of a flip chip power amplifier die, which when soldered to a module, further conducts the heat away from the transistor array.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 15, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Michael Joseph McPartlin, Bharatjeet Singh Gill
  • Patent number: 10439559
    Abstract: A current feed-back instrumentation amplifier (CFIA) comprises a differential pair with degeneration for amplifying small differential voltages in the presence of large common-mode voltages. The CFIA includes input and feedback transconductors and a trimming circuit that trims the back-bias voltages of the transistors in each transconductor. The trimming circuit includes a plurality of selectable resistors disposed in the signal path of the tail current in each transconductor. Each of the plurality of selectable resistors has a switch coupled to it. When a switch is closed, only the resistors up to the respective switch are in the signal path of the bulk-to-source voltage of the differentially paired transistors. The resistor trimming circuit reduces the mismatch between transconductances of the respective differential pair transistors, in turn reducing mismatch of the overall transconductances of the transconductors, and thereby reducing the CFIA's gain error.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: October 8, 2019
    Assignee: Microchip Technology Incorporated
    Inventors: Serban Motoroiu, Jim Nolan
  • Patent number: 10439570
    Abstract: An operational amplifier includes an input stage configured to receive a first input voltage and a second input voltage and a slew boost circuit coupled to the input stage and configured to selectively increase current through the input stage. The operational amplifier also includes an output stage coupled to the input stage and configured to generate an output voltage, and a slew boost disable circuit configured to assert a control signal to the slew boost circuit to disable the slew boost circuit. The slew boost circuit is disabled when both: the first input voltage being more than a first threshold voltage different from the second input voltage and the output voltage failing to change by more than a second threshold rate.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 8, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Martijn Fridus Snoeij, Steven Graham Brantley
  • Patent number: 10411688
    Abstract: A method and apparatus for implementing a CMOS buffer for driving a reference voltage that consumes very low current in normal operating conditions but drive high current when output voltage is off, tracking the required reference voltage. The circuit is operating in a “deadzone” most of the time, where pull-up and pull-down current paths are blocked, and ultra-low power comparators, with build-in offset, are monitoring the output voltage continuously, and driving compensation current, when needed. The circuit can be manufactured with a standard CMOS processing technology.
    Type: Grant
    Filed: June 24, 2018
    Date of Patent: September 10, 2019
    Assignee: PLSense Ltd.
    Inventors: Tuvia Liran, Uzi Zangi, Tzach Hadas
  • Patent number: 10381986
    Abstract: A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. A output passive network can further generate a flat-phase response between dual resonances of operation.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Jong Seok Park, Yanjie J. Wang, Stefano Pellerano, Christopher D. Hull
  • Patent number: 10333478
    Abstract: An input stage of an operational amplifier receives first and second input voltages. An output slew detection circuit decreases a first current responsive to slewing of an output of the operational amplifier and increases the first current responsive to no slewing. A slew boost and differential input voltage detection generates a second current at a first level when the first and second input voltages are approximately equal and to generate the second current at a second level, smaller than the first level, responsive to the first and second input voltages not being approximately equal. A voltage on a capacitor increases responsive to the first current from the output slew detection circuit increasing and responsive to the second current being at the second level. A current mirror is activated responsive to the voltage on the capacitor exceeding a second threshold. The current mirror decreases a third current of the input stage.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 25, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Martijn Fridus Snoeij, Sudarshan Udayashankar
  • Patent number: 10326418
    Abstract: A circuit includes an input transistor pair with first and second input transistors, the first input transistor having a control terminal configured to receive an input signal and a cascode transistor pair including a first and second cascode transistors having a common control node. A bias circuit has a bias input configured to receive the input signal and a first bias output coupled to the common node of the first and second cascode transistors. The bias circuit includes a signal tracking circuit operating to generate the first bias output to track the input signal. A pair of load transistors are coupled to the input transistor pair and biased by a second bias output of the bias circuit.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: June 18, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Stefano Ramorini, Alberto Cattani, Alessandro Gasparini, Germano Nicollini
  • Patent number: 10264988
    Abstract: Systems and methods are disclosed herein for recording electrical signals in the presence of artifacts. The system and methods can employ multiple techniques for attenuating large, unwanted artifacts while preserving lower amplitude desirable signals. Aspects that can improve the recording of electrical signals in the presence of larger artifacts include particular electrode placement and spacing, high dynamic range amplification with good linearity, and signal blanking. Combinations of more or fewer techniques can be employed to achieve the desired attenuation of signal artifacts while preserving the desired signal. The systems and methods are suitable for recording neural signals in the presence of electrical stimulation signals.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: April 23, 2019
    Assignee: THE CHARLES STARK DRAPER LABORATORY, INC.
    Inventors: Brian Nugent, Robert Bousquet, Jesse J. Wheeler, Andrew Czarnecki, John Lachapelle
  • Patent number: 10262575
    Abstract: A current corresponding to the difference between an input signal voltage and an output signal voltage is generated as an amplification acceleration current. The amplification acceleration current is sent to an output node of a current mirror, which drives a transistor in an output amplifier stage, and therefore added to a current to drive the transistor in the output amplifier stage.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 16, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroshi Tsuchi, Manabu Nishimizu, Yuushi Syutou
  • Patent number: 10236840
    Abstract: Embodiments describe a transadmittance amplifier comprising an inverting output port and a non-inverting output port. The transadmittance amplifier comprising a first differential transistor pair having a first transistor comprising an inverting input port. The first transistor is configured to provide an output current to the inverting output port. A second transistor comprising a non-inverting input port. The second transistor is configured to provide an output current to the non-inverting output port. A second differential transistor pair having a third transistor comprising an inverting input port and a fourth transistor comprising a non-inverting input port. A first current source and a second current source. The transadmittance amplifier comprises a first current mirror which is configured to mirror an output current of the fourth transistor to the inverting output port and a second current mirror which is configured to mirror an output current of the third transistor to the non-inverting output port.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alessandro Cevrero, Ilter Özkaya, Thomas H. Toifl
  • Patent number: 10230334
    Abstract: An amplifier circuit including an input amplifier, an output amplifier and a diode device is provided. The output amplifier is coupled to the input amplifier and outputting an output voltage. The diode device is coupled between an output end and an input end of the output amplifier. When a voltage difference between the output end and the input end of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced. The diode device includes a variable resistor to increase the barrier voltage of the diode device.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: March 12, 2019
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chia-Wei Su, Ju-Lin Huang, Keko-Chun Liang
  • Patent number: 10227197
    Abstract: A method for reducing the effects of variations in an unwinding, convolutely wound roll of web material is disclosed. The method utilizes the steps of: a. selecting a reference objective relating to a downstream operation, b. choosing at least one feedback device correlated to the reference objective, c. collecting process data from the at least one feedback device at different positions within a time-varying operation cycle for at least one operation cycle at a learning speed, d. calculating an error as the difference between the collected process data from step (c) and a reference signal related to the selected reference objective, e. generating a correction signal based upon the calculated error from step (d) and, f. applying the correction signal to the actuator during a succeeding time-varying operation cycle.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: March 12, 2019
    Assignee: The Procter & Gamble Plaza
    Inventors: Jason Lee DeBruler, Paul Anthony Kawka, Andrew Price Palmer
  • Patent number: 10216680
    Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Tzu-Chien Hsueh, Ganesh Balamurugan, Bryan K. Casper
  • Patent number: 10186205
    Abstract: The present disclosure provides a source driving circuit, a source driving device, a display panel and a display apparatus, which relate to the field of display technology, and can solve the problem that the conventional source driving circuit has large power consumption and a short lifetime.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: January 22, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Szu Heng Tseng
  • Patent number: 10185347
    Abstract: A circuit arrangement comprising a first capacitor and a second capacitor which are arranged in series between a high potential and a low potential is described. The circuit arrangement comprises first power consuming circuitry which is arranged in parallel to the first capacitor. The first power consuming circuitry (113) consumes electrical power at a first voltage. The circuit arrangement comprises second power consuming circuitry which is arranged in parallel to the second capacitor. The second power consuming circuitry consumes electrical power at a second voltage, wherein a magnitude of the sum of the first voltage and the second voltage is smaller than an absolute difference between the high potential and the low potential. The circuit arrangement sets a voltage at the first capacitor in accordance to the first voltage and to set a voltage at the second capacitor in accordance to the second voltage.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: January 22, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Horst Knoedgen
  • Patent number: 10181824
    Abstract: Metal pillars are placed adjacent to NPN transistor arrays that are used in the power amplifier for RF power generation. By placing the metal pillars in intimate contact with the silicon substrate, the heat generated by the NPN transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar also forms an electrical ground connection in close proximity to the NPN transistors to function as a grounding point for emitter ballast resistors, which form an optimum electrothermal configuration for a linear SiGe power amplifier.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: January 15, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Michael Joseph McPartlin, Bharatjeet Singh Gill
  • Patent number: 10181821
    Abstract: The present invention provides a frequency-compensated transconductance amplifier, includes an input stage consisting of NMOS transistors M1 and M2, a first-stage active load consisting of PMOS transistors M3 and M4, a first-stage tail current source consisting of a constant current source Iss, a second-stage input transistor consisting of a PMOS transistor M5, a second-stage constant current source consisting of an NMOS transistor M6, a load capacitor consisting of a capacitor CL, and a frequency compensation network formed by sequentially connecting a gain stage GAIN, a compensating resistor Rc and a compensating capacitor Cc in series.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: January 15, 2019
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION 24TH RESEARCH INSTITUTE
    Inventors: Daiguo Xu, Gangyi Hu, Ruzhang Li, Jian'an Wang, Guangbing Chen, Yuxin Wang, Tao Liu, Lu Liu, Minming Deng, Hanfu Shi, Xu Wang
  • Patent number: 10177716
    Abstract: Metal pillars are placed adjacent to NPN transistor arrays that are used in the power amplifier for RF power generation. By placing the metal pillars in intimate contact with the silicon substrate, the heat generated by the NPN transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar also forms an electrical ground connection in close proximity to the NPN transistors to function as a grounding point for emitter ballast resistors, which form an optimum electrothermal configuration for a linear SiGe power amplifier.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: January 8, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Michael Joseph McPartlin, Bharatjeet Singh Gill
  • Patent number: 10177713
    Abstract: Methods, circuits, and apparatuses that provide Buffer Amplifier, containing Amplifiers and Buffer Drivers, one or more of the following: ultra low power Buffer Amplifier, capable of having high gain, low noise, high speed, near rail-to-rail input-output voltage span, high sink-source current drive capability for an external load, and able to operate at low power supply voltages. Methods, circuits, and apparatuses that provide regulated cascode (RGC) current mirrors (CM) capable of operating at low power supply and having wide input-output voltage spans.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 8, 2019
    Inventor: Ali Tasdighi Far
  • Patent number: 10148236
    Abstract: An embodiment discloses an operational amplifier comprising: an input stage; an output stage communicatively coupled to the input stage, wherein the output stage further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first current source, a fifth transistor, a sixth transistor and a second current source, wherein a second node of the first transistor is connected to the input stage (vin), a third node of the first transistor is connected to a third node of the fourth transistor, ground (gnd), a third node of the fifth transistor and a third node of the third transistor, a first node of the first transistor is connected to a first node of the first current source, a second node of the sixth transistor and a second node of the second transistor.
    Type: Grant
    Filed: August 27, 2017
    Date of Patent: December 4, 2018
    Assignee: BEKEN CORPORATION
    Inventors: Jiazhou Liu, Dawei Guo
  • Patent number: 10141897
    Abstract: A source follower includes a first transistor, a first output module, a second transistor, a second output module and a feedback module. The first terminal and the control terminal of the first transistor are configured to respectively receive a first base voltage and a first control voltage. The second terminal of the first transistor and the first output module are electrically connected to a first output terminal. The first terminal and the control terminal of the second transistor are configured to respectively receive a first base voltage and a second control voltage. The second terminal of the second transistor and the second output module are electrically connected to a second output terminal. The feedback module is electrically connected to the control terminal of the first transistor, the control terminal of the second transistor and a reference node of the second output module.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: November 27, 2018
    Assignee: SILICON INTERGRATED SYSTEMS CORP.
    Inventors: Ssu-Che Yang, Wen-Chi Lin, Keng-Nan Chen
  • Patent number: 10129657
    Abstract: A loudspeaker enclosure designed to convert an electrical input signal into sound signals is provided. The enclosure comprises a signal processor suitable for generating, from the electrical input signal, a modulated electrical signal using an ultrasonic carrier. The enclosure comprises a source suitable for producing ultrasonic signals from the modulated electrical signal and for broadcasting said ultrasonic signals through a medium. The carrier is chosen such that the sound signals are at least partially produced while the ultrasonic signals are passing through the medium. A buffer device is suitable for allowing the transmission of the modulated electrical signal to said at least two piezo-electric transducers of the group and for keeping the voltage observed at the terminals of said at least two piezo-electric transducers of the group substantially equal to the voltage observed at the output of the signal processor.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: November 13, 2018
    Assignee: AKOUSTIC ARTS
    Inventors: Philippe Robin, Ilan Kaddouch
  • Patent number: 10122334
    Abstract: An amplifier comprising an active device having an output terminal for driving a load impedance in response to a signal applied to an input terminal and a current source connected to the active device to provide a bias to the active device wherein when the active device is operated an output power of the active device increases with increasing load impedance.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: November 6, 2018
    Inventor: Fadhel M Ghannouchi
  • Patent number: 9998000
    Abstract: Methods and systems of controlling a switched capacitor converter are provided. Upon determining that a voltage across a flying capacitor is above a first threshold, a first current is drawn from a first terminal of the flying capacitor by a first current source, and a second current is provided to a second terminal of the flying capacitor by a second current source. Upon determining that the voltage across the flying capacitor is below a second threshold, the first current is provided to the first terminal of the flying capacitor by the first current source, and the second current is drawn from the second terminal of the flying capacitor by the second current source. Upon determining that the voltage across the flying capacitor is above the second threshold and below the first threshold from the reference voltage, the first and second current sources are turned OFF.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 12, 2018
    Assignee: LINEAR TECHNOLOGY CORPORATION
    Inventors: Xu Zhang, Jian Li, San Hwa Chee
  • Patent number: 9991903
    Abstract: A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: June 5, 2018
    Assignee: INNOAXIS CO., LTD
    Inventor: Hwi-Cheol Kim
  • Patent number: 9985633
    Abstract: A voltage clamping system includes: (a) a first electronic device connected to a first power source and having a signal output node, a voltage clamp high node, and a voltage clamp low node, wherein the voltage clamp high node and the voltage clamp low node are coupled to a second power source different than the first power source; and (b) a second electronic device powered by the second power source and having a signal input node coupled to the signal output node of the first electronic device. The signal output node of the first electronic device is passively clamped, with low distortion, approximately rail-to-rail with respect to the second power source such that the second electronic device is protected from damage due to excessive voltage levels.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: May 29, 2018
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Gabriel E. Tanase, Michael B. Francon