Having Push-pull Amplifier Stage Patents (Class 330/255)
  • Patent number: 10264988
    Abstract: Systems and methods are disclosed herein for recording electrical signals in the presence of artifacts. The system and methods can employ multiple techniques for attenuating large, unwanted artifacts while preserving lower amplitude desirable signals. Aspects that can improve the recording of electrical signals in the presence of larger artifacts include particular electrode placement and spacing, high dynamic range amplification with good linearity, and signal blanking. Combinations of more or fewer techniques can be employed to achieve the desired attenuation of signal artifacts while preserving the desired signal. The systems and methods are suitable for recording neural signals in the presence of electrical stimulation signals.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: April 23, 2019
    Assignee: THE CHARLES STARK DRAPER LABORATORY, INC.
    Inventors: Brian Nugent, Robert Bousquet, Jesse J. Wheeler, Andrew Czarnecki, John Lachapelle
  • Patent number: 10262575
    Abstract: A current corresponding to the difference between an input signal voltage and an output signal voltage is generated as an amplification acceleration current. The amplification acceleration current is sent to an output node of a current mirror, which drives a transistor in an output amplifier stage, and therefore added to a current to drive the transistor in the output amplifier stage.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 16, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroshi Tsuchi, Manabu Nishimizu, Yuushi Syutou
  • Patent number: 10236840
    Abstract: Embodiments describe a transadmittance amplifier comprising an inverting output port and a non-inverting output port. The transadmittance amplifier comprising a first differential transistor pair having a first transistor comprising an inverting input port. The first transistor is configured to provide an output current to the inverting output port. A second transistor comprising a non-inverting input port. The second transistor is configured to provide an output current to the non-inverting output port. A second differential transistor pair having a third transistor comprising an inverting input port and a fourth transistor comprising a non-inverting input port. A first current source and a second current source. The transadmittance amplifier comprises a first current mirror which is configured to mirror an output current of the fourth transistor to the inverting output port and a second current mirror which is configured to mirror an output current of the third transistor to the non-inverting output port.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alessandro Cevrero, Ilter Özkaya, Thomas H. Toifl
  • Patent number: 10230334
    Abstract: An amplifier circuit including an input amplifier, an output amplifier and a diode device is provided. The output amplifier is coupled to the input amplifier and outputting an output voltage. The diode device is coupled between an output end and an input end of the output amplifier. When a voltage difference between the output end and the input end of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced. The diode device includes a variable resistor to increase the barrier voltage of the diode device.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: March 12, 2019
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chia-Wei Su, Ju-Lin Huang, Keko-Chun Liang
  • Patent number: 10227197
    Abstract: A method for reducing the effects of variations in an unwinding, convolutely wound roll of web material is disclosed. The method utilizes the steps of: a. selecting a reference objective relating to a downstream operation, b. choosing at least one feedback device correlated to the reference objective, c. collecting process data from the at least one feedback device at different positions within a time-varying operation cycle for at least one operation cycle at a learning speed, d. calculating an error as the difference between the collected process data from step (c) and a reference signal related to the selected reference objective, e. generating a correction signal based upon the calculated error from step (d) and, f. applying the correction signal to the actuator during a succeeding time-varying operation cycle.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: March 12, 2019
    Assignee: The Procter & Gamble Plaza
    Inventors: Jason Lee DeBruler, Paul Anthony Kawka, Andrew Price Palmer
  • Patent number: 10216680
    Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Tzu-Chien Hsueh, Ganesh Balamurugan, Bryan K. Casper
  • Patent number: 10185347
    Abstract: A circuit arrangement comprising a first capacitor and a second capacitor which are arranged in series between a high potential and a low potential is described. The circuit arrangement comprises first power consuming circuitry which is arranged in parallel to the first capacitor. The first power consuming circuitry (113) consumes electrical power at a first voltage. The circuit arrangement comprises second power consuming circuitry which is arranged in parallel to the second capacitor. The second power consuming circuitry consumes electrical power at a second voltage, wherein a magnitude of the sum of the first voltage and the second voltage is smaller than an absolute difference between the high potential and the low potential. The circuit arrangement sets a voltage at the first capacitor in accordance to the first voltage and to set a voltage at the second capacitor in accordance to the second voltage.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: January 22, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Horst Knoedgen
  • Patent number: 10186205
    Abstract: The present disclosure provides a source driving circuit, a source driving device, a display panel and a display apparatus, which relate to the field of display technology, and can solve the problem that the conventional source driving circuit has large power consumption and a short lifetime.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: January 22, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Szu Heng Tseng
  • Patent number: 10181821
    Abstract: The present invention provides a frequency-compensated transconductance amplifier, includes an input stage consisting of NMOS transistors M1 and M2, a first-stage active load consisting of PMOS transistors M3 and M4, a first-stage tail current source consisting of a constant current source Iss, a second-stage input transistor consisting of a PMOS transistor M5, a second-stage constant current source consisting of an NMOS transistor M6, a load capacitor consisting of a capacitor CL, and a frequency compensation network formed by sequentially connecting a gain stage GAIN, a compensating resistor Rc and a compensating capacitor Cc in series.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: January 15, 2019
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION 24TH RESEARCH INSTITUTE
    Inventors: Daiguo Xu, Gangyi Hu, Ruzhang Li, Jian'an Wang, Guangbing Chen, Yuxin Wang, Tao Liu, Lu Liu, Minming Deng, Hanfu Shi, Xu Wang
  • Patent number: 10181824
    Abstract: Metal pillars are placed adjacent to NPN transistor arrays that are used in the power amplifier for RF power generation. By placing the metal pillars in intimate contact with the silicon substrate, the heat generated by the NPN transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar also forms an electrical ground connection in close proximity to the NPN transistors to function as a grounding point for emitter ballast resistors, which form an optimum electrothermal configuration for a linear SiGe power amplifier.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: January 15, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Michael Joseph McPartlin, Bharatjeet Singh Gill
  • Patent number: 10177713
    Abstract: Methods, circuits, and apparatuses that provide Buffer Amplifier, containing Amplifiers and Buffer Drivers, one or more of the following: ultra low power Buffer Amplifier, capable of having high gain, low noise, high speed, near rail-to-rail input-output voltage span, high sink-source current drive capability for an external load, and able to operate at low power supply voltages. Methods, circuits, and apparatuses that provide regulated cascode (RGC) current mirrors (CM) capable of operating at low power supply and having wide input-output voltage spans.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 8, 2019
    Inventor: Ali Tasdighi Far
  • Patent number: 10177716
    Abstract: Metal pillars are placed adjacent to NPN transistor arrays that are used in the power amplifier for RF power generation. By placing the metal pillars in intimate contact with the silicon substrate, the heat generated by the NPN transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar also forms an electrical ground connection in close proximity to the NPN transistors to function as a grounding point for emitter ballast resistors, which form an optimum electrothermal configuration for a linear SiGe power amplifier.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: January 8, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Michael Joseph McPartlin, Bharatjeet Singh Gill
  • Patent number: 10148236
    Abstract: An embodiment discloses an operational amplifier comprising: an input stage; an output stage communicatively coupled to the input stage, wherein the output stage further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first current source, a fifth transistor, a sixth transistor and a second current source, wherein a second node of the first transistor is connected to the input stage (vin), a third node of the first transistor is connected to a third node of the fourth transistor, ground (gnd), a third node of the fifth transistor and a third node of the third transistor, a first node of the first transistor is connected to a first node of the first current source, a second node of the sixth transistor and a second node of the second transistor.
    Type: Grant
    Filed: August 27, 2017
    Date of Patent: December 4, 2018
    Assignee: BEKEN CORPORATION
    Inventors: Jiazhou Liu, Dawei Guo
  • Patent number: 10141897
    Abstract: A source follower includes a first transistor, a first output module, a second transistor, a second output module and a feedback module. The first terminal and the control terminal of the first transistor are configured to respectively receive a first base voltage and a first control voltage. The second terminal of the first transistor and the first output module are electrically connected to a first output terminal. The first terminal and the control terminal of the second transistor are configured to respectively receive a first base voltage and a second control voltage. The second terminal of the second transistor and the second output module are electrically connected to a second output terminal. The feedback module is electrically connected to the control terminal of the first transistor, the control terminal of the second transistor and a reference node of the second output module.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: November 27, 2018
    Assignee: SILICON INTERGRATED SYSTEMS CORP.
    Inventors: Ssu-Che Yang, Wen-Chi Lin, Keng-Nan Chen
  • Patent number: 10129657
    Abstract: A loudspeaker enclosure designed to convert an electrical input signal into sound signals is provided. The enclosure comprises a signal processor suitable for generating, from the electrical input signal, a modulated electrical signal using an ultrasonic carrier. The enclosure comprises a source suitable for producing ultrasonic signals from the modulated electrical signal and for broadcasting said ultrasonic signals through a medium. The carrier is chosen such that the sound signals are at least partially produced while the ultrasonic signals are passing through the medium. A buffer device is suitable for allowing the transmission of the modulated electrical signal to said at least two piezo-electric transducers of the group and for keeping the voltage observed at the terminals of said at least two piezo-electric transducers of the group substantially equal to the voltage observed at the output of the signal processor.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: November 13, 2018
    Assignee: AKOUSTIC ARTS
    Inventors: Philippe Robin, Ilan Kaddouch
  • Patent number: 10122334
    Abstract: An amplifier comprising an active device having an output terminal for driving a load impedance in response to a signal applied to an input terminal and a current source connected to the active device to provide a bias to the active device wherein when the active device is operated an output power of the active device increases with increasing load impedance.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: November 6, 2018
    Inventor: Fadhel M Ghannouchi
  • Patent number: 9998000
    Abstract: Methods and systems of controlling a switched capacitor converter are provided. Upon determining that a voltage across a flying capacitor is above a first threshold, a first current is drawn from a first terminal of the flying capacitor by a first current source, and a second current is provided to a second terminal of the flying capacitor by a second current source. Upon determining that the voltage across the flying capacitor is below a second threshold, the first current is provided to the first terminal of the flying capacitor by the first current source, and the second current is drawn from the second terminal of the flying capacitor by the second current source. Upon determining that the voltage across the flying capacitor is above the second threshold and below the first threshold from the reference voltage, the first and second current sources are turned OFF.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 12, 2018
    Assignee: LINEAR TECHNOLOGY CORPORATION
    Inventors: Xu Zhang, Jian Li, San Hwa Chee
  • Patent number: 9991903
    Abstract: A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: June 5, 2018
    Assignee: INNOAXIS CO., LTD
    Inventor: Hwi-Cheol Kim
  • Patent number: 9985633
    Abstract: A voltage clamping system includes: (a) a first electronic device connected to a first power source and having a signal output node, a voltage clamp high node, and a voltage clamp low node, wherein the voltage clamp high node and the voltage clamp low node are coupled to a second power source different than the first power source; and (b) a second electronic device powered by the second power source and having a signal input node coupled to the signal output node of the first electronic device. The signal output node of the first electronic device is passively clamped, with low distortion, approximately rail-to-rail with respect to the second power source such that the second electronic device is protected from damage due to excessive voltage levels.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: May 29, 2018
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Gabriel E. Tanase, Michael B. Francon
  • Patent number: 9973152
    Abstract: One example includes an amplifier system. The system includes a gain stage configured to conduct a gain current in response to an input voltage. The system also includes a current limit stage coupled to the gain stage and being configured to one of source and sink the gain current and to define a limit amplitude of the gain current during a current limit condition. The system further includes an output stage coupled to the gain stage and configured to conduct an output current through an output node in response to the gain current, the output current having a maximum amplitude during the current limit condition that is proportional to the limit amplitude.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: May 15, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Daijiro Otani, Keita Ikai
  • Patent number: 9967688
    Abstract: To be able to activate a self-device when an input digital audio signal is an audio signal indicating sound. An AV receiver 1 includes a detection circuit 4 that detects that a digital audio signal terminal is connected and supplies a detection signal, a DIR 5 that converts an SPDIF signal into an I2S signal when the detection circuit 4 supplies the detection signal, a detection circuit 7 that detects that the I2S signal into which the DIR 5 convers is an audio signal indicating sound and supplies a detection signal, and a microcomputer 2 that activates the AV receiver 1 when the detection circuit 7 supplies the detection signal.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 8, 2018
    Assignee: Onkyo Corporation
    Inventors: Kuniaki Yamamoto, Tetsuya Nagano
  • Patent number: 9964985
    Abstract: An apparatus having a first coupling network configured to receive an input voltage and output a first gate voltage and a second gate voltage at a first gate node and a second gate node, respectively; a stacked complementary common-source amplifier pair including a first common-source amplifier and a second common-source amplifier configured to receive the first gate voltage and the second gate voltage and output a first drain voltage and a second drain voltage at a first drain node and a second drain node, respectively; a second coupling network configured to provide a coupling between the first drain node and the second drain node to equalize the first drain voltage and the second drain voltage. A first inductor and second inductor couple the first and second drain nodes to a first and second DC node, respectively. Third and fourth inductors are coupled to the first and second inductor.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: May 8, 2018
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Poh-Boon Leong
  • Patent number: 9929708
    Abstract: An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: March 27, 2018
    Assignee: ETHERTRONICS, INC.
    Inventor: Farbod Aram
  • Patent number: 9924904
    Abstract: In an example, an electrical circuit device for amplifying a physiological signal includes a modulation unit configured to receive an input signal, to modulate the input signal to produce a modulated signal. The device also includes an amplification and transconductance unit configured to amplify an amplitude of the modulated signal and increase a transconductance of the modulated signal to produce a transconductance enhanced modulated and amplified signal, where the amplification and transconductance unit comprises at least a first complementary pair of transistors and a second complementary pair of transistors configured to receive the modulated signal and to amplify and increase the transconductance of the modulated signal. The device also includes a demodulation unit configured to receive the transconductance enhanced modulated and amplified signal and to demodulate the signal.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: March 27, 2018
    Assignee: Medtronic, Inc.
    Inventors: Peng Cong, Michael B. Terry
  • Patent number: 9911471
    Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: March 6, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Shuichi Tsukada
  • Patent number: 9899973
    Abstract: Split cascade circuits include multiple cascade paths coupled between voltage supply rails. Each cascade path includes a pair of controllable switches. A feedback path is provided for at least one of the cascade circuit paths. An active load circuit may also have a split cascade structure. Multiple-stage circuits, for implementation in Trans-Impedance Amplifiers (TIAs) or analog Receive Front-End modules (RXFEs), for example, include multiple stages of split cascade circuits.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: February 20, 2018
    Assignee: INPHI CORPORATION
    Inventors: Florin Pera, Stephane Dallaire, Brian Wall
  • Patent number: 9899964
    Abstract: An amplifier arrangement comprising first and second power amplifiers (T1, T2) having drains connected to positive and negative drive voltages, respectively, and gates connected to an input signal. The arrangement further comprises first and second current sensors (1, 2) for detecting first and second drain currents from the power amplifiers, processing circuitry (3) adapted to identify the smallest drain current, and a feedback control loop (5) and means for driving a bias current dependent on a feedback signal through a resistor connected between the input signal and the gate of an inactive one of the first and second power amplifiers. The control loop will keep the idle current constant in the transistor with the lowest current (the inactive transistor). Thereby, the current running in the transistor which does not deliver current to the load will be fixed at a desired value.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: February 20, 2018
    Assignee: BANG & OLUFSEN A/S
    Inventors: Jørgen Selmer Jensen, Jens Nørmølle Rasmussen
  • Patent number: 9875693
    Abstract: A data driver includes a data signal converter to convert image data to a data signal, an output buffer to output the data signal to a data line, a first cascode circuit connected to the output buffer and including a plurality of transistors, a first noise attenuator connected to a first node between the output buffer and the first cascode circuit, and to attenuate a first current noise, a second cascode circuit connected to the output buffer and including a plurality of transistors, a second noise attenuator connected a second node between the output buffer and the second cascode circuit, and to attenuate a second current noise, a current integrator to generate an integrated voltage by integrating a first current flowing through the first cascode circuit and a second current flowing through the second cascade circuit, and an analog-digital converter (ADC) to convert the integrated voltage to a digital signal.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: January 23, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Oh-Jo Kwon, Ji-Woong Kim, Choong-Sun Shin, Joo-Hyung Lee, Jun-Suk Bang, Gyu-Hyeong Cho
  • Patent number: 9876477
    Abstract: In a folded cascode operational amplifier circuit, a source is connected to a back gate in each of third and fourth transistors that are cascode-connected to first and second transistors, which are an electric current source that returns an electric current signal output by a differential pair of an input stage. In the third and fourth transistors, an active parasitic element exists due to its device structure. When a falling edge signal of a rectangular wave is input, and electric current is supplied to the source of the third transistor to increase its electric potential, electric current flows into the drain from the back gate via the active parasitic element in an on state, in order to rapidly charge a capacitor. Thereby, a fifth transistor turns on within a shorter time, in order to improve an internal slew rate.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: January 23, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Motomitsu Iwamoto
  • Patent number: 9793805
    Abstract: A charge pump circuit may include an output node, a current source circuit, a current sink circuit, a first amplifier circuit, and a second amplifier circuit. The current source circuit may be configured to source current to the output node. The current sink circuit may be configured to sink current from the output node. The first amplifier circuit may be configured to adjust a first amount of current sourced by the current source circuit based on a voltage on the output node. The second amplifier circuit may be configured to adjust the first amount of current sourced by the current source circuit or a second amount of current sunk by the current sink circuit based on the voltage on the output node.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: October 17, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Nikola Nedovic
  • Patent number: 9709603
    Abstract: A current sensing system constituted of: an impedance element; a switching network arranged to alternately couple a first end of the impedance element between a supply voltage and return, the impedance element arranged to develop a voltage there across reflecting a current flow to a load coupled to the second end of the impedance element; a first stage amplifier, a first and second input thereof respectively coupled to the first and second end of the impedance element, a power supply input thereof coupled to a voltage greater than the supply voltage and a return thereof coupled to the first end of the impedance element, the amplifier having a first and second output, the potential difference reflecting the impedance element voltage times a first stage gain; and a second stage amplifier, a first and second input thereof respectively coupled to a first and second output of the first stage amplifier.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: July 18, 2017
    Assignee: Microsemi Corporation
    Inventor: Bruce Ferguson
  • Patent number: 9705395
    Abstract: A fault tolerant power supply system includes at least one load switch configured to connect an input voltage to an output node of the load switch when the load switch is turned on and at least one power channel coupled to the load switch to receive the input voltage. The power channel is configured as a buck converter and includes at least a high-side power switch and a low-side power switch. The fault tolerant power supply system is configured to measure a current flowing through the low-side power switch, to determine that the current flowing through the low-side power switch has exceeded a current limit threshold, and to disable the low-side power switch and the load switch in response to the determination that the current flowing in the low-side power switch has exceeded the current limit threshold.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: July 11, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Mark Tomas, Zhiye Zhang, Allen Chang, Kuang Ming Chang, Gilbert Lee
  • Patent number: 9698760
    Abstract: Systems, methods, and other embodiments associated with a continuous-time analog delay device are described. According to one embodiment, a device includes a first terminal connected to an input line to receive an input signal. The device includes a first differential pair of transistors comprising a first transistor and a second transistor, wherein a gate of the second transistor is connected to the first terminal. The device includes a second differential pair of transistors comprising a third transistor and a fourth transistor, wherein a gate of the third transistor is connected to the first terminal. The device includes a first load connected to a drain of the third transistor. The device includes a second load connected to a drain of the fourth transistor. The device includes at least one capacitor connected in parallel between the first load and the second load.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: July 4, 2017
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventor: Riccardo Tonietto
  • Patent number: 9654091
    Abstract: A comparator has an input stage having (i) resistor-coupled super source-follower circuits that convert differential input voltages into differential currents and (ii) hysteresis current-injection circuits that inject hysteresis currents into the differential currents. An output stage processes the differential currents to control the comparator output. Common-mode (CM) detection circuits inhibit some of the differential currents from reaching the output stage if the CM voltage is too close to a voltage rail of the comparator. The comparator is able to operate at CM voltages over the entire rail-to-rail range with constant hysteresis voltage.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: May 16, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jianzhou Wu, Jie Jin, Yikun Mo, Yang Wang
  • Patent number: 9641127
    Abstract: Aspects of the disclosure provide an operational transconductance amplifier (OTA) having an output stage. The output stage includes a first amplifier path configured to drive a first output current from a first power supply and a first resistor coupled between the first power supply and a source terminal of a first transistor in the first amplifier path. The first resistor is configured to improve a linearity of the OTA.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: May 2, 2017
    Assignee: Marvell Semiconductor, Inc.
    Inventors: Zhigang Xu, Junxiong Deng, Taotao Yan
  • Patent number: 9634688
    Abstract: An integrator including: a resistive element connected to an input terminal; an operational amplifier configured to receive, through the resistive element, an input signal that has been supplied to the input terminal; and a voltage regulator circuit connected to an intermediate node between the resistive element and the operational amplifier. The voltage regulator circuit has a first current source connected to the intermediate node, and a switch connected between the intermediate node and the first current source and selectively turning ON or OFF.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: April 25, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Yosuke Mitani, Takashi Morie, Kazuo Matsukawa
  • Patent number: 9608575
    Abstract: A signal amplifying circuit with noise suppression function includes a first circuit module and a second circuit module. The first circuit module includes a current source and a switch. The current source is connected to an input stage for inputting a current. The switch is connected to a first output terminal and adapted to switch the input stage and the first output terminal according to a chopping frequency. The second circuit module includes an equivalent capacitance disposed between an output stage and a second input terminal connected to the first output terminal. The signal amplifying circuit controls current volume of the current source and capacity value of the equivalent capacitance to accordingly adjust an interior frequency bandwidth of the signal amplifying circuit, and the interior frequency bandwidth is smaller than the chopping frequency and greater than an input signal of the input stage.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: March 28, 2017
    Assignee: PixArt Imaging Inc.
    Inventors: Hsiang-Wei Hwang, Jui-Te Chiu
  • Patent number: 9564857
    Abstract: A low noise amplifier and a chip. The amplifier includes a biasing circuit unit, a first amplifying circuit unit, a first adjusting unit, a first signal input, a second signal input and a first signal output; the biasing circuit unit includes a first voltage output and a second voltage output; the first amplifying circuit unit includes a first N-type transistor, a first P-type transistor, a first output capacitor, a second output capacitor, a first impedance and a second impedance; gates of first N-type and P-type transistors are connected to first voltage output and first signal input, and second voltage output and first signal input, respectively, via adjusting unit; source of first N-type transistor is connected to source of first P-type transistor and second signal input; drains of first N-type and P-type transistors are connected respectively to impedance, and to first signal output and second signal output via output capacitor.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: February 7, 2017
    Assignee: SHANGHAI EASTSOFT MICROELECTRONICS CO., LTD.
    Inventors: Jingjing Tao, Xu Zhang, Ruijin Liu
  • Patent number: 9564855
    Abstract: Adaptive biasing circuits for input differential pairs of a buffer or an amplifier adapt to autozero currents for discrete pair selection or continuous pair selection. The adaptive biasing circuits include a multistage device including current source and follower devices with a plurality of switches for a two-phase operation: autozero and amplifying phases. During an autozero phase, input differential pairs are isolated from subsequent stages and biasing currents are determined for autozeroing of input offset voltages. During an amplifying phase, both input differential pairs can be coupled to subsequent stages for continuous selection or a selected input differential pair can be coupled to subsequent stages for discrete selection.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: February 7, 2017
    Assignee: Analog Devices Global
    Inventor: Gerard Mora-Puchalt
  • Patent number: 9531336
    Abstract: An operational amplifier, including an input stage circuit, an output stage circuit and a constant-gm circuit is provided. The input stage circuit provides a driving voltage according to an input voltage. Input terminals of the output stage circuit receive the driving voltage, and an output terminal of the output stage circuit provides an output voltage according to the driving voltage. The constant-gm circuit includes a constant-gm switch circuit, a current mirror circuit and a current mirror switch circuit. The constant-gm switch circuit controls the operation of the constant-gm circuit. The constant-gm switch circuit allows the current mirror circuit to operate during a transient time when the driving voltage is transited according to the driving voltage, so as to provide a compensated current for the input stage circuit. When the driving voltage is during a non-transient time, the current mirror switch circuit turns off the current mirror circuit.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: December 27, 2016
    Assignee: Novatek Microelectronics Corp.
    Inventor: Ji-Ting Chen
  • Patent number: 9515610
    Abstract: A line driver and a method for driving a load are proposed. The line driver includes a current amplifier and a feedback network. The current amplifier has an input node arranged to receive an input current of the line driver, and an output node arranged to produce an output current. The feedback network is coupled between the input node and the output node of the current amplifier, wherein a portion of the output current of the line driver is guided to the feedback network, and an equivalent impedance obtained by looking into the output node of the current amplifier with the feedback network substantially equals an impedance of the load.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: December 6, 2016
    Assignee: MEDIATEK INC.
    Inventor: Wen-Hua Chang
  • Patent number: 9496012
    Abstract: According to at least one example embodiment, a method and corresponding system, or circuit, for calibrating a reference voltage of a single-ended receiver, include applying a clock signal and a reference voltage signal as inputs to the differential amplifier of the single-ended receiver. The differential amplifier provides an output signal, the output signal is processed, and an indication of a duty cycle associated with an output signal of the amplifier is evaluated. Based on the evaluated indication of the duty cycle, a control logic module, or circuit, adjusts a level of the reference voltage signal. The process of evaluating the indication of the duty cycle and adjusting the reference voltage level is repeated for a number of iterations.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 15, 2016
    Assignee: Cavium, Inc.
    Inventors: Omer O. Yildirim, David Lin, Scott E. Meninger
  • Patent number: 9495933
    Abstract: An analog data transmitter applied in a LCD apparatus includes an output pad, a channel operational amplifier, an initial switch, an auxiliary switch module, and a detection unit. The detection unit selectively starts a first switch unit or a second switch unit of the auxiliary switch module according to a pulse width modulation corresponding to a data conversion amplitude of an output data signal outputted from the output pad. During a period of the first switch unit or the second switch unit operating from a first time to a second time, transistors in an output stage of the channel operational amplifier operate in a linear region of smaller resistance instead of a saturation region of larger resistance, and the initial switch is turned-off during the period and not started until the second time. The length of the period corresponds to the pulse width modulation.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: November 15, 2016
    Assignee: Raydium Semiconductor Corporation
    Inventor: Po-Cheng Lin
  • Patent number: 9491830
    Abstract: A compensation unit includes a current source unit, a current sink unit, a sensing resistor, a comparator, and a memory. The current source unit is configured to supply a first reference current to a first node. The current sink unit is configured to sink a second reference current from the first node. The sensing resistor is coupled between the first node and a second node. The comparator is configured to: compare a voltage at the first node with a voltage at the second node, and output a comparison result signal based on the comparison. The memory unit is configured to: store compensation data related to operational disparity of at least one organic light emitting diode and/or of at least one driving transistor, output the compensation data, and modify the compensation data based on the comparison result signal.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: November 8, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Wook Lee
  • Patent number: 9473208
    Abstract: A communication device is disclosed that includes an antenna circuit with coupling connections that are used interchangeably as a receive coupling connection and a transmit coupling connection for an RF signal. A driver maintains a constant voltage or a constant current on a first coupling connection of the antenna circuit based on a drive signal that includes an output voltage and an output current. A demodulator extracts modulation from the RF signal based on a fluctuating voltage or a fluctuating current on a second coupling connection of the antenna circuit.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: October 18, 2016
    Assignee: Broadcom Corporation
    Inventor: Alastair Lefley
  • Patent number: 9455671
    Abstract: In accordance with an embodiment, a system for amplifying a signal provided by a capacitive signal source includes a first voltage follower device, a second voltage follower device, and a first capacitor. The first voltage follower device includes an input terminal configured to be coupled to a first terminal of the capacitive signal source, and the second voltage follower device includes an input terminal coupled to the first output terminal of the first voltage follower device, and an output terminal coupled to a second output terminal of the first voltage follower device. Furthermore, first capacitor has a first end coupled to a first output terminal of the first voltage follower device, and a second end configured to be coupled to a second terminal of the capacitive signal source.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: September 27, 2016
    Assignee: Infineon Technologies AG
    Inventors: Michael Kropfitsch, Jose Luis Ceballos
  • Patent number: 9450549
    Abstract: A differential amplification circuit includes: a first input node; a second input node; a first output node; a second output node; a first transistor having a gate coupled to the first input node and a source coupled to a first node; a second transistor having a gate coupled to the second input node; a third transistor having a drain coupled to a drain of the first transistor; a fourth transistor having a gate coupled to a gate of the third transistor; a first resistor; a second resistor; a fifth transistor having a gate coupled to the drain of the first transistor; a sixth transistor having a gate coupled to the drain of the second transistor; a seventh transistor having a source coupled to the first node; an eighth transistor having a gate coupled to a gate of the seventh transistor; a third resistor; and a fourth resistor.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: September 20, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Kazuaki Oishi
  • Patent number: 9444410
    Abstract: A wide-band single-ended-to-differential low-noise amplifier using a push-pull architecture with an input node coupled to the sources of a first PMOS transistor and a first NMOS transistor, a positive output node coupled to the drains of the first PMOS transistor and the first NMOS transistor, a negative output node coupled to the drains of a second PMOS transistor and a second NMOS transistor, and bias circuitry coupled to the gates of the first and second PMOS and first and second NMOS transistors. The source of the first PMOS transistor is coupled to the gate of the second PMOS transistor, the source of the first NMOS transistor is coupled to the gate of the second NMOS transistor, the source of the second PMOS transistor is coupled to a first supply voltage, and the source of the second NMOS transistor is coupled to a second supply voltage.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: September 13, 2016
    Assignee: AltoBeam Inc.
    Inventors: Renjie Zhou, Xiang Guan
  • Patent number: 9438189
    Abstract: A low voltage multi-stage amplifier is described. The low voltage multi-stage amplifier includes one or more prior stages. The low voltage multi-stage amplifier also includes a supply stage. The low voltage multi-stage amplifier further includes an output stage that operates with a supply voltage as low as a sum of a threshold voltage of a first transistor in the output stage and a saturation voltage of a second transistor of the supply stage. The supply stage supplies the output stage.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 6, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Vijayakumar Dhanasekaran
  • Patent number: 9431971
    Abstract: In an example, a differential amplifier is disclosed that is configured to realize low noise with decreased overall system current. The differential amplifier may include a first amplifier stage and a second amplifier stage arranged in series, wherein a pull-up current iH flowing as a single bias current iB=iH flows into the first stage. A single pull-down current iT sources to ground from the second stage, wherein iH=iT=iB substantially. In certain embodiments, the transconductance of the second stage may be increased by providing two transconductors coupled at their base nodes.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: August 30, 2016
    Assignee: ANALOG DEVICES, INC.
    Inventor: Daniel Rey-Losada